Marc Zyngier | 1a89dd9 | 2013-01-21 19:36:12 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 ARM Ltd. |
| 3 | * Author: Marc Zyngier <marc.zyngier@arm.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program; if not, write to the Free Software |
| 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 17 | */ |
| 18 | |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 19 | #include <linux/cpu.h> |
Marc Zyngier | 1a89dd9 | 2013-01-21 19:36:12 -0500 | [diff] [blame] | 20 | #include <linux/kvm.h> |
| 21 | #include <linux/kvm_host.h> |
| 22 | #include <linux/interrupt.h> |
| 23 | #include <linux/io.h> |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 24 | #include <linux/of.h> |
| 25 | #include <linux/of_address.h> |
| 26 | #include <linux/of_irq.h> |
Christoffer Dall | 2a2f3e26 | 2014-02-02 13:41:02 -0800 | [diff] [blame] | 27 | #include <linux/uaccess.h> |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 28 | |
| 29 | #include <linux/irqchip/arm-gic.h> |
| 30 | |
Marc Zyngier | 1a89dd9 | 2013-01-21 19:36:12 -0500 | [diff] [blame] | 31 | #include <asm/kvm_emulate.h> |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 32 | #include <asm/kvm_arm.h> |
| 33 | #include <asm/kvm_mmu.h> |
Marc Zyngier | 1a89dd9 | 2013-01-21 19:36:12 -0500 | [diff] [blame] | 34 | |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 35 | /* |
| 36 | * How the whole thing works (courtesy of Christoffer Dall): |
| 37 | * |
| 38 | * - At any time, the dist->irq_pending_on_cpu is the oracle that knows if |
Christoffer Dall | 7e36291 | 2014-06-14 22:34:04 +0200 | [diff] [blame] | 39 | * something is pending on the CPU interface. |
| 40 | * - Interrupts that are pending on the distributor are stored on the |
| 41 | * vgic.irq_pending vgic bitmap (this bitmap is updated by both user land |
| 42 | * ioctls and guest mmio ops, and other in-kernel peripherals such as the |
| 43 | * arch. timers). |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 44 | * - Every time the bitmap changes, the irq_pending_on_cpu oracle is |
| 45 | * recalculated |
| 46 | * - To calculate the oracle, we need info for each cpu from |
| 47 | * compute_pending_for_cpu, which considers: |
Christoffer Dall | 227844f | 2014-06-09 12:27:18 +0200 | [diff] [blame] | 48 | * - PPI: dist->irq_pending & dist->irq_enable |
| 49 | * - SPI: dist->irq_pending & dist->irq_enable & dist->irq_spi_target |
Christoffer Dall | 7e36291 | 2014-06-14 22:34:04 +0200 | [diff] [blame] | 50 | * - irq_spi_target is a 'formatted' version of the GICD_ITARGETSRn |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 51 | * registers, stored on each vcpu. We only keep one bit of |
| 52 | * information per interrupt, making sure that only one vcpu can |
| 53 | * accept the interrupt. |
Christoffer Dall | 7e36291 | 2014-06-14 22:34:04 +0200 | [diff] [blame] | 54 | * - If any of the above state changes, we must recalculate the oracle. |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 55 | * - The same is true when injecting an interrupt, except that we only |
| 56 | * consider a single interrupt at a time. The irq_spi_cpu array |
| 57 | * contains the target CPU for each SPI. |
| 58 | * |
| 59 | * The handling of level interrupts adds some extra complexity. We |
| 60 | * need to track when the interrupt has been EOIed, so we can sample |
| 61 | * the 'line' again. This is achieved as such: |
| 62 | * |
| 63 | * - When a level interrupt is moved onto a vcpu, the corresponding |
Christoffer Dall | dbf20f9 | 2014-06-09 12:55:13 +0200 | [diff] [blame] | 64 | * bit in irq_queued is set. As long as this bit is set, the line |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 65 | * will be ignored for further interrupts. The interrupt is injected |
| 66 | * into the vcpu with the GICH_LR_EOI bit set (generate a |
| 67 | * maintenance interrupt on EOI). |
| 68 | * - When the interrupt is EOIed, the maintenance interrupt fires, |
Christoffer Dall | dbf20f9 | 2014-06-09 12:55:13 +0200 | [diff] [blame] | 69 | * and clears the corresponding bit in irq_queued. This allows the |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 70 | * interrupt line to be sampled again. |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 71 | * - Note that level-triggered interrupts can also be set to pending from |
| 72 | * writes to GICD_ISPENDRn and lowering the external input line does not |
| 73 | * cause the interrupt to become inactive in such a situation. |
| 74 | * Conversely, writes to GICD_ICPENDRn do not cause the interrupt to become |
| 75 | * inactive as long as the external input line is held high. |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 76 | */ |
| 77 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 78 | #include "vgic.h" |
Christoffer Dall | 330690c | 2013-01-21 19:36:13 -0500 | [diff] [blame] | 79 | |
Christoffer Dall | fa20f5ae | 2013-09-23 14:55:57 -0700 | [diff] [blame] | 80 | #define GICC_ARCH_VERSION_V2 0x2 |
| 81 | |
Marc Zyngier | a1fcb44 | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 82 | static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu); |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 83 | static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu); |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 84 | static u8 *vgic_get_sgi_sources(struct vgic_dist *dist, int vcpu_id, int sgi); |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 85 | static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg); |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 86 | static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr); |
| 87 | static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr, struct vgic_lr lr_desc); |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 88 | |
Marc Zyngier | 8f186d5 | 2014-02-04 18:13:03 +0000 | [diff] [blame] | 89 | static const struct vgic_ops *vgic_ops; |
| 90 | static const struct vgic_params *vgic; |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 91 | |
Andre Przywara | b26e5fd | 2014-06-02 16:19:12 +0200 | [diff] [blame] | 92 | static void add_sgi_source(struct kvm_vcpu *vcpu, int irq, int source) |
| 93 | { |
| 94 | vcpu->kvm->arch.vgic.vm_ops.add_sgi_source(vcpu, irq, source); |
| 95 | } |
| 96 | |
| 97 | static bool queue_sgi(struct kvm_vcpu *vcpu, int irq) |
| 98 | { |
| 99 | return vcpu->kvm->arch.vgic.vm_ops.queue_sgi(vcpu, irq); |
| 100 | } |
| 101 | |
| 102 | int kvm_vgic_map_resources(struct kvm *kvm) |
| 103 | { |
| 104 | return kvm->arch.vgic.vm_ops.map_resources(kvm, vgic); |
| 105 | } |
| 106 | |
Victor Kamensky | 9662fb4 | 2014-06-12 09:30:10 -0700 | [diff] [blame] | 107 | /* |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 108 | * struct vgic_bitmap contains a bitmap made of unsigned longs, but |
| 109 | * extracts u32s out of them. |
Victor Kamensky | 9662fb4 | 2014-06-12 09:30:10 -0700 | [diff] [blame] | 110 | * |
| 111 | * This does not work on 64-bit BE systems, because the bitmap access |
| 112 | * will store two consecutive 32-bit words with the higher-addressed |
| 113 | * register's bits at the lower index and the lower-addressed register's |
| 114 | * bits at the higher index. |
| 115 | * |
| 116 | * Therefore, swizzle the register index when accessing the 32-bit word |
| 117 | * registers to access the right register's value. |
| 118 | */ |
| 119 | #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 64 |
| 120 | #define REG_OFFSET_SWIZZLE 1 |
| 121 | #else |
| 122 | #define REG_OFFSET_SWIZZLE 0 |
| 123 | #endif |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 124 | |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 125 | static int vgic_init_bitmap(struct vgic_bitmap *b, int nr_cpus, int nr_irqs) |
| 126 | { |
| 127 | int nr_longs; |
| 128 | |
| 129 | nr_longs = nr_cpus + BITS_TO_LONGS(nr_irqs - VGIC_NR_PRIVATE_IRQS); |
| 130 | |
| 131 | b->private = kzalloc(sizeof(unsigned long) * nr_longs, GFP_KERNEL); |
| 132 | if (!b->private) |
| 133 | return -ENOMEM; |
| 134 | |
| 135 | b->shared = b->private + nr_cpus; |
| 136 | |
| 137 | return 0; |
| 138 | } |
| 139 | |
| 140 | static void vgic_free_bitmap(struct vgic_bitmap *b) |
| 141 | { |
| 142 | kfree(b->private); |
| 143 | b->private = NULL; |
| 144 | b->shared = NULL; |
| 145 | } |
| 146 | |
Christoffer Dall | 2df36a5 | 2014-09-28 16:04:26 +0200 | [diff] [blame] | 147 | /* |
| 148 | * Call this function to convert a u64 value to an unsigned long * bitmask |
| 149 | * in a way that works on both 32-bit and 64-bit LE and BE platforms. |
| 150 | * |
| 151 | * Warning: Calling this function may modify *val. |
| 152 | */ |
| 153 | static unsigned long *u64_to_bitmask(u64 *val) |
| 154 | { |
| 155 | #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 32 |
| 156 | *val = (*val >> 32) | (*val << 32); |
| 157 | #endif |
| 158 | return (unsigned long *)val; |
| 159 | } |
| 160 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 161 | u32 *vgic_bitmap_get_reg(struct vgic_bitmap *x, int cpuid, u32 offset) |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 162 | { |
| 163 | offset >>= 2; |
| 164 | if (!offset) |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 165 | return (u32 *)(x->private + cpuid) + REG_OFFSET_SWIZZLE; |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 166 | else |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 167 | return (u32 *)(x->shared) + ((offset - 1) ^ REG_OFFSET_SWIZZLE); |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 168 | } |
| 169 | |
| 170 | static int vgic_bitmap_get_irq_val(struct vgic_bitmap *x, |
| 171 | int cpuid, int irq) |
| 172 | { |
| 173 | if (irq < VGIC_NR_PRIVATE_IRQS) |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 174 | return test_bit(irq, x->private + cpuid); |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 175 | |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 176 | return test_bit(irq - VGIC_NR_PRIVATE_IRQS, x->shared); |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 177 | } |
| 178 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 179 | void vgic_bitmap_set_irq_val(struct vgic_bitmap *x, int cpuid, |
| 180 | int irq, int val) |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 181 | { |
| 182 | unsigned long *reg; |
| 183 | |
| 184 | if (irq < VGIC_NR_PRIVATE_IRQS) { |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 185 | reg = x->private + cpuid; |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 186 | } else { |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 187 | reg = x->shared; |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 188 | irq -= VGIC_NR_PRIVATE_IRQS; |
| 189 | } |
| 190 | |
| 191 | if (val) |
| 192 | set_bit(irq, reg); |
| 193 | else |
| 194 | clear_bit(irq, reg); |
| 195 | } |
| 196 | |
| 197 | static unsigned long *vgic_bitmap_get_cpu_map(struct vgic_bitmap *x, int cpuid) |
| 198 | { |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 199 | return x->private + cpuid; |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 200 | } |
| 201 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 202 | unsigned long *vgic_bitmap_get_shared_map(struct vgic_bitmap *x) |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 203 | { |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 204 | return x->shared; |
| 205 | } |
| 206 | |
| 207 | static int vgic_init_bytemap(struct vgic_bytemap *x, int nr_cpus, int nr_irqs) |
| 208 | { |
| 209 | int size; |
| 210 | |
| 211 | size = nr_cpus * VGIC_NR_PRIVATE_IRQS; |
| 212 | size += nr_irqs - VGIC_NR_PRIVATE_IRQS; |
| 213 | |
| 214 | x->private = kzalloc(size, GFP_KERNEL); |
| 215 | if (!x->private) |
| 216 | return -ENOMEM; |
| 217 | |
| 218 | x->shared = x->private + nr_cpus * VGIC_NR_PRIVATE_IRQS / sizeof(u32); |
| 219 | return 0; |
| 220 | } |
| 221 | |
| 222 | static void vgic_free_bytemap(struct vgic_bytemap *b) |
| 223 | { |
| 224 | kfree(b->private); |
| 225 | b->private = NULL; |
| 226 | b->shared = NULL; |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 227 | } |
| 228 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 229 | u32 *vgic_bytemap_get_reg(struct vgic_bytemap *x, int cpuid, u32 offset) |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 230 | { |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 231 | u32 *reg; |
| 232 | |
| 233 | if (offset < VGIC_NR_PRIVATE_IRQS) { |
| 234 | reg = x->private; |
| 235 | offset += cpuid * VGIC_NR_PRIVATE_IRQS; |
| 236 | } else { |
| 237 | reg = x->shared; |
| 238 | offset -= VGIC_NR_PRIVATE_IRQS; |
| 239 | } |
| 240 | |
| 241 | return reg + (offset / sizeof(u32)); |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 242 | } |
| 243 | |
| 244 | #define VGIC_CFG_LEVEL 0 |
| 245 | #define VGIC_CFG_EDGE 1 |
| 246 | |
| 247 | static bool vgic_irq_is_edge(struct kvm_vcpu *vcpu, int irq) |
| 248 | { |
| 249 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 250 | int irq_val; |
| 251 | |
| 252 | irq_val = vgic_bitmap_get_irq_val(&dist->irq_cfg, vcpu->vcpu_id, irq); |
| 253 | return irq_val == VGIC_CFG_EDGE; |
| 254 | } |
| 255 | |
| 256 | static int vgic_irq_is_enabled(struct kvm_vcpu *vcpu, int irq) |
| 257 | { |
| 258 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 259 | |
| 260 | return vgic_bitmap_get_irq_val(&dist->irq_enabled, vcpu->vcpu_id, irq); |
| 261 | } |
| 262 | |
Christoffer Dall | dbf20f9 | 2014-06-09 12:55:13 +0200 | [diff] [blame] | 263 | static int vgic_irq_is_queued(struct kvm_vcpu *vcpu, int irq) |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 264 | { |
| 265 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 266 | |
Christoffer Dall | dbf20f9 | 2014-06-09 12:55:13 +0200 | [diff] [blame] | 267 | return vgic_bitmap_get_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 268 | } |
| 269 | |
Christoffer Dall | dbf20f9 | 2014-06-09 12:55:13 +0200 | [diff] [blame] | 270 | static void vgic_irq_set_queued(struct kvm_vcpu *vcpu, int irq) |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 271 | { |
| 272 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 273 | |
Christoffer Dall | dbf20f9 | 2014-06-09 12:55:13 +0200 | [diff] [blame] | 274 | vgic_bitmap_set_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq, 1); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 275 | } |
| 276 | |
Christoffer Dall | dbf20f9 | 2014-06-09 12:55:13 +0200 | [diff] [blame] | 277 | static void vgic_irq_clear_queued(struct kvm_vcpu *vcpu, int irq) |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 278 | { |
| 279 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 280 | |
Christoffer Dall | dbf20f9 | 2014-06-09 12:55:13 +0200 | [diff] [blame] | 281 | vgic_bitmap_set_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq, 0); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 282 | } |
| 283 | |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 284 | static int vgic_dist_irq_get_level(struct kvm_vcpu *vcpu, int irq) |
| 285 | { |
| 286 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 287 | |
| 288 | return vgic_bitmap_get_irq_val(&dist->irq_level, vcpu->vcpu_id, irq); |
| 289 | } |
| 290 | |
| 291 | static void vgic_dist_irq_set_level(struct kvm_vcpu *vcpu, int irq) |
| 292 | { |
| 293 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 294 | |
| 295 | vgic_bitmap_set_irq_val(&dist->irq_level, vcpu->vcpu_id, irq, 1); |
| 296 | } |
| 297 | |
| 298 | static void vgic_dist_irq_clear_level(struct kvm_vcpu *vcpu, int irq) |
| 299 | { |
| 300 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 301 | |
| 302 | vgic_bitmap_set_irq_val(&dist->irq_level, vcpu->vcpu_id, irq, 0); |
| 303 | } |
| 304 | |
| 305 | static int vgic_dist_irq_soft_pend(struct kvm_vcpu *vcpu, int irq) |
| 306 | { |
| 307 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 308 | |
| 309 | return vgic_bitmap_get_irq_val(&dist->irq_soft_pend, vcpu->vcpu_id, irq); |
| 310 | } |
| 311 | |
| 312 | static void vgic_dist_irq_clear_soft_pend(struct kvm_vcpu *vcpu, int irq) |
| 313 | { |
| 314 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 315 | |
| 316 | vgic_bitmap_set_irq_val(&dist->irq_soft_pend, vcpu->vcpu_id, irq, 0); |
| 317 | } |
| 318 | |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 319 | static int vgic_dist_irq_is_pending(struct kvm_vcpu *vcpu, int irq) |
| 320 | { |
| 321 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 322 | |
Christoffer Dall | 227844f | 2014-06-09 12:27:18 +0200 | [diff] [blame] | 323 | return vgic_bitmap_get_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 324 | } |
| 325 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 326 | void vgic_dist_irq_set_pending(struct kvm_vcpu *vcpu, int irq) |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 327 | { |
| 328 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 329 | |
Christoffer Dall | 227844f | 2014-06-09 12:27:18 +0200 | [diff] [blame] | 330 | vgic_bitmap_set_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq, 1); |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 331 | } |
| 332 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 333 | void vgic_dist_irq_clear_pending(struct kvm_vcpu *vcpu, int irq) |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 334 | { |
| 335 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 336 | |
Christoffer Dall | 227844f | 2014-06-09 12:27:18 +0200 | [diff] [blame] | 337 | vgic_bitmap_set_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq, 0); |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 338 | } |
| 339 | |
| 340 | static void vgic_cpu_irq_set(struct kvm_vcpu *vcpu, int irq) |
| 341 | { |
| 342 | if (irq < VGIC_NR_PRIVATE_IRQS) |
| 343 | set_bit(irq, vcpu->arch.vgic_cpu.pending_percpu); |
| 344 | else |
| 345 | set_bit(irq - VGIC_NR_PRIVATE_IRQS, |
| 346 | vcpu->arch.vgic_cpu.pending_shared); |
| 347 | } |
| 348 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 349 | void vgic_cpu_irq_clear(struct kvm_vcpu *vcpu, int irq) |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 350 | { |
| 351 | if (irq < VGIC_NR_PRIVATE_IRQS) |
| 352 | clear_bit(irq, vcpu->arch.vgic_cpu.pending_percpu); |
| 353 | else |
| 354 | clear_bit(irq - VGIC_NR_PRIVATE_IRQS, |
| 355 | vcpu->arch.vgic_cpu.pending_shared); |
| 356 | } |
| 357 | |
Christoffer Dall | dbf20f9 | 2014-06-09 12:55:13 +0200 | [diff] [blame] | 358 | static bool vgic_can_sample_irq(struct kvm_vcpu *vcpu, int irq) |
| 359 | { |
| 360 | return vgic_irq_is_edge(vcpu, irq) || !vgic_irq_is_queued(vcpu, irq); |
| 361 | } |
| 362 | |
Marc Zyngier | 1a89dd9 | 2013-01-21 19:36:12 -0500 | [diff] [blame] | 363 | /** |
| 364 | * vgic_reg_access - access vgic register |
| 365 | * @mmio: pointer to the data describing the mmio access |
| 366 | * @reg: pointer to the virtual backing of vgic distributor data |
| 367 | * @offset: least significant 2 bits used for word offset |
| 368 | * @mode: ACCESS_ mode (see defines above) |
| 369 | * |
| 370 | * Helper to make vgic register access easier using one of the access |
| 371 | * modes defined for vgic register access |
| 372 | * (read,raz,write-ignored,setbit,clearbit,write) |
| 373 | */ |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 374 | void vgic_reg_access(struct kvm_exit_mmio *mmio, u32 *reg, |
| 375 | phys_addr_t offset, int mode) |
Marc Zyngier | 1a89dd9 | 2013-01-21 19:36:12 -0500 | [diff] [blame] | 376 | { |
| 377 | int word_offset = (offset & 3) * 8; |
| 378 | u32 mask = (1UL << (mmio->len * 8)) - 1; |
| 379 | u32 regval; |
| 380 | |
| 381 | /* |
| 382 | * Any alignment fault should have been delivered to the guest |
| 383 | * directly (ARM ARM B3.12.7 "Prioritization of aborts"). |
| 384 | */ |
| 385 | |
| 386 | if (reg) { |
| 387 | regval = *reg; |
| 388 | } else { |
| 389 | BUG_ON(mode != (ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED)); |
| 390 | regval = 0; |
| 391 | } |
| 392 | |
| 393 | if (mmio->is_write) { |
| 394 | u32 data = mmio_data_read(mmio, mask) << word_offset; |
| 395 | switch (ACCESS_WRITE_MASK(mode)) { |
| 396 | case ACCESS_WRITE_IGNORED: |
| 397 | return; |
| 398 | |
| 399 | case ACCESS_WRITE_SETBIT: |
| 400 | regval |= data; |
| 401 | break; |
| 402 | |
| 403 | case ACCESS_WRITE_CLEARBIT: |
| 404 | regval &= ~data; |
| 405 | break; |
| 406 | |
| 407 | case ACCESS_WRITE_VALUE: |
| 408 | regval = (regval & ~(mask << word_offset)) | data; |
| 409 | break; |
| 410 | } |
| 411 | *reg = regval; |
| 412 | } else { |
| 413 | switch (ACCESS_READ_MASK(mode)) { |
| 414 | case ACCESS_READ_RAZ: |
| 415 | regval = 0; |
| 416 | /* fall through */ |
| 417 | |
| 418 | case ACCESS_READ_VALUE: |
| 419 | mmio_data_write(mmio, mask, regval >> word_offset); |
| 420 | } |
| 421 | } |
| 422 | } |
| 423 | |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 424 | static bool handle_mmio_misc(struct kvm_vcpu *vcpu, |
| 425 | struct kvm_exit_mmio *mmio, phys_addr_t offset) |
| 426 | { |
| 427 | u32 reg; |
| 428 | u32 word_offset = offset & 3; |
| 429 | |
| 430 | switch (offset & ~3) { |
Christoffer Dall | fa20f5ae | 2013-09-23 14:55:57 -0700 | [diff] [blame] | 431 | case 0: /* GICD_CTLR */ |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 432 | reg = vcpu->kvm->arch.vgic.enabled; |
| 433 | vgic_reg_access(mmio, ®, word_offset, |
| 434 | ACCESS_READ_VALUE | ACCESS_WRITE_VALUE); |
| 435 | if (mmio->is_write) { |
| 436 | vcpu->kvm->arch.vgic.enabled = reg & 1; |
| 437 | vgic_update_state(vcpu->kvm); |
| 438 | return true; |
| 439 | } |
| 440 | break; |
| 441 | |
Christoffer Dall | fa20f5ae | 2013-09-23 14:55:57 -0700 | [diff] [blame] | 442 | case 4: /* GICD_TYPER */ |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 443 | reg = (atomic_read(&vcpu->kvm->online_vcpus) - 1) << 5; |
Marc Zyngier | 5fb66da | 2014-07-08 12:09:05 +0100 | [diff] [blame] | 444 | reg |= (vcpu->kvm->arch.vgic.nr_irqs >> 5) - 1; |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 445 | vgic_reg_access(mmio, ®, word_offset, |
| 446 | ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED); |
| 447 | break; |
| 448 | |
Christoffer Dall | fa20f5ae | 2013-09-23 14:55:57 -0700 | [diff] [blame] | 449 | case 8: /* GICD_IIDR */ |
| 450 | reg = (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0); |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 451 | vgic_reg_access(mmio, ®, word_offset, |
| 452 | ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED); |
| 453 | break; |
| 454 | } |
| 455 | |
| 456 | return false; |
| 457 | } |
| 458 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 459 | bool handle_mmio_raz_wi(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio, |
| 460 | phys_addr_t offset) |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 461 | { |
| 462 | vgic_reg_access(mmio, NULL, offset, |
| 463 | ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED); |
| 464 | return false; |
| 465 | } |
| 466 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 467 | bool vgic_handle_enable_reg(struct kvm *kvm, struct kvm_exit_mmio *mmio, |
| 468 | phys_addr_t offset, int vcpu_id, int access) |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 469 | { |
Andre Przywara | d97f683 | 2014-06-11 14:11:49 +0200 | [diff] [blame] | 470 | u32 *reg; |
| 471 | int mode = ACCESS_READ_VALUE | access; |
| 472 | struct kvm_vcpu *target_vcpu = kvm_get_vcpu(kvm, vcpu_id); |
| 473 | |
| 474 | reg = vgic_bitmap_get_reg(&kvm->arch.vgic.irq_enabled, vcpu_id, offset); |
| 475 | vgic_reg_access(mmio, reg, offset, mode); |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 476 | if (mmio->is_write) { |
Andre Przywara | d97f683 | 2014-06-11 14:11:49 +0200 | [diff] [blame] | 477 | if (access & ACCESS_WRITE_CLEARBIT) { |
| 478 | if (offset < 4) /* Force SGI enabled */ |
| 479 | *reg |= 0xffff; |
| 480 | vgic_retire_disabled_irqs(target_vcpu); |
| 481 | } |
| 482 | vgic_update_state(kvm); |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 483 | return true; |
| 484 | } |
| 485 | |
| 486 | return false; |
| 487 | } |
| 488 | |
Andre Przywara | d97f683 | 2014-06-11 14:11:49 +0200 | [diff] [blame] | 489 | static bool handle_mmio_set_enable_reg(struct kvm_vcpu *vcpu, |
| 490 | struct kvm_exit_mmio *mmio, |
| 491 | phys_addr_t offset) |
| 492 | { |
| 493 | return vgic_handle_enable_reg(vcpu->kvm, mmio, offset, |
| 494 | vcpu->vcpu_id, ACCESS_WRITE_SETBIT); |
| 495 | } |
| 496 | |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 497 | static bool handle_mmio_clear_enable_reg(struct kvm_vcpu *vcpu, |
| 498 | struct kvm_exit_mmio *mmio, |
| 499 | phys_addr_t offset) |
| 500 | { |
Andre Przywara | d97f683 | 2014-06-11 14:11:49 +0200 | [diff] [blame] | 501 | return vgic_handle_enable_reg(vcpu->kvm, mmio, offset, |
| 502 | vcpu->vcpu_id, ACCESS_WRITE_CLEARBIT); |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 503 | } |
| 504 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 505 | bool vgic_handle_set_pending_reg(struct kvm *kvm, |
| 506 | struct kvm_exit_mmio *mmio, |
| 507 | phys_addr_t offset, int vcpu_id) |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 508 | { |
Christoffer Dall | 9da48b5 | 2014-06-14 22:30:45 +0200 | [diff] [blame] | 509 | u32 *reg, orig; |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 510 | u32 level_mask; |
Andre Przywara | d97f683 | 2014-06-11 14:11:49 +0200 | [diff] [blame] | 511 | int mode = ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT; |
| 512 | struct vgic_dist *dist = &kvm->arch.vgic; |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 513 | |
Andre Przywara | d97f683 | 2014-06-11 14:11:49 +0200 | [diff] [blame] | 514 | reg = vgic_bitmap_get_reg(&dist->irq_cfg, vcpu_id, offset); |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 515 | level_mask = (~(*reg)); |
| 516 | |
| 517 | /* Mark both level and edge triggered irqs as pending */ |
Andre Przywara | d97f683 | 2014-06-11 14:11:49 +0200 | [diff] [blame] | 518 | reg = vgic_bitmap_get_reg(&dist->irq_pending, vcpu_id, offset); |
Christoffer Dall | 9da48b5 | 2014-06-14 22:30:45 +0200 | [diff] [blame] | 519 | orig = *reg; |
Andre Przywara | d97f683 | 2014-06-11 14:11:49 +0200 | [diff] [blame] | 520 | vgic_reg_access(mmio, reg, offset, mode); |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 521 | |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 522 | if (mmio->is_write) { |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 523 | /* Set the soft-pending flag only for level-triggered irqs */ |
| 524 | reg = vgic_bitmap_get_reg(&dist->irq_soft_pend, |
Andre Przywara | d97f683 | 2014-06-11 14:11:49 +0200 | [diff] [blame] | 525 | vcpu_id, offset); |
| 526 | vgic_reg_access(mmio, reg, offset, mode); |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 527 | *reg &= level_mask; |
| 528 | |
Christoffer Dall | 9da48b5 | 2014-06-14 22:30:45 +0200 | [diff] [blame] | 529 | /* Ignore writes to SGIs */ |
| 530 | if (offset < 2) { |
| 531 | *reg &= ~0xffff; |
| 532 | *reg |= orig & 0xffff; |
| 533 | } |
| 534 | |
Andre Przywara | d97f683 | 2014-06-11 14:11:49 +0200 | [diff] [blame] | 535 | vgic_update_state(kvm); |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 536 | return true; |
| 537 | } |
| 538 | |
| 539 | return false; |
| 540 | } |
| 541 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 542 | bool vgic_handle_clear_pending_reg(struct kvm *kvm, |
| 543 | struct kvm_exit_mmio *mmio, |
| 544 | phys_addr_t offset, int vcpu_id) |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 545 | { |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 546 | u32 *level_active; |
Christoffer Dall | 9da48b5 | 2014-06-14 22:30:45 +0200 | [diff] [blame] | 547 | u32 *reg, orig; |
Andre Przywara | d97f683 | 2014-06-11 14:11:49 +0200 | [diff] [blame] | 548 | int mode = ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT; |
| 549 | struct vgic_dist *dist = &kvm->arch.vgic; |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 550 | |
Andre Przywara | d97f683 | 2014-06-11 14:11:49 +0200 | [diff] [blame] | 551 | reg = vgic_bitmap_get_reg(&dist->irq_pending, vcpu_id, offset); |
Christoffer Dall | 9da48b5 | 2014-06-14 22:30:45 +0200 | [diff] [blame] | 552 | orig = *reg; |
Andre Przywara | d97f683 | 2014-06-11 14:11:49 +0200 | [diff] [blame] | 553 | vgic_reg_access(mmio, reg, offset, mode); |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 554 | if (mmio->is_write) { |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 555 | /* Re-set level triggered level-active interrupts */ |
| 556 | level_active = vgic_bitmap_get_reg(&dist->irq_level, |
Andre Przywara | d97f683 | 2014-06-11 14:11:49 +0200 | [diff] [blame] | 557 | vcpu_id, offset); |
| 558 | reg = vgic_bitmap_get_reg(&dist->irq_pending, vcpu_id, offset); |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 559 | *reg |= *level_active; |
| 560 | |
Christoffer Dall | 9da48b5 | 2014-06-14 22:30:45 +0200 | [diff] [blame] | 561 | /* Ignore writes to SGIs */ |
| 562 | if (offset < 2) { |
| 563 | *reg &= ~0xffff; |
| 564 | *reg |= orig & 0xffff; |
| 565 | } |
| 566 | |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 567 | /* Clear soft-pending flags */ |
| 568 | reg = vgic_bitmap_get_reg(&dist->irq_soft_pend, |
Andre Przywara | d97f683 | 2014-06-11 14:11:49 +0200 | [diff] [blame] | 569 | vcpu_id, offset); |
| 570 | vgic_reg_access(mmio, reg, offset, mode); |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 571 | |
Andre Przywara | d97f683 | 2014-06-11 14:11:49 +0200 | [diff] [blame] | 572 | vgic_update_state(kvm); |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 573 | return true; |
| 574 | } |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 575 | return false; |
| 576 | } |
| 577 | |
Andre Przywara | d97f683 | 2014-06-11 14:11:49 +0200 | [diff] [blame] | 578 | static bool handle_mmio_set_pending_reg(struct kvm_vcpu *vcpu, |
| 579 | struct kvm_exit_mmio *mmio, |
| 580 | phys_addr_t offset) |
| 581 | { |
| 582 | return vgic_handle_set_pending_reg(vcpu->kvm, mmio, offset, |
| 583 | vcpu->vcpu_id); |
| 584 | } |
| 585 | |
| 586 | static bool handle_mmio_clear_pending_reg(struct kvm_vcpu *vcpu, |
| 587 | struct kvm_exit_mmio *mmio, |
| 588 | phys_addr_t offset) |
| 589 | { |
| 590 | return vgic_handle_clear_pending_reg(vcpu->kvm, mmio, offset, |
| 591 | vcpu->vcpu_id); |
| 592 | } |
| 593 | |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 594 | static bool handle_mmio_priority_reg(struct kvm_vcpu *vcpu, |
| 595 | struct kvm_exit_mmio *mmio, |
| 596 | phys_addr_t offset) |
| 597 | { |
| 598 | u32 *reg = vgic_bytemap_get_reg(&vcpu->kvm->arch.vgic.irq_priority, |
| 599 | vcpu->vcpu_id, offset); |
| 600 | vgic_reg_access(mmio, reg, offset, |
| 601 | ACCESS_READ_VALUE | ACCESS_WRITE_VALUE); |
| 602 | return false; |
| 603 | } |
| 604 | |
| 605 | #define GICD_ITARGETSR_SIZE 32 |
| 606 | #define GICD_CPUTARGETS_BITS 8 |
| 607 | #define GICD_IRQS_PER_ITARGETSR (GICD_ITARGETSR_SIZE / GICD_CPUTARGETS_BITS) |
| 608 | static u32 vgic_get_target_reg(struct kvm *kvm, int irq) |
| 609 | { |
| 610 | struct vgic_dist *dist = &kvm->arch.vgic; |
Marc Zyngier | 986af8e | 2013-08-29 11:08:22 +0100 | [diff] [blame] | 611 | int i; |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 612 | u32 val = 0; |
| 613 | |
| 614 | irq -= VGIC_NR_PRIVATE_IRQS; |
| 615 | |
Marc Zyngier | 986af8e | 2013-08-29 11:08:22 +0100 | [diff] [blame] | 616 | for (i = 0; i < GICD_IRQS_PER_ITARGETSR; i++) |
| 617 | val |= 1 << (dist->irq_spi_cpu[irq + i] + i * 8); |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 618 | |
| 619 | return val; |
| 620 | } |
| 621 | |
| 622 | static void vgic_set_target_reg(struct kvm *kvm, u32 val, int irq) |
| 623 | { |
| 624 | struct vgic_dist *dist = &kvm->arch.vgic; |
| 625 | struct kvm_vcpu *vcpu; |
| 626 | int i, c; |
| 627 | unsigned long *bmap; |
| 628 | u32 target; |
| 629 | |
| 630 | irq -= VGIC_NR_PRIVATE_IRQS; |
| 631 | |
| 632 | /* |
| 633 | * Pick the LSB in each byte. This ensures we target exactly |
| 634 | * one vcpu per IRQ. If the byte is null, assume we target |
| 635 | * CPU0. |
| 636 | */ |
| 637 | for (i = 0; i < GICD_IRQS_PER_ITARGETSR; i++) { |
| 638 | int shift = i * GICD_CPUTARGETS_BITS; |
| 639 | target = ffs((val >> shift) & 0xffU); |
| 640 | target = target ? (target - 1) : 0; |
| 641 | dist->irq_spi_cpu[irq + i] = target; |
| 642 | kvm_for_each_vcpu(c, vcpu, kvm) { |
| 643 | bmap = vgic_bitmap_get_shared_map(&dist->irq_spi_target[c]); |
| 644 | if (c == target) |
| 645 | set_bit(irq + i, bmap); |
| 646 | else |
| 647 | clear_bit(irq + i, bmap); |
| 648 | } |
| 649 | } |
| 650 | } |
| 651 | |
| 652 | static bool handle_mmio_target_reg(struct kvm_vcpu *vcpu, |
| 653 | struct kvm_exit_mmio *mmio, |
| 654 | phys_addr_t offset) |
| 655 | { |
| 656 | u32 reg; |
| 657 | |
| 658 | /* We treat the banked interrupts targets as read-only */ |
| 659 | if (offset < 32) { |
| 660 | u32 roreg = 1 << vcpu->vcpu_id; |
| 661 | roreg |= roreg << 8; |
| 662 | roreg |= roreg << 16; |
| 663 | |
| 664 | vgic_reg_access(mmio, &roreg, offset, |
| 665 | ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED); |
| 666 | return false; |
| 667 | } |
| 668 | |
| 669 | reg = vgic_get_target_reg(vcpu->kvm, offset & ~3U); |
| 670 | vgic_reg_access(mmio, ®, offset, |
| 671 | ACCESS_READ_VALUE | ACCESS_WRITE_VALUE); |
| 672 | if (mmio->is_write) { |
| 673 | vgic_set_target_reg(vcpu->kvm, reg, offset & ~3U); |
| 674 | vgic_update_state(vcpu->kvm); |
| 675 | return true; |
| 676 | } |
| 677 | |
| 678 | return false; |
| 679 | } |
| 680 | |
| 681 | static u32 vgic_cfg_expand(u16 val) |
| 682 | { |
| 683 | u32 res = 0; |
| 684 | int i; |
| 685 | |
| 686 | /* |
| 687 | * Turn a 16bit value like abcd...mnop into a 32bit word |
| 688 | * a0b0c0d0...m0n0o0p0, which is what the HW cfg register is. |
| 689 | */ |
| 690 | for (i = 0; i < 16; i++) |
| 691 | res |= ((val >> i) & VGIC_CFG_EDGE) << (2 * i + 1); |
| 692 | |
| 693 | return res; |
| 694 | } |
| 695 | |
| 696 | static u16 vgic_cfg_compress(u32 val) |
| 697 | { |
| 698 | u16 res = 0; |
| 699 | int i; |
| 700 | |
| 701 | /* |
| 702 | * Turn a 32bit word a0b0c0d0...m0n0o0p0 into 16bit value like |
| 703 | * abcd...mnop which is what we really care about. |
| 704 | */ |
| 705 | for (i = 0; i < 16; i++) |
| 706 | res |= ((val >> (i * 2 + 1)) & VGIC_CFG_EDGE) << i; |
| 707 | |
| 708 | return res; |
| 709 | } |
| 710 | |
| 711 | /* |
| 712 | * The distributor uses 2 bits per IRQ for the CFG register, but the |
| 713 | * LSB is always 0. As such, we only keep the upper bit, and use the |
| 714 | * two above functions to compress/expand the bits |
| 715 | */ |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 716 | bool vgic_handle_cfg_reg(u32 *reg, struct kvm_exit_mmio *mmio, |
| 717 | phys_addr_t offset) |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 718 | { |
| 719 | u32 val; |
Marc Zyngier | 6545eae | 2013-08-29 11:08:23 +0100 | [diff] [blame] | 720 | |
Andre Przywara | f2ae85b | 2014-04-11 00:07:18 +0200 | [diff] [blame] | 721 | if (offset & 4) |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 722 | val = *reg >> 16; |
| 723 | else |
| 724 | val = *reg & 0xffff; |
| 725 | |
| 726 | val = vgic_cfg_expand(val); |
| 727 | vgic_reg_access(mmio, &val, offset, |
| 728 | ACCESS_READ_VALUE | ACCESS_WRITE_VALUE); |
| 729 | if (mmio->is_write) { |
Andre Przywara | f2ae85b | 2014-04-11 00:07:18 +0200 | [diff] [blame] | 730 | if (offset < 8) { |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 731 | *reg = ~0U; /* Force PPIs/SGIs to 1 */ |
| 732 | return false; |
| 733 | } |
| 734 | |
| 735 | val = vgic_cfg_compress(val); |
Andre Przywara | f2ae85b | 2014-04-11 00:07:18 +0200 | [diff] [blame] | 736 | if (offset & 4) { |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 737 | *reg &= 0xffff; |
| 738 | *reg |= val << 16; |
| 739 | } else { |
| 740 | *reg &= 0xffff << 16; |
| 741 | *reg |= val; |
| 742 | } |
| 743 | } |
| 744 | |
| 745 | return false; |
| 746 | } |
| 747 | |
Andre Przywara | d97f683 | 2014-06-11 14:11:49 +0200 | [diff] [blame] | 748 | static bool handle_mmio_cfg_reg(struct kvm_vcpu *vcpu, |
| 749 | struct kvm_exit_mmio *mmio, phys_addr_t offset) |
| 750 | { |
| 751 | u32 *reg; |
| 752 | |
| 753 | reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_cfg, |
| 754 | vcpu->vcpu_id, offset >> 1); |
| 755 | |
| 756 | return vgic_handle_cfg_reg(reg, mmio, offset); |
| 757 | } |
| 758 | |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 759 | static bool handle_mmio_sgi_reg(struct kvm_vcpu *vcpu, |
| 760 | struct kvm_exit_mmio *mmio, phys_addr_t offset) |
| 761 | { |
| 762 | u32 reg; |
| 763 | vgic_reg_access(mmio, ®, offset, |
| 764 | ACCESS_READ_RAZ | ACCESS_WRITE_VALUE); |
| 765 | if (mmio->is_write) { |
| 766 | vgic_dispatch_sgi(vcpu, reg); |
| 767 | vgic_update_state(vcpu->kvm); |
| 768 | return true; |
| 769 | } |
| 770 | |
| 771 | return false; |
| 772 | } |
| 773 | |
Andre Przywara | b26e5fd | 2014-06-02 16:19:12 +0200 | [diff] [blame] | 774 | static void vgic_v2_add_sgi_source(struct kvm_vcpu *vcpu, int irq, int source) |
| 775 | { |
| 776 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 777 | |
| 778 | *vgic_get_sgi_sources(dist, vcpu->vcpu_id, irq) |= 1 << source; |
| 779 | } |
| 780 | |
Christoffer Dall | cbd333a | 2013-11-15 20:51:31 -0800 | [diff] [blame] | 781 | /** |
| 782 | * vgic_unqueue_irqs - move pending IRQs from LRs to the distributor |
| 783 | * @vgic_cpu: Pointer to the vgic_cpu struct holding the LRs |
| 784 | * |
| 785 | * Move any pending IRQs that have already been assigned to LRs back to the |
| 786 | * emulated distributor state so that the complete emulated state can be read |
| 787 | * from the main emulation structures without investigating the LRs. |
| 788 | * |
| 789 | * Note that IRQs in the active state in the LRs get their pending state moved |
| 790 | * to the distributor but the active state stays in the LRs, because we don't |
| 791 | * track the active state on the distributor side. |
| 792 | */ |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 793 | void vgic_unqueue_irqs(struct kvm_vcpu *vcpu) |
Christoffer Dall | cbd333a | 2013-11-15 20:51:31 -0800 | [diff] [blame] | 794 | { |
Christoffer Dall | cbd333a | 2013-11-15 20:51:31 -0800 | [diff] [blame] | 795 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 796 | int i; |
Christoffer Dall | cbd333a | 2013-11-15 20:51:31 -0800 | [diff] [blame] | 797 | |
| 798 | for_each_set_bit(i, vgic_cpu->lr_used, vgic_cpu->nr_lr) { |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 799 | struct vgic_lr lr = vgic_get_lr(vcpu, i); |
Christoffer Dall | cbd333a | 2013-11-15 20:51:31 -0800 | [diff] [blame] | 800 | |
| 801 | /* |
| 802 | * There are three options for the state bits: |
| 803 | * |
| 804 | * 01: pending |
| 805 | * 10: active |
| 806 | * 11: pending and active |
| 807 | * |
| 808 | * If the LR holds only an active interrupt (not pending) then |
| 809 | * just leave it alone. |
| 810 | */ |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 811 | if ((lr.state & LR_STATE_MASK) == LR_STATE_ACTIVE) |
Christoffer Dall | cbd333a | 2013-11-15 20:51:31 -0800 | [diff] [blame] | 812 | continue; |
| 813 | |
| 814 | /* |
| 815 | * Reestablish the pending state on the distributor and the |
| 816 | * CPU interface. It may have already been pending, but that |
| 817 | * is fine, then we are only setting a few bits that were |
| 818 | * already set. |
| 819 | */ |
Christoffer Dall | 227844f | 2014-06-09 12:27:18 +0200 | [diff] [blame] | 820 | vgic_dist_irq_set_pending(vcpu, lr.irq); |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 821 | if (lr.irq < VGIC_NR_SGIS) |
Andre Przywara | b26e5fd | 2014-06-02 16:19:12 +0200 | [diff] [blame] | 822 | add_sgi_source(vcpu, lr.irq, lr.source); |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 823 | lr.state &= ~LR_STATE_PENDING; |
| 824 | vgic_set_lr(vcpu, i, lr); |
Christoffer Dall | cbd333a | 2013-11-15 20:51:31 -0800 | [diff] [blame] | 825 | |
| 826 | /* |
| 827 | * If there's no state left on the LR (it could still be |
| 828 | * active), then the LR does not hold any useful info and can |
| 829 | * be marked as free for other use. |
| 830 | */ |
Christoffer Dall | cced50c | 2014-06-14 22:37:33 +0200 | [diff] [blame] | 831 | if (!(lr.state & LR_STATE_MASK)) { |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 832 | vgic_retire_lr(i, lr.irq, vcpu); |
Christoffer Dall | cced50c | 2014-06-14 22:37:33 +0200 | [diff] [blame] | 833 | vgic_irq_clear_queued(vcpu, lr.irq); |
| 834 | } |
Christoffer Dall | cbd333a | 2013-11-15 20:51:31 -0800 | [diff] [blame] | 835 | |
| 836 | /* Finally update the VGIC state. */ |
| 837 | vgic_update_state(vcpu->kvm); |
| 838 | } |
| 839 | } |
| 840 | |
Christoffer Dall | 90a5355 | 2013-10-25 21:22:31 +0100 | [diff] [blame] | 841 | /* Handle reads of GICD_CPENDSGIRn and GICD_SPENDSGIRn */ |
| 842 | static bool read_set_clear_sgi_pend_reg(struct kvm_vcpu *vcpu, |
| 843 | struct kvm_exit_mmio *mmio, |
| 844 | phys_addr_t offset) |
Christoffer Dall | c07a019 | 2013-10-25 21:17:31 +0100 | [diff] [blame] | 845 | { |
Christoffer Dall | 90a5355 | 2013-10-25 21:22:31 +0100 | [diff] [blame] | 846 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 847 | int sgi; |
Christoffer Dall | 0fea6d7 | 2014-09-25 18:41:07 +0200 | [diff] [blame] | 848 | int min_sgi = (offset & ~0x3); |
Christoffer Dall | 90a5355 | 2013-10-25 21:22:31 +0100 | [diff] [blame] | 849 | int max_sgi = min_sgi + 3; |
| 850 | int vcpu_id = vcpu->vcpu_id; |
| 851 | u32 reg = 0; |
| 852 | |
| 853 | /* Copy source SGIs from distributor side */ |
| 854 | for (sgi = min_sgi; sgi <= max_sgi; sgi++) { |
| 855 | int shift = 8 * (sgi - min_sgi); |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 856 | reg |= ((u32)*vgic_get_sgi_sources(dist, vcpu_id, sgi)) << shift; |
Christoffer Dall | 90a5355 | 2013-10-25 21:22:31 +0100 | [diff] [blame] | 857 | } |
| 858 | |
| 859 | mmio_data_write(mmio, ~0, reg); |
Christoffer Dall | c07a019 | 2013-10-25 21:17:31 +0100 | [diff] [blame] | 860 | return false; |
| 861 | } |
| 862 | |
Christoffer Dall | 90a5355 | 2013-10-25 21:22:31 +0100 | [diff] [blame] | 863 | static bool write_set_clear_sgi_pend_reg(struct kvm_vcpu *vcpu, |
| 864 | struct kvm_exit_mmio *mmio, |
| 865 | phys_addr_t offset, bool set) |
| 866 | { |
| 867 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 868 | int sgi; |
Christoffer Dall | 0fea6d7 | 2014-09-25 18:41:07 +0200 | [diff] [blame] | 869 | int min_sgi = (offset & ~0x3); |
Christoffer Dall | 90a5355 | 2013-10-25 21:22:31 +0100 | [diff] [blame] | 870 | int max_sgi = min_sgi + 3; |
| 871 | int vcpu_id = vcpu->vcpu_id; |
| 872 | u32 reg; |
| 873 | bool updated = false; |
| 874 | |
| 875 | reg = mmio_data_read(mmio, ~0); |
| 876 | |
| 877 | /* Clear pending SGIs on the distributor */ |
| 878 | for (sgi = min_sgi; sgi <= max_sgi; sgi++) { |
| 879 | u8 mask = reg >> (8 * (sgi - min_sgi)); |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 880 | u8 *src = vgic_get_sgi_sources(dist, vcpu_id, sgi); |
Christoffer Dall | 90a5355 | 2013-10-25 21:22:31 +0100 | [diff] [blame] | 881 | if (set) { |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 882 | if ((*src & mask) != mask) |
Christoffer Dall | 90a5355 | 2013-10-25 21:22:31 +0100 | [diff] [blame] | 883 | updated = true; |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 884 | *src |= mask; |
Christoffer Dall | 90a5355 | 2013-10-25 21:22:31 +0100 | [diff] [blame] | 885 | } else { |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 886 | if (*src & mask) |
Christoffer Dall | 90a5355 | 2013-10-25 21:22:31 +0100 | [diff] [blame] | 887 | updated = true; |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 888 | *src &= ~mask; |
Christoffer Dall | 90a5355 | 2013-10-25 21:22:31 +0100 | [diff] [blame] | 889 | } |
| 890 | } |
| 891 | |
| 892 | if (updated) |
| 893 | vgic_update_state(vcpu->kvm); |
| 894 | |
| 895 | return updated; |
| 896 | } |
| 897 | |
Christoffer Dall | c07a019 | 2013-10-25 21:17:31 +0100 | [diff] [blame] | 898 | static bool handle_mmio_sgi_set(struct kvm_vcpu *vcpu, |
| 899 | struct kvm_exit_mmio *mmio, |
| 900 | phys_addr_t offset) |
| 901 | { |
Christoffer Dall | 90a5355 | 2013-10-25 21:22:31 +0100 | [diff] [blame] | 902 | if (!mmio->is_write) |
| 903 | return read_set_clear_sgi_pend_reg(vcpu, mmio, offset); |
| 904 | else |
| 905 | return write_set_clear_sgi_pend_reg(vcpu, mmio, offset, true); |
| 906 | } |
| 907 | |
| 908 | static bool handle_mmio_sgi_clear(struct kvm_vcpu *vcpu, |
| 909 | struct kvm_exit_mmio *mmio, |
| 910 | phys_addr_t offset) |
| 911 | { |
| 912 | if (!mmio->is_write) |
| 913 | return read_set_clear_sgi_pend_reg(vcpu, mmio, offset); |
| 914 | else |
| 915 | return write_set_clear_sgi_pend_reg(vcpu, mmio, offset, false); |
Christoffer Dall | c07a019 | 2013-10-25 21:17:31 +0100 | [diff] [blame] | 916 | } |
| 917 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 918 | static const struct kvm_mmio_range vgic_dist_ranges[] = { |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 919 | { |
| 920 | .base = GIC_DIST_CTRL, |
| 921 | .len = 12, |
Marc Zyngier | c3c9183 | 2014-07-08 12:09:04 +0100 | [diff] [blame] | 922 | .bits_per_irq = 0, |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 923 | .handle_mmio = handle_mmio_misc, |
| 924 | }, |
| 925 | { |
| 926 | .base = GIC_DIST_IGROUP, |
Marc Zyngier | c3c9183 | 2014-07-08 12:09:04 +0100 | [diff] [blame] | 927 | .len = VGIC_MAX_IRQS / 8, |
| 928 | .bits_per_irq = 1, |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 929 | .handle_mmio = handle_mmio_raz_wi, |
| 930 | }, |
| 931 | { |
| 932 | .base = GIC_DIST_ENABLE_SET, |
Marc Zyngier | c3c9183 | 2014-07-08 12:09:04 +0100 | [diff] [blame] | 933 | .len = VGIC_MAX_IRQS / 8, |
| 934 | .bits_per_irq = 1, |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 935 | .handle_mmio = handle_mmio_set_enable_reg, |
| 936 | }, |
| 937 | { |
| 938 | .base = GIC_DIST_ENABLE_CLEAR, |
Marc Zyngier | c3c9183 | 2014-07-08 12:09:04 +0100 | [diff] [blame] | 939 | .len = VGIC_MAX_IRQS / 8, |
| 940 | .bits_per_irq = 1, |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 941 | .handle_mmio = handle_mmio_clear_enable_reg, |
| 942 | }, |
| 943 | { |
| 944 | .base = GIC_DIST_PENDING_SET, |
Marc Zyngier | c3c9183 | 2014-07-08 12:09:04 +0100 | [diff] [blame] | 945 | .len = VGIC_MAX_IRQS / 8, |
| 946 | .bits_per_irq = 1, |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 947 | .handle_mmio = handle_mmio_set_pending_reg, |
| 948 | }, |
| 949 | { |
| 950 | .base = GIC_DIST_PENDING_CLEAR, |
Marc Zyngier | c3c9183 | 2014-07-08 12:09:04 +0100 | [diff] [blame] | 951 | .len = VGIC_MAX_IRQS / 8, |
| 952 | .bits_per_irq = 1, |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 953 | .handle_mmio = handle_mmio_clear_pending_reg, |
| 954 | }, |
| 955 | { |
| 956 | .base = GIC_DIST_ACTIVE_SET, |
Marc Zyngier | c3c9183 | 2014-07-08 12:09:04 +0100 | [diff] [blame] | 957 | .len = VGIC_MAX_IRQS / 8, |
| 958 | .bits_per_irq = 1, |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 959 | .handle_mmio = handle_mmio_raz_wi, |
| 960 | }, |
| 961 | { |
| 962 | .base = GIC_DIST_ACTIVE_CLEAR, |
Marc Zyngier | c3c9183 | 2014-07-08 12:09:04 +0100 | [diff] [blame] | 963 | .len = VGIC_MAX_IRQS / 8, |
| 964 | .bits_per_irq = 1, |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 965 | .handle_mmio = handle_mmio_raz_wi, |
| 966 | }, |
| 967 | { |
| 968 | .base = GIC_DIST_PRI, |
Marc Zyngier | c3c9183 | 2014-07-08 12:09:04 +0100 | [diff] [blame] | 969 | .len = VGIC_MAX_IRQS, |
| 970 | .bits_per_irq = 8, |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 971 | .handle_mmio = handle_mmio_priority_reg, |
| 972 | }, |
| 973 | { |
| 974 | .base = GIC_DIST_TARGET, |
Marc Zyngier | c3c9183 | 2014-07-08 12:09:04 +0100 | [diff] [blame] | 975 | .len = VGIC_MAX_IRQS, |
| 976 | .bits_per_irq = 8, |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 977 | .handle_mmio = handle_mmio_target_reg, |
| 978 | }, |
| 979 | { |
| 980 | .base = GIC_DIST_CONFIG, |
Marc Zyngier | c3c9183 | 2014-07-08 12:09:04 +0100 | [diff] [blame] | 981 | .len = VGIC_MAX_IRQS / 4, |
| 982 | .bits_per_irq = 2, |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 983 | .handle_mmio = handle_mmio_cfg_reg, |
| 984 | }, |
| 985 | { |
| 986 | .base = GIC_DIST_SOFTINT, |
| 987 | .len = 4, |
| 988 | .handle_mmio = handle_mmio_sgi_reg, |
| 989 | }, |
Christoffer Dall | c07a019 | 2013-10-25 21:17:31 +0100 | [diff] [blame] | 990 | { |
| 991 | .base = GIC_DIST_SGI_PENDING_CLEAR, |
| 992 | .len = VGIC_NR_SGIS, |
| 993 | .handle_mmio = handle_mmio_sgi_clear, |
| 994 | }, |
| 995 | { |
| 996 | .base = GIC_DIST_SGI_PENDING_SET, |
| 997 | .len = VGIC_NR_SGIS, |
| 998 | .handle_mmio = handle_mmio_sgi_set, |
| 999 | }, |
Marc Zyngier | 1a89dd9 | 2013-01-21 19:36:12 -0500 | [diff] [blame] | 1000 | {} |
| 1001 | }; |
| 1002 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 1003 | const |
| 1004 | struct kvm_mmio_range *vgic_find_range(const struct kvm_mmio_range *ranges, |
Marc Zyngier | 1a89dd9 | 2013-01-21 19:36:12 -0500 | [diff] [blame] | 1005 | struct kvm_exit_mmio *mmio, |
Christoffer Dall | 1006e8c | 2013-09-23 14:55:56 -0700 | [diff] [blame] | 1006 | phys_addr_t offset) |
Marc Zyngier | 1a89dd9 | 2013-01-21 19:36:12 -0500 | [diff] [blame] | 1007 | { |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 1008 | const struct kvm_mmio_range *r = ranges; |
Marc Zyngier | 1a89dd9 | 2013-01-21 19:36:12 -0500 | [diff] [blame] | 1009 | |
| 1010 | while (r->len) { |
Christoffer Dall | 1006e8c | 2013-09-23 14:55:56 -0700 | [diff] [blame] | 1011 | if (offset >= r->base && |
| 1012 | (offset + mmio->len) <= (r->base + r->len)) |
Marc Zyngier | 1a89dd9 | 2013-01-21 19:36:12 -0500 | [diff] [blame] | 1013 | return r; |
| 1014 | r++; |
| 1015 | } |
| 1016 | |
| 1017 | return NULL; |
| 1018 | } |
| 1019 | |
Marc Zyngier | c3c9183 | 2014-07-08 12:09:04 +0100 | [diff] [blame] | 1020 | static bool vgic_validate_access(const struct vgic_dist *dist, |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 1021 | const struct kvm_mmio_range *range, |
Marc Zyngier | c3c9183 | 2014-07-08 12:09:04 +0100 | [diff] [blame] | 1022 | unsigned long offset) |
| 1023 | { |
| 1024 | int irq; |
| 1025 | |
| 1026 | if (!range->bits_per_irq) |
| 1027 | return true; /* Not an irq-based access */ |
| 1028 | |
| 1029 | irq = offset * 8 / range->bits_per_irq; |
| 1030 | if (irq >= dist->nr_irqs) |
| 1031 | return false; |
| 1032 | |
| 1033 | return true; |
| 1034 | } |
| 1035 | |
Andre Przywara | 05bc8aa | 2014-06-05 16:07:50 +0200 | [diff] [blame] | 1036 | /* |
| 1037 | * Call the respective handler function for the given range. |
| 1038 | * We split up any 64 bit accesses into two consecutive 32 bit |
| 1039 | * handler calls and merge the result afterwards. |
| 1040 | * We do this in a little endian fashion regardless of the host's |
| 1041 | * or guest's endianness, because the GIC is always LE and the rest of |
| 1042 | * the code (vgic_reg_access) also puts it in a LE fashion already. |
| 1043 | * At this point we have already identified the handle function, so |
| 1044 | * range points to that one entry and offset is relative to this. |
| 1045 | */ |
| 1046 | static bool call_range_handler(struct kvm_vcpu *vcpu, |
| 1047 | struct kvm_exit_mmio *mmio, |
| 1048 | unsigned long offset, |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 1049 | const struct kvm_mmio_range *range) |
Andre Przywara | 05bc8aa | 2014-06-05 16:07:50 +0200 | [diff] [blame] | 1050 | { |
| 1051 | u32 *data32 = (void *)mmio->data; |
| 1052 | struct kvm_exit_mmio mmio32; |
| 1053 | bool ret; |
| 1054 | |
| 1055 | if (likely(mmio->len <= 4)) |
| 1056 | return range->handle_mmio(vcpu, mmio, offset); |
| 1057 | |
| 1058 | /* |
| 1059 | * Any access bigger than 4 bytes (that we currently handle in KVM) |
| 1060 | * is actually 8 bytes long, caused by a 64-bit access |
| 1061 | */ |
| 1062 | |
| 1063 | mmio32.len = 4; |
| 1064 | mmio32.is_write = mmio->is_write; |
| 1065 | |
| 1066 | mmio32.phys_addr = mmio->phys_addr + 4; |
| 1067 | if (mmio->is_write) |
| 1068 | *(u32 *)mmio32.data = data32[1]; |
| 1069 | ret = range->handle_mmio(vcpu, &mmio32, offset + 4); |
| 1070 | if (!mmio->is_write) |
| 1071 | data32[1] = *(u32 *)mmio32.data; |
| 1072 | |
| 1073 | mmio32.phys_addr = mmio->phys_addr; |
| 1074 | if (mmio->is_write) |
| 1075 | *(u32 *)mmio32.data = data32[0]; |
| 1076 | ret |= range->handle_mmio(vcpu, &mmio32, offset); |
| 1077 | if (!mmio->is_write) |
| 1078 | data32[0] = *(u32 *)mmio32.data; |
| 1079 | |
| 1080 | return ret; |
| 1081 | } |
| 1082 | |
Marc Zyngier | 1a89dd9 | 2013-01-21 19:36:12 -0500 | [diff] [blame] | 1083 | /** |
Andre Przywara | 9641525 | 2014-06-02 22:44:37 +0200 | [diff] [blame] | 1084 | * vgic_handle_mmio_range - handle an in-kernel MMIO access |
Marc Zyngier | 1a89dd9 | 2013-01-21 19:36:12 -0500 | [diff] [blame] | 1085 | * @vcpu: pointer to the vcpu performing the access |
| 1086 | * @run: pointer to the kvm_run structure |
| 1087 | * @mmio: pointer to the data describing the access |
Andre Przywara | 9641525 | 2014-06-02 22:44:37 +0200 | [diff] [blame] | 1088 | * @ranges: array of MMIO ranges in a given region |
| 1089 | * @mmio_base: base address of that region |
Marc Zyngier | 1a89dd9 | 2013-01-21 19:36:12 -0500 | [diff] [blame] | 1090 | * |
Andre Przywara | 9641525 | 2014-06-02 22:44:37 +0200 | [diff] [blame] | 1091 | * returns true if the MMIO access could be performed |
Marc Zyngier | 1a89dd9 | 2013-01-21 19:36:12 -0500 | [diff] [blame] | 1092 | */ |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 1093 | bool vgic_handle_mmio_range(struct kvm_vcpu *vcpu, struct kvm_run *run, |
Andre Przywara | 9641525 | 2014-06-02 22:44:37 +0200 | [diff] [blame] | 1094 | struct kvm_exit_mmio *mmio, |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 1095 | const struct kvm_mmio_range *ranges, |
Andre Przywara | 9641525 | 2014-06-02 22:44:37 +0200 | [diff] [blame] | 1096 | unsigned long mmio_base) |
Marc Zyngier | 1a89dd9 | 2013-01-21 19:36:12 -0500 | [diff] [blame] | 1097 | { |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 1098 | const struct kvm_mmio_range *range; |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1099 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1100 | bool updated_state; |
| 1101 | unsigned long offset; |
| 1102 | |
Andre Przywara | 9641525 | 2014-06-02 22:44:37 +0200 | [diff] [blame] | 1103 | offset = mmio->phys_addr - mmio_base; |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 1104 | range = vgic_find_range(ranges, mmio, offset); |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1105 | if (unlikely(!range || !range->handle_mmio)) { |
| 1106 | pr_warn("Unhandled access %d %08llx %d\n", |
| 1107 | mmio->is_write, mmio->phys_addr, mmio->len); |
| 1108 | return false; |
| 1109 | } |
| 1110 | |
| 1111 | spin_lock(&vcpu->kvm->arch.vgic.lock); |
Andre Przywara | 9641525 | 2014-06-02 22:44:37 +0200 | [diff] [blame] | 1112 | offset -= range->base; |
Marc Zyngier | c3c9183 | 2014-07-08 12:09:04 +0100 | [diff] [blame] | 1113 | if (vgic_validate_access(dist, range, offset)) { |
Andre Przywara | 05bc8aa | 2014-06-05 16:07:50 +0200 | [diff] [blame] | 1114 | updated_state = call_range_handler(vcpu, mmio, offset, range); |
Marc Zyngier | c3c9183 | 2014-07-08 12:09:04 +0100 | [diff] [blame] | 1115 | } else { |
Andre Przywara | 05bc8aa | 2014-06-05 16:07:50 +0200 | [diff] [blame] | 1116 | if (!mmio->is_write) |
| 1117 | memset(mmio->data, 0, mmio->len); |
Marc Zyngier | c3c9183 | 2014-07-08 12:09:04 +0100 | [diff] [blame] | 1118 | updated_state = false; |
| 1119 | } |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1120 | spin_unlock(&vcpu->kvm->arch.vgic.lock); |
| 1121 | kvm_prepare_mmio(run, mmio); |
| 1122 | kvm_handle_mmio_return(vcpu, run); |
| 1123 | |
Marc Zyngier | 5863c2c | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1124 | if (updated_state) |
| 1125 | vgic_kick_vcpus(vcpu->kvm); |
| 1126 | |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1127 | return true; |
| 1128 | } |
| 1129 | |
Andre Przywara | 9641525 | 2014-06-02 22:44:37 +0200 | [diff] [blame] | 1130 | static bool vgic_v2_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run, |
| 1131 | struct kvm_exit_mmio *mmio) |
| 1132 | { |
| 1133 | unsigned long base = vcpu->kvm->arch.vgic.vgic_dist_base; |
| 1134 | |
| 1135 | if (!is_in_range(mmio->phys_addr, mmio->len, base, |
| 1136 | KVM_VGIC_V2_DIST_SIZE)) |
| 1137 | return false; |
| 1138 | |
| 1139 | /* GICv2 does not support accesses wider than 32 bits */ |
| 1140 | if (mmio->len > 4) { |
| 1141 | kvm_inject_dabt(vcpu, mmio->phys_addr); |
| 1142 | return true; |
| 1143 | } |
| 1144 | |
| 1145 | return vgic_handle_mmio_range(vcpu, run, mmio, vgic_dist_ranges, base); |
| 1146 | } |
| 1147 | |
| 1148 | /** |
| 1149 | * vgic_handle_mmio - handle an in-kernel MMIO access for the GIC emulation |
| 1150 | * @vcpu: pointer to the vcpu performing the access |
| 1151 | * @run: pointer to the kvm_run structure |
| 1152 | * @mmio: pointer to the data describing the access |
| 1153 | * |
| 1154 | * returns true if the MMIO access has been performed in kernel space, |
| 1155 | * and false if it needs to be emulated in user space. |
Andre Przywara | b26e5fd | 2014-06-02 16:19:12 +0200 | [diff] [blame] | 1156 | * Calls the actual handling routine for the selected VGIC model. |
Andre Przywara | 9641525 | 2014-06-02 22:44:37 +0200 | [diff] [blame] | 1157 | */ |
| 1158 | bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run, |
| 1159 | struct kvm_exit_mmio *mmio) |
| 1160 | { |
| 1161 | if (!irqchip_in_kernel(vcpu->kvm)) |
| 1162 | return false; |
| 1163 | |
Andre Przywara | b26e5fd | 2014-06-02 16:19:12 +0200 | [diff] [blame] | 1164 | /* |
| 1165 | * This will currently call either vgic_v2_handle_mmio() or |
| 1166 | * vgic_v3_handle_mmio(), which in turn will call |
| 1167 | * vgic_handle_mmio_range() defined above. |
| 1168 | */ |
| 1169 | return vcpu->kvm->arch.vgic.vm_ops.handle_mmio(vcpu, run, mmio); |
Andre Przywara | 9641525 | 2014-06-02 22:44:37 +0200 | [diff] [blame] | 1170 | } |
| 1171 | |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1172 | static u8 *vgic_get_sgi_sources(struct vgic_dist *dist, int vcpu_id, int sgi) |
| 1173 | { |
| 1174 | return dist->irq_sgi_sources + vcpu_id * VGIC_NR_SGIS + sgi; |
| 1175 | } |
| 1176 | |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1177 | static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg) |
| 1178 | { |
| 1179 | struct kvm *kvm = vcpu->kvm; |
| 1180 | struct vgic_dist *dist = &kvm->arch.vgic; |
| 1181 | int nrcpus = atomic_read(&kvm->online_vcpus); |
| 1182 | u8 target_cpus; |
| 1183 | int sgi, mode, c, vcpu_id; |
| 1184 | |
| 1185 | vcpu_id = vcpu->vcpu_id; |
| 1186 | |
| 1187 | sgi = reg & 0xf; |
| 1188 | target_cpus = (reg >> 16) & 0xff; |
| 1189 | mode = (reg >> 24) & 3; |
| 1190 | |
| 1191 | switch (mode) { |
| 1192 | case 0: |
| 1193 | if (!target_cpus) |
| 1194 | return; |
Haibin Wang | 91021a6 | 2014-04-10 13:14:32 +0100 | [diff] [blame] | 1195 | break; |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1196 | |
| 1197 | case 1: |
| 1198 | target_cpus = ((1 << nrcpus) - 1) & ~(1 << vcpu_id) & 0xff; |
| 1199 | break; |
| 1200 | |
| 1201 | case 2: |
| 1202 | target_cpus = 1 << vcpu_id; |
| 1203 | break; |
| 1204 | } |
| 1205 | |
| 1206 | kvm_for_each_vcpu(c, vcpu, kvm) { |
| 1207 | if (target_cpus & 1) { |
| 1208 | /* Flag the SGI as pending */ |
Christoffer Dall | 227844f | 2014-06-09 12:27:18 +0200 | [diff] [blame] | 1209 | vgic_dist_irq_set_pending(vcpu, sgi); |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1210 | *vgic_get_sgi_sources(dist, c, sgi) |= 1 << vcpu_id; |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1211 | kvm_debug("SGI%d from CPU%d to CPU%d\n", sgi, vcpu_id, c); |
| 1212 | } |
| 1213 | |
| 1214 | target_cpus >>= 1; |
| 1215 | } |
| 1216 | } |
| 1217 | |
Marc Zyngier | fb65ab6 | 2014-07-08 12:09:02 +0100 | [diff] [blame] | 1218 | static int vgic_nr_shared_irqs(struct vgic_dist *dist) |
| 1219 | { |
| 1220 | return dist->nr_irqs - VGIC_NR_PRIVATE_IRQS; |
| 1221 | } |
| 1222 | |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1223 | static int compute_pending_for_cpu(struct kvm_vcpu *vcpu) |
| 1224 | { |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1225 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 1226 | unsigned long *pending, *enabled, *pend_percpu, *pend_shared; |
| 1227 | unsigned long pending_private, pending_shared; |
Marc Zyngier | fb65ab6 | 2014-07-08 12:09:02 +0100 | [diff] [blame] | 1228 | int nr_shared = vgic_nr_shared_irqs(dist); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1229 | int vcpu_id; |
| 1230 | |
| 1231 | vcpu_id = vcpu->vcpu_id; |
| 1232 | pend_percpu = vcpu->arch.vgic_cpu.pending_percpu; |
| 1233 | pend_shared = vcpu->arch.vgic_cpu.pending_shared; |
| 1234 | |
Christoffer Dall | 227844f | 2014-06-09 12:27:18 +0200 | [diff] [blame] | 1235 | pending = vgic_bitmap_get_cpu_map(&dist->irq_pending, vcpu_id); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1236 | enabled = vgic_bitmap_get_cpu_map(&dist->irq_enabled, vcpu_id); |
| 1237 | bitmap_and(pend_percpu, pending, enabled, VGIC_NR_PRIVATE_IRQS); |
| 1238 | |
Christoffer Dall | 227844f | 2014-06-09 12:27:18 +0200 | [diff] [blame] | 1239 | pending = vgic_bitmap_get_shared_map(&dist->irq_pending); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1240 | enabled = vgic_bitmap_get_shared_map(&dist->irq_enabled); |
Marc Zyngier | fb65ab6 | 2014-07-08 12:09:02 +0100 | [diff] [blame] | 1241 | bitmap_and(pend_shared, pending, enabled, nr_shared); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1242 | bitmap_and(pend_shared, pend_shared, |
| 1243 | vgic_bitmap_get_shared_map(&dist->irq_spi_target[vcpu_id]), |
Marc Zyngier | fb65ab6 | 2014-07-08 12:09:02 +0100 | [diff] [blame] | 1244 | nr_shared); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1245 | |
| 1246 | pending_private = find_first_bit(pend_percpu, VGIC_NR_PRIVATE_IRQS); |
Marc Zyngier | fb65ab6 | 2014-07-08 12:09:02 +0100 | [diff] [blame] | 1247 | pending_shared = find_first_bit(pend_shared, nr_shared); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1248 | return (pending_private < VGIC_NR_PRIVATE_IRQS || |
Marc Zyngier | fb65ab6 | 2014-07-08 12:09:02 +0100 | [diff] [blame] | 1249 | pending_shared < vgic_nr_shared_irqs(dist)); |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1250 | } |
| 1251 | |
| 1252 | /* |
| 1253 | * Update the interrupt state and determine which CPUs have pending |
| 1254 | * interrupts. Must be called with distributor lock held. |
| 1255 | */ |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 1256 | void vgic_update_state(struct kvm *kvm) |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1257 | { |
| 1258 | struct vgic_dist *dist = &kvm->arch.vgic; |
| 1259 | struct kvm_vcpu *vcpu; |
| 1260 | int c; |
| 1261 | |
| 1262 | if (!dist->enabled) { |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1263 | set_bit(0, dist->irq_pending_on_cpu); |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1264 | return; |
| 1265 | } |
| 1266 | |
| 1267 | kvm_for_each_vcpu(c, vcpu, kvm) { |
| 1268 | if (compute_pending_for_cpu(vcpu)) { |
| 1269 | pr_debug("CPU%d has pending interrupts\n", c); |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1270 | set_bit(c, dist->irq_pending_on_cpu); |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1271 | } |
| 1272 | } |
Marc Zyngier | 1a89dd9 | 2013-01-21 19:36:12 -0500 | [diff] [blame] | 1273 | } |
Christoffer Dall | 330690c | 2013-01-21 19:36:13 -0500 | [diff] [blame] | 1274 | |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 1275 | static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr) |
| 1276 | { |
Marc Zyngier | 8f186d5 | 2014-02-04 18:13:03 +0000 | [diff] [blame] | 1277 | return vgic_ops->get_lr(vcpu, lr); |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 1278 | } |
| 1279 | |
| 1280 | static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr, |
| 1281 | struct vgic_lr vlr) |
| 1282 | { |
Marc Zyngier | 8f186d5 | 2014-02-04 18:13:03 +0000 | [diff] [blame] | 1283 | vgic_ops->set_lr(vcpu, lr, vlr); |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 1284 | } |
| 1285 | |
Marc Zyngier | 69bb2c9 | 2013-06-04 10:29:39 +0100 | [diff] [blame] | 1286 | static void vgic_sync_lr_elrsr(struct kvm_vcpu *vcpu, int lr, |
| 1287 | struct vgic_lr vlr) |
| 1288 | { |
Marc Zyngier | 8f186d5 | 2014-02-04 18:13:03 +0000 | [diff] [blame] | 1289 | vgic_ops->sync_lr_elrsr(vcpu, lr, vlr); |
Marc Zyngier | 69bb2c9 | 2013-06-04 10:29:39 +0100 | [diff] [blame] | 1290 | } |
| 1291 | |
| 1292 | static inline u64 vgic_get_elrsr(struct kvm_vcpu *vcpu) |
| 1293 | { |
Marc Zyngier | 8f186d5 | 2014-02-04 18:13:03 +0000 | [diff] [blame] | 1294 | return vgic_ops->get_elrsr(vcpu); |
Marc Zyngier | 69bb2c9 | 2013-06-04 10:29:39 +0100 | [diff] [blame] | 1295 | } |
| 1296 | |
Marc Zyngier | 8d6a031 | 2013-06-04 10:33:43 +0100 | [diff] [blame] | 1297 | static inline u64 vgic_get_eisr(struct kvm_vcpu *vcpu) |
| 1298 | { |
Marc Zyngier | 8f186d5 | 2014-02-04 18:13:03 +0000 | [diff] [blame] | 1299 | return vgic_ops->get_eisr(vcpu); |
Marc Zyngier | 8d6a031 | 2013-06-04 10:33:43 +0100 | [diff] [blame] | 1300 | } |
| 1301 | |
Marc Zyngier | 495dd85 | 2013-06-04 11:02:10 +0100 | [diff] [blame] | 1302 | static inline u32 vgic_get_interrupt_status(struct kvm_vcpu *vcpu) |
| 1303 | { |
Marc Zyngier | 8f186d5 | 2014-02-04 18:13:03 +0000 | [diff] [blame] | 1304 | return vgic_ops->get_interrupt_status(vcpu); |
Marc Zyngier | 495dd85 | 2013-06-04 11:02:10 +0100 | [diff] [blame] | 1305 | } |
| 1306 | |
Marc Zyngier | 909d9b5 | 2013-06-04 11:24:17 +0100 | [diff] [blame] | 1307 | static inline void vgic_enable_underflow(struct kvm_vcpu *vcpu) |
| 1308 | { |
Marc Zyngier | 8f186d5 | 2014-02-04 18:13:03 +0000 | [diff] [blame] | 1309 | vgic_ops->enable_underflow(vcpu); |
Marc Zyngier | 909d9b5 | 2013-06-04 11:24:17 +0100 | [diff] [blame] | 1310 | } |
| 1311 | |
| 1312 | static inline void vgic_disable_underflow(struct kvm_vcpu *vcpu) |
| 1313 | { |
Marc Zyngier | 8f186d5 | 2014-02-04 18:13:03 +0000 | [diff] [blame] | 1314 | vgic_ops->disable_underflow(vcpu); |
Marc Zyngier | 909d9b5 | 2013-06-04 11:24:17 +0100 | [diff] [blame] | 1315 | } |
| 1316 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 1317 | void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr) |
Marc Zyngier | beee38b | 2014-02-04 17:48:10 +0000 | [diff] [blame] | 1318 | { |
Marc Zyngier | 8f186d5 | 2014-02-04 18:13:03 +0000 | [diff] [blame] | 1319 | vgic_ops->get_vmcr(vcpu, vmcr); |
Marc Zyngier | beee38b | 2014-02-04 17:48:10 +0000 | [diff] [blame] | 1320 | } |
| 1321 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 1322 | void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr) |
Marc Zyngier | beee38b | 2014-02-04 17:48:10 +0000 | [diff] [blame] | 1323 | { |
Marc Zyngier | 8f186d5 | 2014-02-04 18:13:03 +0000 | [diff] [blame] | 1324 | vgic_ops->set_vmcr(vcpu, vmcr); |
Marc Zyngier | beee38b | 2014-02-04 17:48:10 +0000 | [diff] [blame] | 1325 | } |
| 1326 | |
Marc Zyngier | da8dafd1 | 2013-06-04 11:36:38 +0100 | [diff] [blame] | 1327 | static inline void vgic_enable(struct kvm_vcpu *vcpu) |
| 1328 | { |
Marc Zyngier | 8f186d5 | 2014-02-04 18:13:03 +0000 | [diff] [blame] | 1329 | vgic_ops->enable(vcpu); |
Marc Zyngier | da8dafd1 | 2013-06-04 11:36:38 +0100 | [diff] [blame] | 1330 | } |
| 1331 | |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 1332 | static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu) |
| 1333 | { |
| 1334 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; |
| 1335 | struct vgic_lr vlr = vgic_get_lr(vcpu, lr_nr); |
| 1336 | |
| 1337 | vlr.state = 0; |
| 1338 | vgic_set_lr(vcpu, lr_nr, vlr); |
| 1339 | clear_bit(lr_nr, vgic_cpu->lr_used); |
| 1340 | vgic_cpu->vgic_irq_lr_map[irq] = LR_EMPTY; |
| 1341 | } |
Marc Zyngier | a1fcb44 | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1342 | |
| 1343 | /* |
| 1344 | * An interrupt may have been disabled after being made pending on the |
| 1345 | * CPU interface (the classic case is a timer running while we're |
| 1346 | * rebooting the guest - the interrupt would kick as soon as the CPU |
| 1347 | * interface gets enabled, with deadly consequences). |
| 1348 | * |
| 1349 | * The solution is to examine already active LRs, and check the |
| 1350 | * interrupt is still enabled. If not, just retire it. |
| 1351 | */ |
| 1352 | static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu) |
| 1353 | { |
| 1354 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; |
| 1355 | int lr; |
| 1356 | |
Marc Zyngier | 8f186d5 | 2014-02-04 18:13:03 +0000 | [diff] [blame] | 1357 | for_each_set_bit(lr, vgic_cpu->lr_used, vgic->nr_lr) { |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 1358 | struct vgic_lr vlr = vgic_get_lr(vcpu, lr); |
Marc Zyngier | a1fcb44 | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1359 | |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 1360 | if (!vgic_irq_is_enabled(vcpu, vlr.irq)) { |
| 1361 | vgic_retire_lr(lr, vlr.irq, vcpu); |
Christoffer Dall | dbf20f9 | 2014-06-09 12:55:13 +0200 | [diff] [blame] | 1362 | if (vgic_irq_is_queued(vcpu, vlr.irq)) |
| 1363 | vgic_irq_clear_queued(vcpu, vlr.irq); |
Marc Zyngier | a1fcb44 | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1364 | } |
| 1365 | } |
| 1366 | } |
| 1367 | |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1368 | /* |
| 1369 | * Queue an interrupt to a CPU virtual interface. Return true on success, |
| 1370 | * or false if it wasn't possible to queue it. |
| 1371 | */ |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 1372 | bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq) |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1373 | { |
| 1374 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; |
Marc Zyngier | 5fb66da | 2014-07-08 12:09:05 +0100 | [diff] [blame] | 1375 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 1376 | struct vgic_lr vlr; |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1377 | int lr; |
| 1378 | |
| 1379 | /* Sanitize the input... */ |
| 1380 | BUG_ON(sgi_source_id & ~7); |
| 1381 | BUG_ON(sgi_source_id && irq >= VGIC_NR_SGIS); |
Marc Zyngier | 5fb66da | 2014-07-08 12:09:05 +0100 | [diff] [blame] | 1382 | BUG_ON(irq >= dist->nr_irqs); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1383 | |
| 1384 | kvm_debug("Queue IRQ%d\n", irq); |
| 1385 | |
| 1386 | lr = vgic_cpu->vgic_irq_lr_map[irq]; |
| 1387 | |
| 1388 | /* Do we have an active interrupt for the same CPUID? */ |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 1389 | if (lr != LR_EMPTY) { |
| 1390 | vlr = vgic_get_lr(vcpu, lr); |
| 1391 | if (vlr.source == sgi_source_id) { |
| 1392 | kvm_debug("LR%d piggyback for IRQ%d\n", lr, vlr.irq); |
| 1393 | BUG_ON(!test_bit(lr, vgic_cpu->lr_used)); |
| 1394 | vlr.state |= LR_STATE_PENDING; |
| 1395 | vgic_set_lr(vcpu, lr, vlr); |
| 1396 | return true; |
| 1397 | } |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1398 | } |
| 1399 | |
| 1400 | /* Try to use another LR for this interrupt */ |
| 1401 | lr = find_first_zero_bit((unsigned long *)vgic_cpu->lr_used, |
Marc Zyngier | 8f186d5 | 2014-02-04 18:13:03 +0000 | [diff] [blame] | 1402 | vgic->nr_lr); |
| 1403 | if (lr >= vgic->nr_lr) |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1404 | return false; |
| 1405 | |
| 1406 | kvm_debug("LR%d allocated for IRQ%d %x\n", lr, irq, sgi_source_id); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1407 | vgic_cpu->vgic_irq_lr_map[irq] = lr; |
| 1408 | set_bit(lr, vgic_cpu->lr_used); |
| 1409 | |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 1410 | vlr.irq = irq; |
| 1411 | vlr.source = sgi_source_id; |
| 1412 | vlr.state = LR_STATE_PENDING; |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1413 | if (!vgic_irq_is_edge(vcpu, irq)) |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 1414 | vlr.state |= LR_EOI_INT; |
| 1415 | |
| 1416 | vgic_set_lr(vcpu, lr, vlr); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1417 | |
| 1418 | return true; |
| 1419 | } |
| 1420 | |
Andre Przywara | b26e5fd | 2014-06-02 16:19:12 +0200 | [diff] [blame] | 1421 | static bool vgic_v2_queue_sgi(struct kvm_vcpu *vcpu, int irq) |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1422 | { |
| 1423 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 1424 | unsigned long sources; |
| 1425 | int vcpu_id = vcpu->vcpu_id; |
| 1426 | int c; |
| 1427 | |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1428 | sources = *vgic_get_sgi_sources(dist, vcpu_id, irq); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1429 | |
Marc Zyngier | fc675e3 | 2014-07-08 12:09:03 +0100 | [diff] [blame] | 1430 | for_each_set_bit(c, &sources, dist->nr_cpus) { |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1431 | if (vgic_queue_irq(vcpu, c, irq)) |
| 1432 | clear_bit(c, &sources); |
| 1433 | } |
| 1434 | |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1435 | *vgic_get_sgi_sources(dist, vcpu_id, irq) = sources; |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1436 | |
| 1437 | /* |
| 1438 | * If the sources bitmap has been cleared it means that we |
| 1439 | * could queue all the SGIs onto link registers (see the |
| 1440 | * clear_bit above), and therefore we are done with them in |
| 1441 | * our emulated gic and can get rid of them. |
| 1442 | */ |
| 1443 | if (!sources) { |
Christoffer Dall | 227844f | 2014-06-09 12:27:18 +0200 | [diff] [blame] | 1444 | vgic_dist_irq_clear_pending(vcpu, irq); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1445 | vgic_cpu_irq_clear(vcpu, irq); |
| 1446 | return true; |
| 1447 | } |
| 1448 | |
| 1449 | return false; |
| 1450 | } |
| 1451 | |
| 1452 | static bool vgic_queue_hwirq(struct kvm_vcpu *vcpu, int irq) |
| 1453 | { |
Christoffer Dall | dbf20f9 | 2014-06-09 12:55:13 +0200 | [diff] [blame] | 1454 | if (!vgic_can_sample_irq(vcpu, irq)) |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1455 | return true; /* level interrupt, already queued */ |
| 1456 | |
| 1457 | if (vgic_queue_irq(vcpu, 0, irq)) { |
| 1458 | if (vgic_irq_is_edge(vcpu, irq)) { |
Christoffer Dall | 227844f | 2014-06-09 12:27:18 +0200 | [diff] [blame] | 1459 | vgic_dist_irq_clear_pending(vcpu, irq); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1460 | vgic_cpu_irq_clear(vcpu, irq); |
| 1461 | } else { |
Christoffer Dall | dbf20f9 | 2014-06-09 12:55:13 +0200 | [diff] [blame] | 1462 | vgic_irq_set_queued(vcpu, irq); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1463 | } |
| 1464 | |
| 1465 | return true; |
| 1466 | } |
| 1467 | |
| 1468 | return false; |
| 1469 | } |
| 1470 | |
| 1471 | /* |
| 1472 | * Fill the list registers with pending interrupts before running the |
| 1473 | * guest. |
| 1474 | */ |
| 1475 | static void __kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) |
| 1476 | { |
| 1477 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; |
| 1478 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 1479 | int i, vcpu_id; |
| 1480 | int overflow = 0; |
| 1481 | |
| 1482 | vcpu_id = vcpu->vcpu_id; |
| 1483 | |
| 1484 | /* |
| 1485 | * We may not have any pending interrupt, or the interrupts |
| 1486 | * may have been serviced from another vcpu. In all cases, |
| 1487 | * move along. |
| 1488 | */ |
| 1489 | if (!kvm_vgic_vcpu_pending_irq(vcpu)) { |
| 1490 | pr_debug("CPU%d has no pending interrupt\n", vcpu_id); |
| 1491 | goto epilog; |
| 1492 | } |
| 1493 | |
| 1494 | /* SGIs */ |
| 1495 | for_each_set_bit(i, vgic_cpu->pending_percpu, VGIC_NR_SGIS) { |
Andre Przywara | b26e5fd | 2014-06-02 16:19:12 +0200 | [diff] [blame] | 1496 | if (!queue_sgi(vcpu, i)) |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1497 | overflow = 1; |
| 1498 | } |
| 1499 | |
| 1500 | /* PPIs */ |
| 1501 | for_each_set_bit_from(i, vgic_cpu->pending_percpu, VGIC_NR_PRIVATE_IRQS) { |
| 1502 | if (!vgic_queue_hwirq(vcpu, i)) |
| 1503 | overflow = 1; |
| 1504 | } |
| 1505 | |
| 1506 | /* SPIs */ |
Marc Zyngier | fb65ab6 | 2014-07-08 12:09:02 +0100 | [diff] [blame] | 1507 | for_each_set_bit(i, vgic_cpu->pending_shared, vgic_nr_shared_irqs(dist)) { |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1508 | if (!vgic_queue_hwirq(vcpu, i + VGIC_NR_PRIVATE_IRQS)) |
| 1509 | overflow = 1; |
| 1510 | } |
| 1511 | |
| 1512 | epilog: |
| 1513 | if (overflow) { |
Marc Zyngier | 909d9b5 | 2013-06-04 11:24:17 +0100 | [diff] [blame] | 1514 | vgic_enable_underflow(vcpu); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1515 | } else { |
Marc Zyngier | 909d9b5 | 2013-06-04 11:24:17 +0100 | [diff] [blame] | 1516 | vgic_disable_underflow(vcpu); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1517 | /* |
| 1518 | * We're about to run this VCPU, and we've consumed |
| 1519 | * everything the distributor had in store for |
| 1520 | * us. Claim we don't have anything pending. We'll |
| 1521 | * adjust that if needed while exiting. |
| 1522 | */ |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1523 | clear_bit(vcpu_id, dist->irq_pending_on_cpu); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1524 | } |
| 1525 | } |
| 1526 | |
| 1527 | static bool vgic_process_maintenance(struct kvm_vcpu *vcpu) |
| 1528 | { |
Marc Zyngier | 495dd85 | 2013-06-04 11:02:10 +0100 | [diff] [blame] | 1529 | u32 status = vgic_get_interrupt_status(vcpu); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1530 | bool level_pending = false; |
| 1531 | |
Marc Zyngier | 495dd85 | 2013-06-04 11:02:10 +0100 | [diff] [blame] | 1532 | kvm_debug("STATUS = %08x\n", status); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1533 | |
Marc Zyngier | 495dd85 | 2013-06-04 11:02:10 +0100 | [diff] [blame] | 1534 | if (status & INT_STATUS_EOI) { |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1535 | /* |
| 1536 | * Some level interrupts have been EOIed. Clear their |
| 1537 | * active bit. |
| 1538 | */ |
Marc Zyngier | 8d6a031 | 2013-06-04 10:33:43 +0100 | [diff] [blame] | 1539 | u64 eisr = vgic_get_eisr(vcpu); |
Christoffer Dall | 2df36a5 | 2014-09-28 16:04:26 +0200 | [diff] [blame] | 1540 | unsigned long *eisr_ptr = u64_to_bitmask(&eisr); |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 1541 | int lr; |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1542 | |
Marc Zyngier | 8f186d5 | 2014-02-04 18:13:03 +0000 | [diff] [blame] | 1543 | for_each_set_bit(lr, eisr_ptr, vgic->nr_lr) { |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 1544 | struct vgic_lr vlr = vgic_get_lr(vcpu, lr); |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 1545 | WARN_ON(vgic_irq_is_edge(vcpu, vlr.irq)); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1546 | |
Christoffer Dall | dbf20f9 | 2014-06-09 12:55:13 +0200 | [diff] [blame] | 1547 | vgic_irq_clear_queued(vcpu, vlr.irq); |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 1548 | WARN_ON(vlr.state & LR_STATE_MASK); |
| 1549 | vlr.state = 0; |
| 1550 | vgic_set_lr(vcpu, lr, vlr); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1551 | |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 1552 | /* |
| 1553 | * If the IRQ was EOIed it was also ACKed and we we |
| 1554 | * therefore assume we can clear the soft pending |
| 1555 | * state (should it had been set) for this interrupt. |
| 1556 | * |
| 1557 | * Note: if the IRQ soft pending state was set after |
| 1558 | * the IRQ was acked, it actually shouldn't be |
| 1559 | * cleared, but we have no way of knowing that unless |
| 1560 | * we start trapping ACKs when the soft-pending state |
| 1561 | * is set. |
| 1562 | */ |
| 1563 | vgic_dist_irq_clear_soft_pend(vcpu, vlr.irq); |
| 1564 | |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1565 | /* Any additional pending interrupt? */ |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 1566 | if (vgic_dist_irq_get_level(vcpu, vlr.irq)) { |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 1567 | vgic_cpu_irq_set(vcpu, vlr.irq); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1568 | level_pending = true; |
| 1569 | } else { |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 1570 | vgic_dist_irq_clear_pending(vcpu, vlr.irq); |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 1571 | vgic_cpu_irq_clear(vcpu, vlr.irq); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1572 | } |
Marc Zyngier | 75da01e | 2013-01-31 11:25:52 +0000 | [diff] [blame] | 1573 | |
| 1574 | /* |
| 1575 | * Despite being EOIed, the LR may not have |
| 1576 | * been marked as empty. |
| 1577 | */ |
Marc Zyngier | 69bb2c9 | 2013-06-04 10:29:39 +0100 | [diff] [blame] | 1578 | vgic_sync_lr_elrsr(vcpu, lr, vlr); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1579 | } |
| 1580 | } |
| 1581 | |
Marc Zyngier | 495dd85 | 2013-06-04 11:02:10 +0100 | [diff] [blame] | 1582 | if (status & INT_STATUS_UNDERFLOW) |
Marc Zyngier | 909d9b5 | 2013-06-04 11:24:17 +0100 | [diff] [blame] | 1583 | vgic_disable_underflow(vcpu); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1584 | |
| 1585 | return level_pending; |
| 1586 | } |
| 1587 | |
| 1588 | /* |
Marc Zyngier | 33c83cb | 2013-02-01 18:28:30 +0000 | [diff] [blame] | 1589 | * Sync back the VGIC state after a guest run. The distributor lock is |
| 1590 | * needed so we don't get preempted in the middle of the state processing. |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1591 | */ |
| 1592 | static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) |
| 1593 | { |
| 1594 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; |
| 1595 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
Marc Zyngier | 69bb2c9 | 2013-06-04 10:29:39 +0100 | [diff] [blame] | 1596 | u64 elrsr; |
| 1597 | unsigned long *elrsr_ptr; |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1598 | int lr, pending; |
| 1599 | bool level_pending; |
| 1600 | |
| 1601 | level_pending = vgic_process_maintenance(vcpu); |
Marc Zyngier | 69bb2c9 | 2013-06-04 10:29:39 +0100 | [diff] [blame] | 1602 | elrsr = vgic_get_elrsr(vcpu); |
Christoffer Dall | 2df36a5 | 2014-09-28 16:04:26 +0200 | [diff] [blame] | 1603 | elrsr_ptr = u64_to_bitmask(&elrsr); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1604 | |
| 1605 | /* Clear mappings for empty LRs */ |
Marc Zyngier | 8f186d5 | 2014-02-04 18:13:03 +0000 | [diff] [blame] | 1606 | for_each_set_bit(lr, elrsr_ptr, vgic->nr_lr) { |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 1607 | struct vgic_lr vlr; |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1608 | |
| 1609 | if (!test_and_clear_bit(lr, vgic_cpu->lr_used)) |
| 1610 | continue; |
| 1611 | |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 1612 | vlr = vgic_get_lr(vcpu, lr); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1613 | |
Marc Zyngier | 5fb66da | 2014-07-08 12:09:05 +0100 | [diff] [blame] | 1614 | BUG_ON(vlr.irq >= dist->nr_irqs); |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 1615 | vgic_cpu->vgic_irq_lr_map[vlr.irq] = LR_EMPTY; |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1616 | } |
| 1617 | |
| 1618 | /* Check if we still have something up our sleeve... */ |
Marc Zyngier | 8f186d5 | 2014-02-04 18:13:03 +0000 | [diff] [blame] | 1619 | pending = find_first_zero_bit(elrsr_ptr, vgic->nr_lr); |
| 1620 | if (level_pending || pending < vgic->nr_lr) |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1621 | set_bit(vcpu->vcpu_id, dist->irq_pending_on_cpu); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1622 | } |
| 1623 | |
| 1624 | void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) |
| 1625 | { |
| 1626 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 1627 | |
| 1628 | if (!irqchip_in_kernel(vcpu->kvm)) |
| 1629 | return; |
| 1630 | |
| 1631 | spin_lock(&dist->lock); |
| 1632 | __kvm_vgic_flush_hwstate(vcpu); |
| 1633 | spin_unlock(&dist->lock); |
| 1634 | } |
| 1635 | |
| 1636 | void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) |
| 1637 | { |
Marc Zyngier | 33c83cb | 2013-02-01 18:28:30 +0000 | [diff] [blame] | 1638 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 1639 | |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1640 | if (!irqchip_in_kernel(vcpu->kvm)) |
| 1641 | return; |
| 1642 | |
Marc Zyngier | 33c83cb | 2013-02-01 18:28:30 +0000 | [diff] [blame] | 1643 | spin_lock(&dist->lock); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1644 | __kvm_vgic_sync_hwstate(vcpu); |
Marc Zyngier | 33c83cb | 2013-02-01 18:28:30 +0000 | [diff] [blame] | 1645 | spin_unlock(&dist->lock); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1646 | } |
| 1647 | |
| 1648 | int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu) |
| 1649 | { |
| 1650 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 1651 | |
| 1652 | if (!irqchip_in_kernel(vcpu->kvm)) |
| 1653 | return 0; |
| 1654 | |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1655 | return test_bit(vcpu->vcpu_id, dist->irq_pending_on_cpu); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1656 | } |
| 1657 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 1658 | void vgic_kick_vcpus(struct kvm *kvm) |
Marc Zyngier | 5863c2c | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1659 | { |
| 1660 | struct kvm_vcpu *vcpu; |
| 1661 | int c; |
| 1662 | |
| 1663 | /* |
| 1664 | * We've injected an interrupt, time to find out who deserves |
| 1665 | * a good kick... |
| 1666 | */ |
| 1667 | kvm_for_each_vcpu(c, vcpu, kvm) { |
| 1668 | if (kvm_vgic_vcpu_pending_irq(vcpu)) |
| 1669 | kvm_vcpu_kick(vcpu); |
| 1670 | } |
| 1671 | } |
| 1672 | |
| 1673 | static int vgic_validate_injection(struct kvm_vcpu *vcpu, int irq, int level) |
| 1674 | { |
Christoffer Dall | 227844f | 2014-06-09 12:27:18 +0200 | [diff] [blame] | 1675 | int edge_triggered = vgic_irq_is_edge(vcpu, irq); |
Marc Zyngier | 5863c2c | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1676 | |
| 1677 | /* |
| 1678 | * Only inject an interrupt if: |
| 1679 | * - edge triggered and we have a rising edge |
| 1680 | * - level triggered and we change level |
| 1681 | */ |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 1682 | if (edge_triggered) { |
| 1683 | int state = vgic_dist_irq_is_pending(vcpu, irq); |
Marc Zyngier | 5863c2c | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1684 | return level > state; |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 1685 | } else { |
| 1686 | int state = vgic_dist_irq_get_level(vcpu, irq); |
Marc Zyngier | 5863c2c | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1687 | return level != state; |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 1688 | } |
Marc Zyngier | 5863c2c | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1689 | } |
| 1690 | |
Shannon Zhao | 016ed39 | 2014-11-19 10:11:25 +0000 | [diff] [blame] | 1691 | static int vgic_update_irq_pending(struct kvm *kvm, int cpuid, |
Marc Zyngier | 5863c2c | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1692 | unsigned int irq_num, bool level) |
| 1693 | { |
| 1694 | struct vgic_dist *dist = &kvm->arch.vgic; |
| 1695 | struct kvm_vcpu *vcpu; |
Christoffer Dall | 227844f | 2014-06-09 12:27:18 +0200 | [diff] [blame] | 1696 | int edge_triggered, level_triggered; |
Marc Zyngier | 5863c2c | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1697 | int enabled; |
| 1698 | bool ret = true; |
| 1699 | |
| 1700 | spin_lock(&dist->lock); |
| 1701 | |
| 1702 | vcpu = kvm_get_vcpu(kvm, cpuid); |
Christoffer Dall | 227844f | 2014-06-09 12:27:18 +0200 | [diff] [blame] | 1703 | edge_triggered = vgic_irq_is_edge(vcpu, irq_num); |
| 1704 | level_triggered = !edge_triggered; |
Marc Zyngier | 5863c2c | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1705 | |
| 1706 | if (!vgic_validate_injection(vcpu, irq_num, level)) { |
| 1707 | ret = false; |
| 1708 | goto out; |
| 1709 | } |
| 1710 | |
| 1711 | if (irq_num >= VGIC_NR_PRIVATE_IRQS) { |
| 1712 | cpuid = dist->irq_spi_cpu[irq_num - VGIC_NR_PRIVATE_IRQS]; |
| 1713 | vcpu = kvm_get_vcpu(kvm, cpuid); |
| 1714 | } |
| 1715 | |
| 1716 | kvm_debug("Inject IRQ%d level %d CPU%d\n", irq_num, level, cpuid); |
| 1717 | |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 1718 | if (level) { |
| 1719 | if (level_triggered) |
| 1720 | vgic_dist_irq_set_level(vcpu, irq_num); |
Christoffer Dall | 227844f | 2014-06-09 12:27:18 +0200 | [diff] [blame] | 1721 | vgic_dist_irq_set_pending(vcpu, irq_num); |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 1722 | } else { |
| 1723 | if (level_triggered) { |
| 1724 | vgic_dist_irq_clear_level(vcpu, irq_num); |
| 1725 | if (!vgic_dist_irq_soft_pend(vcpu, irq_num)) |
| 1726 | vgic_dist_irq_clear_pending(vcpu, irq_num); |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 1727 | } |
wanghaibin | 7d39f9e3 | 2014-11-17 09:27:37 +0000 | [diff] [blame] | 1728 | |
| 1729 | ret = false; |
| 1730 | goto out; |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 1731 | } |
Marc Zyngier | 5863c2c | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1732 | |
| 1733 | enabled = vgic_irq_is_enabled(vcpu, irq_num); |
| 1734 | |
| 1735 | if (!enabled) { |
| 1736 | ret = false; |
| 1737 | goto out; |
| 1738 | } |
| 1739 | |
Christoffer Dall | dbf20f9 | 2014-06-09 12:55:13 +0200 | [diff] [blame] | 1740 | if (!vgic_can_sample_irq(vcpu, irq_num)) { |
Marc Zyngier | 5863c2c | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1741 | /* |
| 1742 | * Level interrupt in progress, will be picked up |
| 1743 | * when EOId. |
| 1744 | */ |
| 1745 | ret = false; |
| 1746 | goto out; |
| 1747 | } |
| 1748 | |
| 1749 | if (level) { |
| 1750 | vgic_cpu_irq_set(vcpu, irq_num); |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1751 | set_bit(cpuid, dist->irq_pending_on_cpu); |
Marc Zyngier | 5863c2c | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1752 | } |
| 1753 | |
| 1754 | out: |
| 1755 | spin_unlock(&dist->lock); |
| 1756 | |
Shannon Zhao | 016ed39 | 2014-11-19 10:11:25 +0000 | [diff] [blame] | 1757 | return ret ? cpuid : -EINVAL; |
Marc Zyngier | 5863c2c | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1758 | } |
| 1759 | |
| 1760 | /** |
| 1761 | * kvm_vgic_inject_irq - Inject an IRQ from a device to the vgic |
| 1762 | * @kvm: The VM structure pointer |
| 1763 | * @cpuid: The CPU for PPIs |
| 1764 | * @irq_num: The IRQ number that is assigned to the device |
| 1765 | * @level: Edge-triggered: true: to trigger the interrupt |
| 1766 | * false: to ignore the call |
| 1767 | * Level-sensitive true: activates an interrupt |
| 1768 | * false: deactivates an interrupt |
| 1769 | * |
| 1770 | * The GIC is not concerned with devices being active-LOW or active-HIGH for |
| 1771 | * level-sensitive interrupts. You can think of the level parameter as 1 |
| 1772 | * being HIGH and 0 being LOW and all devices being active-HIGH. |
| 1773 | */ |
| 1774 | int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num, |
| 1775 | bool level) |
| 1776 | { |
Christoffer Dall | ca7d9c8 | 2014-12-09 14:35:33 +0100 | [diff] [blame] | 1777 | int ret = 0; |
Shannon Zhao | 016ed39 | 2014-11-19 10:11:25 +0000 | [diff] [blame] | 1778 | int vcpu_id; |
Marc Zyngier | 5863c2c | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1779 | |
Christoffer Dall | ca7d9c8 | 2014-12-09 14:35:33 +0100 | [diff] [blame] | 1780 | if (unlikely(!vgic_initialized(kvm))) { |
Andre Przywara | 59892136 | 2014-06-03 09:33:10 +0200 | [diff] [blame] | 1781 | /* |
| 1782 | * We only provide the automatic initialization of the VGIC |
| 1783 | * for the legacy case of a GICv2. Any other type must |
| 1784 | * be explicitly initialized once setup with the respective |
| 1785 | * KVM device call. |
| 1786 | */ |
| 1787 | if (kvm->arch.vgic.vgic_model != KVM_DEV_TYPE_ARM_VGIC_V2) { |
| 1788 | ret = -EBUSY; |
| 1789 | goto out; |
| 1790 | } |
Christoffer Dall | ca7d9c8 | 2014-12-09 14:35:33 +0100 | [diff] [blame] | 1791 | mutex_lock(&kvm->lock); |
| 1792 | ret = vgic_init(kvm); |
| 1793 | mutex_unlock(&kvm->lock); |
| 1794 | |
| 1795 | if (ret) |
| 1796 | goto out; |
Shannon Zhao | 016ed39 | 2014-11-19 10:11:25 +0000 | [diff] [blame] | 1797 | } |
Marc Zyngier | 5863c2c | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1798 | |
Christoffer Dall | ca7d9c8 | 2014-12-09 14:35:33 +0100 | [diff] [blame] | 1799 | vcpu_id = vgic_update_irq_pending(kvm, cpuid, irq_num, level); |
| 1800 | if (vcpu_id >= 0) { |
| 1801 | /* kick the specified vcpu */ |
| 1802 | kvm_vcpu_kick(kvm_get_vcpu(kvm, vcpu_id)); |
| 1803 | } |
| 1804 | |
| 1805 | out: |
| 1806 | return ret; |
Marc Zyngier | 5863c2c | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1807 | } |
| 1808 | |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 1809 | static irqreturn_t vgic_maintenance_handler(int irq, void *data) |
| 1810 | { |
| 1811 | /* |
| 1812 | * We cannot rely on the vgic maintenance interrupt to be |
| 1813 | * delivered synchronously. This means we can only use it to |
| 1814 | * exit the VM, and we perform the handling of EOIed |
| 1815 | * interrupts on the exit path (see vgic_process_maintenance). |
| 1816 | */ |
| 1817 | return IRQ_HANDLED; |
| 1818 | } |
| 1819 | |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1820 | void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu) |
| 1821 | { |
| 1822 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; |
| 1823 | |
| 1824 | kfree(vgic_cpu->pending_shared); |
| 1825 | kfree(vgic_cpu->vgic_irq_lr_map); |
| 1826 | vgic_cpu->pending_shared = NULL; |
| 1827 | vgic_cpu->vgic_irq_lr_map = NULL; |
| 1828 | } |
| 1829 | |
| 1830 | static int vgic_vcpu_init_maps(struct kvm_vcpu *vcpu, int nr_irqs) |
| 1831 | { |
| 1832 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; |
| 1833 | |
| 1834 | int sz = (nr_irqs - VGIC_NR_PRIVATE_IRQS) / 8; |
| 1835 | vgic_cpu->pending_shared = kzalloc(sz, GFP_KERNEL); |
Peter Maydell | 6d3cfbe | 2014-12-04 15:02:24 +0000 | [diff] [blame] | 1836 | vgic_cpu->vgic_irq_lr_map = kmalloc(nr_irqs, GFP_KERNEL); |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1837 | |
| 1838 | if (!vgic_cpu->pending_shared || !vgic_cpu->vgic_irq_lr_map) { |
| 1839 | kvm_vgic_vcpu_destroy(vcpu); |
| 1840 | return -ENOMEM; |
| 1841 | } |
| 1842 | |
Peter Maydell | 6d3cfbe | 2014-12-04 15:02:24 +0000 | [diff] [blame] | 1843 | memset(vgic_cpu->vgic_irq_lr_map, LR_EMPTY, nr_irqs); |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 1844 | |
| 1845 | /* |
Marc Zyngier | ca85f62 | 2013-06-18 19:17:28 +0100 | [diff] [blame] | 1846 | * Store the number of LRs per vcpu, so we don't have to go |
| 1847 | * all the way to the distributor structure to find out. Only |
| 1848 | * assembly code should use this one. |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 1849 | */ |
Marc Zyngier | 8f186d5 | 2014-02-04 18:13:03 +0000 | [diff] [blame] | 1850 | vgic_cpu->nr_lr = vgic->nr_lr; |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 1851 | |
Peter Maydell | 6d3cfbe | 2014-12-04 15:02:24 +0000 | [diff] [blame] | 1852 | return 0; |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 1853 | } |
| 1854 | |
Andre Przywara | 3caa2d8 | 2014-06-02 16:26:01 +0200 | [diff] [blame] | 1855 | /** |
| 1856 | * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW |
| 1857 | * |
| 1858 | * The host's GIC naturally limits the maximum amount of VCPUs a guest |
| 1859 | * can use. |
| 1860 | */ |
| 1861 | int kvm_vgic_get_max_vcpus(void) |
| 1862 | { |
| 1863 | return vgic->max_gic_vcpus; |
| 1864 | } |
| 1865 | |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1866 | void kvm_vgic_destroy(struct kvm *kvm) |
| 1867 | { |
| 1868 | struct vgic_dist *dist = &kvm->arch.vgic; |
| 1869 | struct kvm_vcpu *vcpu; |
| 1870 | int i; |
| 1871 | |
| 1872 | kvm_for_each_vcpu(i, vcpu, kvm) |
| 1873 | kvm_vgic_vcpu_destroy(vcpu); |
| 1874 | |
| 1875 | vgic_free_bitmap(&dist->irq_enabled); |
| 1876 | vgic_free_bitmap(&dist->irq_level); |
| 1877 | vgic_free_bitmap(&dist->irq_pending); |
| 1878 | vgic_free_bitmap(&dist->irq_soft_pend); |
| 1879 | vgic_free_bitmap(&dist->irq_queued); |
| 1880 | vgic_free_bitmap(&dist->irq_cfg); |
| 1881 | vgic_free_bytemap(&dist->irq_priority); |
| 1882 | if (dist->irq_spi_target) { |
| 1883 | for (i = 0; i < dist->nr_cpus; i++) |
| 1884 | vgic_free_bitmap(&dist->irq_spi_target[i]); |
| 1885 | } |
| 1886 | kfree(dist->irq_sgi_sources); |
| 1887 | kfree(dist->irq_spi_cpu); |
| 1888 | kfree(dist->irq_spi_target); |
| 1889 | kfree(dist->irq_pending_on_cpu); |
| 1890 | dist->irq_sgi_sources = NULL; |
| 1891 | dist->irq_spi_cpu = NULL; |
| 1892 | dist->irq_spi_target = NULL; |
| 1893 | dist->irq_pending_on_cpu = NULL; |
Christoffer Dall | 1f57be2 | 2014-12-09 14:30:36 +0100 | [diff] [blame] | 1894 | dist->nr_cpus = 0; |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1895 | } |
| 1896 | |
Andre Przywara | b26e5fd | 2014-06-02 16:19:12 +0200 | [diff] [blame] | 1897 | static int vgic_v2_init_model(struct kvm *kvm) |
| 1898 | { |
| 1899 | int i; |
| 1900 | |
| 1901 | for (i = VGIC_NR_PRIVATE_IRQS; i < kvm->arch.vgic.nr_irqs; i += 4) |
| 1902 | vgic_set_target_reg(kvm, 0, i); |
| 1903 | |
| 1904 | return 0; |
| 1905 | } |
| 1906 | |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1907 | /* |
| 1908 | * Allocate and initialize the various data structures. Must be called |
| 1909 | * with kvm->lock held! |
| 1910 | */ |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 1911 | int vgic_init(struct kvm *kvm) |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1912 | { |
| 1913 | struct vgic_dist *dist = &kvm->arch.vgic; |
| 1914 | struct kvm_vcpu *vcpu; |
| 1915 | int nr_cpus, nr_irqs; |
Peter Maydell | 6d3cfbe | 2014-12-04 15:02:24 +0000 | [diff] [blame] | 1916 | int ret, i, vcpu_id; |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1917 | |
Christoffer Dall | 1f57be2 | 2014-12-09 14:30:36 +0100 | [diff] [blame] | 1918 | if (vgic_initialized(kvm)) |
Marc Zyngier | 4956f2b | 2014-07-08 12:09:06 +0100 | [diff] [blame] | 1919 | return 0; |
Marc Zyngier | 5fb66da | 2014-07-08 12:09:05 +0100 | [diff] [blame] | 1920 | |
Marc Zyngier | 4956f2b | 2014-07-08 12:09:06 +0100 | [diff] [blame] | 1921 | nr_cpus = dist->nr_cpus = atomic_read(&kvm->online_vcpus); |
| 1922 | if (!nr_cpus) /* No vcpus? Can't be good... */ |
Eric Auger | 66b030e | 2014-12-15 18:43:32 +0100 | [diff] [blame] | 1923 | return -ENODEV; |
Marc Zyngier | 4956f2b | 2014-07-08 12:09:06 +0100 | [diff] [blame] | 1924 | |
| 1925 | /* |
| 1926 | * If nobody configured the number of interrupts, use the |
| 1927 | * legacy one. |
| 1928 | */ |
Marc Zyngier | 5fb66da | 2014-07-08 12:09:05 +0100 | [diff] [blame] | 1929 | if (!dist->nr_irqs) |
| 1930 | dist->nr_irqs = VGIC_NR_IRQS_LEGACY; |
| 1931 | |
| 1932 | nr_irqs = dist->nr_irqs; |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1933 | |
| 1934 | ret = vgic_init_bitmap(&dist->irq_enabled, nr_cpus, nr_irqs); |
| 1935 | ret |= vgic_init_bitmap(&dist->irq_level, nr_cpus, nr_irqs); |
| 1936 | ret |= vgic_init_bitmap(&dist->irq_pending, nr_cpus, nr_irqs); |
| 1937 | ret |= vgic_init_bitmap(&dist->irq_soft_pend, nr_cpus, nr_irqs); |
| 1938 | ret |= vgic_init_bitmap(&dist->irq_queued, nr_cpus, nr_irqs); |
| 1939 | ret |= vgic_init_bitmap(&dist->irq_cfg, nr_cpus, nr_irqs); |
| 1940 | ret |= vgic_init_bytemap(&dist->irq_priority, nr_cpus, nr_irqs); |
| 1941 | |
| 1942 | if (ret) |
| 1943 | goto out; |
| 1944 | |
| 1945 | dist->irq_sgi_sources = kzalloc(nr_cpus * VGIC_NR_SGIS, GFP_KERNEL); |
| 1946 | dist->irq_spi_cpu = kzalloc(nr_irqs - VGIC_NR_PRIVATE_IRQS, GFP_KERNEL); |
| 1947 | dist->irq_spi_target = kzalloc(sizeof(*dist->irq_spi_target) * nr_cpus, |
| 1948 | GFP_KERNEL); |
| 1949 | dist->irq_pending_on_cpu = kzalloc(BITS_TO_LONGS(nr_cpus) * sizeof(long), |
| 1950 | GFP_KERNEL); |
| 1951 | if (!dist->irq_sgi_sources || |
| 1952 | !dist->irq_spi_cpu || |
| 1953 | !dist->irq_spi_target || |
| 1954 | !dist->irq_pending_on_cpu) { |
| 1955 | ret = -ENOMEM; |
| 1956 | goto out; |
| 1957 | } |
| 1958 | |
| 1959 | for (i = 0; i < nr_cpus; i++) |
| 1960 | ret |= vgic_init_bitmap(&dist->irq_spi_target[i], |
| 1961 | nr_cpus, nr_irqs); |
| 1962 | |
| 1963 | if (ret) |
| 1964 | goto out; |
| 1965 | |
Andre Przywara | b26e5fd | 2014-06-02 16:19:12 +0200 | [diff] [blame] | 1966 | ret = kvm->arch.vgic.vm_ops.init_model(kvm); |
| 1967 | if (ret) |
| 1968 | goto out; |
Peter Maydell | 6d3cfbe | 2014-12-04 15:02:24 +0000 | [diff] [blame] | 1969 | |
| 1970 | kvm_for_each_vcpu(vcpu_id, vcpu, kvm) { |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1971 | ret = vgic_vcpu_init_maps(vcpu, nr_irqs); |
| 1972 | if (ret) { |
| 1973 | kvm_err("VGIC: Failed to allocate vcpu memory\n"); |
| 1974 | break; |
| 1975 | } |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1976 | |
Peter Maydell | 6d3cfbe | 2014-12-04 15:02:24 +0000 | [diff] [blame] | 1977 | for (i = 0; i < dist->nr_irqs; i++) { |
| 1978 | if (i < VGIC_NR_PPIS) |
| 1979 | vgic_bitmap_set_irq_val(&dist->irq_enabled, |
| 1980 | vcpu->vcpu_id, i, 1); |
| 1981 | if (i < VGIC_NR_PRIVATE_IRQS) |
| 1982 | vgic_bitmap_set_irq_val(&dist->irq_cfg, |
| 1983 | vcpu->vcpu_id, i, |
| 1984 | VGIC_CFG_EDGE); |
| 1985 | } |
| 1986 | |
| 1987 | vgic_enable(vcpu); |
| 1988 | } |
Marc Zyngier | 4956f2b | 2014-07-08 12:09:06 +0100 | [diff] [blame] | 1989 | |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1990 | out: |
| 1991 | if (ret) |
| 1992 | kvm_vgic_destroy(kvm); |
| 1993 | |
| 1994 | return ret; |
| 1995 | } |
| 1996 | |
Christoffer Dall | e1ba020 | 2013-09-23 14:55:55 -0700 | [diff] [blame] | 1997 | /** |
Peter Maydell | 6d3cfbe | 2014-12-04 15:02:24 +0000 | [diff] [blame] | 1998 | * kvm_vgic_map_resources - Configure global VGIC state before running any VCPUs |
Christoffer Dall | e1ba020 | 2013-09-23 14:55:55 -0700 | [diff] [blame] | 1999 | * @kvm: pointer to the kvm struct |
| 2000 | * |
| 2001 | * Map the virtual CPU interface into the VM before running any VCPUs. We |
| 2002 | * can't do this at creation time, because user space must first set the |
Peter Maydell | 6d3cfbe | 2014-12-04 15:02:24 +0000 | [diff] [blame] | 2003 | * virtual CPU interface address in the guest physical address space. |
Christoffer Dall | e1ba020 | 2013-09-23 14:55:55 -0700 | [diff] [blame] | 2004 | */ |
Andre Przywara | b26e5fd | 2014-06-02 16:19:12 +0200 | [diff] [blame] | 2005 | static int vgic_v2_map_resources(struct kvm *kvm, |
| 2006 | const struct vgic_params *params) |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 2007 | { |
Peter Maydell | 6d3cfbe | 2014-12-04 15:02:24 +0000 | [diff] [blame] | 2008 | int ret = 0; |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 2009 | |
Christoffer Dall | e1ba020 | 2013-09-23 14:55:55 -0700 | [diff] [blame] | 2010 | if (!irqchip_in_kernel(kvm)) |
| 2011 | return 0; |
| 2012 | |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 2013 | mutex_lock(&kvm->lock); |
| 2014 | |
Christoffer Dall | c52edf5 | 2014-12-09 14:28:09 +0100 | [diff] [blame] | 2015 | if (vgic_ready(kvm)) |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 2016 | goto out; |
| 2017 | |
| 2018 | if (IS_VGIC_ADDR_UNDEF(kvm->arch.vgic.vgic_dist_base) || |
| 2019 | IS_VGIC_ADDR_UNDEF(kvm->arch.vgic.vgic_cpu_base)) { |
| 2020 | kvm_err("Need to set vgic cpu and dist addresses first\n"); |
| 2021 | ret = -ENXIO; |
| 2022 | goto out; |
| 2023 | } |
| 2024 | |
Peter Maydell | 6d3cfbe | 2014-12-04 15:02:24 +0000 | [diff] [blame] | 2025 | /* |
| 2026 | * Initialize the vgic if this hasn't already been done on demand by |
| 2027 | * accessing the vgic state from userspace. |
| 2028 | */ |
| 2029 | ret = vgic_init(kvm); |
Marc Zyngier | 4956f2b | 2014-07-08 12:09:06 +0100 | [diff] [blame] | 2030 | if (ret) { |
| 2031 | kvm_err("Unable to allocate maps\n"); |
| 2032 | goto out; |
| 2033 | } |
| 2034 | |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 2035 | ret = kvm_phys_addr_ioremap(kvm, kvm->arch.vgic.vgic_cpu_base, |
Andre Przywara | b26e5fd | 2014-06-02 16:19:12 +0200 | [diff] [blame] | 2036 | params->vcpu_base, KVM_VGIC_V2_CPU_SIZE, |
Ard Biesheuvel | c40f2f8 | 2014-09-17 14:56:18 -0700 | [diff] [blame] | 2037 | true); |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 2038 | if (ret) { |
| 2039 | kvm_err("Unable to remap VGIC CPU to VCPU\n"); |
| 2040 | goto out; |
| 2041 | } |
| 2042 | |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 2043 | kvm->arch.vgic.ready = true; |
| 2044 | out: |
Marc Zyngier | 4956f2b | 2014-07-08 12:09:06 +0100 | [diff] [blame] | 2045 | if (ret) |
| 2046 | kvm_vgic_destroy(kvm); |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 2047 | mutex_unlock(&kvm->lock); |
| 2048 | return ret; |
| 2049 | } |
| 2050 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 2051 | void vgic_v2_init_emulation(struct kvm *kvm) |
Andre Przywara | b26e5fd | 2014-06-02 16:19:12 +0200 | [diff] [blame] | 2052 | { |
| 2053 | struct vgic_dist *dist = &kvm->arch.vgic; |
| 2054 | |
| 2055 | dist->vm_ops.handle_mmio = vgic_v2_handle_mmio; |
| 2056 | dist->vm_ops.queue_sgi = vgic_v2_queue_sgi; |
| 2057 | dist->vm_ops.add_sgi_source = vgic_v2_add_sgi_source; |
| 2058 | dist->vm_ops.init_model = vgic_v2_init_model; |
| 2059 | dist->vm_ops.map_resources = vgic_v2_map_resources; |
Andre Przywara | 3caa2d8 | 2014-06-02 16:26:01 +0200 | [diff] [blame] | 2060 | |
| 2061 | kvm->arch.max_vcpus = VGIC_V2_MAX_CPUS; |
Andre Przywara | b26e5fd | 2014-06-02 16:19:12 +0200 | [diff] [blame] | 2062 | } |
| 2063 | |
| 2064 | static int init_vgic_model(struct kvm *kvm, int type) |
| 2065 | { |
| 2066 | switch (type) { |
| 2067 | case KVM_DEV_TYPE_ARM_VGIC_V2: |
| 2068 | vgic_v2_init_emulation(kvm); |
| 2069 | break; |
| 2070 | default: |
| 2071 | return -ENODEV; |
| 2072 | } |
| 2073 | |
Andre Przywara | 3caa2d8 | 2014-06-02 16:26:01 +0200 | [diff] [blame] | 2074 | if (atomic_read(&kvm->online_vcpus) > kvm->arch.max_vcpus) |
| 2075 | return -E2BIG; |
| 2076 | |
Andre Przywara | b26e5fd | 2014-06-02 16:19:12 +0200 | [diff] [blame] | 2077 | return 0; |
| 2078 | } |
| 2079 | |
Andre Przywara | 59892136 | 2014-06-03 09:33:10 +0200 | [diff] [blame] | 2080 | int kvm_vgic_create(struct kvm *kvm, u32 type) |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 2081 | { |
Christoffer Dall | 6b50f54 | 2014-11-06 11:47:39 +0000 | [diff] [blame] | 2082 | int i, vcpu_lock_idx = -1, ret; |
Christoffer Dall | 7330672 | 2013-10-25 17:29:18 +0100 | [diff] [blame] | 2083 | struct kvm_vcpu *vcpu; |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 2084 | |
| 2085 | mutex_lock(&kvm->lock); |
| 2086 | |
Andre Przywara | 4ce7ebd | 2014-10-26 23:18:14 +0000 | [diff] [blame] | 2087 | if (irqchip_in_kernel(kvm)) { |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 2088 | ret = -EEXIST; |
| 2089 | goto out; |
| 2090 | } |
| 2091 | |
Christoffer Dall | 7330672 | 2013-10-25 17:29:18 +0100 | [diff] [blame] | 2092 | /* |
| 2093 | * Any time a vcpu is run, vcpu_load is called which tries to grab the |
| 2094 | * vcpu->mutex. By grabbing the vcpu->mutex of all VCPUs we ensure |
| 2095 | * that no other VCPUs are run while we create the vgic. |
| 2096 | */ |
Christoffer Dall | 6b50f54 | 2014-11-06 11:47:39 +0000 | [diff] [blame] | 2097 | ret = -EBUSY; |
Christoffer Dall | 7330672 | 2013-10-25 17:29:18 +0100 | [diff] [blame] | 2098 | kvm_for_each_vcpu(i, vcpu, kvm) { |
| 2099 | if (!mutex_trylock(&vcpu->mutex)) |
| 2100 | goto out_unlock; |
| 2101 | vcpu_lock_idx = i; |
| 2102 | } |
| 2103 | |
| 2104 | kvm_for_each_vcpu(i, vcpu, kvm) { |
Christoffer Dall | 6b50f54 | 2014-11-06 11:47:39 +0000 | [diff] [blame] | 2105 | if (vcpu->arch.has_run_once) |
Christoffer Dall | 7330672 | 2013-10-25 17:29:18 +0100 | [diff] [blame] | 2106 | goto out_unlock; |
Christoffer Dall | 7330672 | 2013-10-25 17:29:18 +0100 | [diff] [blame] | 2107 | } |
Christoffer Dall | 6b50f54 | 2014-11-06 11:47:39 +0000 | [diff] [blame] | 2108 | ret = 0; |
Christoffer Dall | 7330672 | 2013-10-25 17:29:18 +0100 | [diff] [blame] | 2109 | |
Andre Przywara | b26e5fd | 2014-06-02 16:19:12 +0200 | [diff] [blame] | 2110 | ret = init_vgic_model(kvm, type); |
| 2111 | if (ret) |
| 2112 | goto out_unlock; |
| 2113 | |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 2114 | spin_lock_init(&kvm->arch.vgic.lock); |
Marc Zyngier | f982cf4 | 2014-05-15 10:03:25 +0100 | [diff] [blame] | 2115 | kvm->arch.vgic.in_kernel = true; |
Andre Przywara | 59892136 | 2014-06-03 09:33:10 +0200 | [diff] [blame] | 2116 | kvm->arch.vgic.vgic_model = type; |
Marc Zyngier | 8f186d5 | 2014-02-04 18:13:03 +0000 | [diff] [blame] | 2117 | kvm->arch.vgic.vctrl_base = vgic->vctrl_base; |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 2118 | kvm->arch.vgic.vgic_dist_base = VGIC_ADDR_UNDEF; |
| 2119 | kvm->arch.vgic.vgic_cpu_base = VGIC_ADDR_UNDEF; |
| 2120 | |
Christoffer Dall | 7330672 | 2013-10-25 17:29:18 +0100 | [diff] [blame] | 2121 | out_unlock: |
| 2122 | for (; vcpu_lock_idx >= 0; vcpu_lock_idx--) { |
| 2123 | vcpu = kvm_get_vcpu(kvm, vcpu_lock_idx); |
| 2124 | mutex_unlock(&vcpu->mutex); |
| 2125 | } |
| 2126 | |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 2127 | out: |
| 2128 | mutex_unlock(&kvm->lock); |
| 2129 | return ret; |
| 2130 | } |
| 2131 | |
Will Deacon | 1fa451b | 2014-08-26 15:13:24 +0100 | [diff] [blame] | 2132 | static int vgic_ioaddr_overlap(struct kvm *kvm) |
Christoffer Dall | 330690c | 2013-01-21 19:36:13 -0500 | [diff] [blame] | 2133 | { |
| 2134 | phys_addr_t dist = kvm->arch.vgic.vgic_dist_base; |
| 2135 | phys_addr_t cpu = kvm->arch.vgic.vgic_cpu_base; |
| 2136 | |
| 2137 | if (IS_VGIC_ADDR_UNDEF(dist) || IS_VGIC_ADDR_UNDEF(cpu)) |
| 2138 | return 0; |
| 2139 | if ((dist <= cpu && dist + KVM_VGIC_V2_DIST_SIZE > cpu) || |
| 2140 | (cpu <= dist && cpu + KVM_VGIC_V2_CPU_SIZE > dist)) |
| 2141 | return -EBUSY; |
| 2142 | return 0; |
| 2143 | } |
| 2144 | |
| 2145 | static int vgic_ioaddr_assign(struct kvm *kvm, phys_addr_t *ioaddr, |
| 2146 | phys_addr_t addr, phys_addr_t size) |
| 2147 | { |
| 2148 | int ret; |
| 2149 | |
Christoffer Dall | ce01e4e | 2013-09-23 14:55:56 -0700 | [diff] [blame] | 2150 | if (addr & ~KVM_PHYS_MASK) |
| 2151 | return -E2BIG; |
| 2152 | |
| 2153 | if (addr & (SZ_4K - 1)) |
| 2154 | return -EINVAL; |
| 2155 | |
Christoffer Dall | 330690c | 2013-01-21 19:36:13 -0500 | [diff] [blame] | 2156 | if (!IS_VGIC_ADDR_UNDEF(*ioaddr)) |
| 2157 | return -EEXIST; |
| 2158 | if (addr + size < addr) |
| 2159 | return -EINVAL; |
| 2160 | |
Haibin Wang | 30c2117 | 2014-04-29 14:49:17 +0800 | [diff] [blame] | 2161 | *ioaddr = addr; |
Christoffer Dall | 330690c | 2013-01-21 19:36:13 -0500 | [diff] [blame] | 2162 | ret = vgic_ioaddr_overlap(kvm); |
| 2163 | if (ret) |
Haibin Wang | 30c2117 | 2014-04-29 14:49:17 +0800 | [diff] [blame] | 2164 | *ioaddr = VGIC_ADDR_UNDEF; |
| 2165 | |
Christoffer Dall | 330690c | 2013-01-21 19:36:13 -0500 | [diff] [blame] | 2166 | return ret; |
| 2167 | } |
| 2168 | |
Christoffer Dall | ce01e4e | 2013-09-23 14:55:56 -0700 | [diff] [blame] | 2169 | /** |
| 2170 | * kvm_vgic_addr - set or get vgic VM base addresses |
| 2171 | * @kvm: pointer to the vm struct |
| 2172 | * @type: the VGIC addr type, one of KVM_VGIC_V2_ADDR_TYPE_XXX |
| 2173 | * @addr: pointer to address value |
| 2174 | * @write: if true set the address in the VM address space, if false read the |
| 2175 | * address |
| 2176 | * |
| 2177 | * Set or get the vgic base addresses for the distributor and the virtual CPU |
| 2178 | * interface in the VM physical address space. These addresses are properties |
| 2179 | * of the emulated core/SoC and therefore user space initially knows this |
| 2180 | * information. |
| 2181 | */ |
| 2182 | int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write) |
Christoffer Dall | 330690c | 2013-01-21 19:36:13 -0500 | [diff] [blame] | 2183 | { |
| 2184 | int r = 0; |
| 2185 | struct vgic_dist *vgic = &kvm->arch.vgic; |
| 2186 | |
Christoffer Dall | 330690c | 2013-01-21 19:36:13 -0500 | [diff] [blame] | 2187 | mutex_lock(&kvm->lock); |
| 2188 | switch (type) { |
| 2189 | case KVM_VGIC_V2_ADDR_TYPE_DIST: |
Christoffer Dall | ce01e4e | 2013-09-23 14:55:56 -0700 | [diff] [blame] | 2190 | if (write) { |
| 2191 | r = vgic_ioaddr_assign(kvm, &vgic->vgic_dist_base, |
| 2192 | *addr, KVM_VGIC_V2_DIST_SIZE); |
| 2193 | } else { |
| 2194 | *addr = vgic->vgic_dist_base; |
| 2195 | } |
Christoffer Dall | 330690c | 2013-01-21 19:36:13 -0500 | [diff] [blame] | 2196 | break; |
| 2197 | case KVM_VGIC_V2_ADDR_TYPE_CPU: |
Christoffer Dall | ce01e4e | 2013-09-23 14:55:56 -0700 | [diff] [blame] | 2198 | if (write) { |
| 2199 | r = vgic_ioaddr_assign(kvm, &vgic->vgic_cpu_base, |
| 2200 | *addr, KVM_VGIC_V2_CPU_SIZE); |
| 2201 | } else { |
| 2202 | *addr = vgic->vgic_cpu_base; |
| 2203 | } |
Christoffer Dall | 330690c | 2013-01-21 19:36:13 -0500 | [diff] [blame] | 2204 | break; |
| 2205 | default: |
| 2206 | r = -ENODEV; |
| 2207 | } |
| 2208 | |
| 2209 | mutex_unlock(&kvm->lock); |
| 2210 | return r; |
| 2211 | } |
Christoffer Dall | 7330672 | 2013-10-25 17:29:18 +0100 | [diff] [blame] | 2212 | |
Christoffer Dall | c07a019 | 2013-10-25 21:17:31 +0100 | [diff] [blame] | 2213 | static bool handle_cpu_mmio_misc(struct kvm_vcpu *vcpu, |
| 2214 | struct kvm_exit_mmio *mmio, phys_addr_t offset) |
| 2215 | { |
Christoffer Dall | fa20f5ae | 2013-09-23 14:55:57 -0700 | [diff] [blame] | 2216 | bool updated = false; |
Marc Zyngier | beee38b | 2014-02-04 17:48:10 +0000 | [diff] [blame] | 2217 | struct vgic_vmcr vmcr; |
| 2218 | u32 *vmcr_field; |
| 2219 | u32 reg; |
| 2220 | |
| 2221 | vgic_get_vmcr(vcpu, &vmcr); |
Christoffer Dall | fa20f5ae | 2013-09-23 14:55:57 -0700 | [diff] [blame] | 2222 | |
| 2223 | switch (offset & ~0x3) { |
| 2224 | case GIC_CPU_CTRL: |
Marc Zyngier | beee38b | 2014-02-04 17:48:10 +0000 | [diff] [blame] | 2225 | vmcr_field = &vmcr.ctlr; |
Christoffer Dall | fa20f5ae | 2013-09-23 14:55:57 -0700 | [diff] [blame] | 2226 | break; |
| 2227 | case GIC_CPU_PRIMASK: |
Marc Zyngier | beee38b | 2014-02-04 17:48:10 +0000 | [diff] [blame] | 2228 | vmcr_field = &vmcr.pmr; |
Christoffer Dall | fa20f5ae | 2013-09-23 14:55:57 -0700 | [diff] [blame] | 2229 | break; |
| 2230 | case GIC_CPU_BINPOINT: |
Marc Zyngier | beee38b | 2014-02-04 17:48:10 +0000 | [diff] [blame] | 2231 | vmcr_field = &vmcr.bpr; |
Christoffer Dall | fa20f5ae | 2013-09-23 14:55:57 -0700 | [diff] [blame] | 2232 | break; |
| 2233 | case GIC_CPU_ALIAS_BINPOINT: |
Marc Zyngier | beee38b | 2014-02-04 17:48:10 +0000 | [diff] [blame] | 2234 | vmcr_field = &vmcr.abpr; |
Christoffer Dall | fa20f5ae | 2013-09-23 14:55:57 -0700 | [diff] [blame] | 2235 | break; |
Marc Zyngier | beee38b | 2014-02-04 17:48:10 +0000 | [diff] [blame] | 2236 | default: |
| 2237 | BUG(); |
Christoffer Dall | fa20f5ae | 2013-09-23 14:55:57 -0700 | [diff] [blame] | 2238 | } |
| 2239 | |
| 2240 | if (!mmio->is_write) { |
Marc Zyngier | beee38b | 2014-02-04 17:48:10 +0000 | [diff] [blame] | 2241 | reg = *vmcr_field; |
Christoffer Dall | fa20f5ae | 2013-09-23 14:55:57 -0700 | [diff] [blame] | 2242 | mmio_data_write(mmio, ~0, reg); |
| 2243 | } else { |
| 2244 | reg = mmio_data_read(mmio, ~0); |
Marc Zyngier | beee38b | 2014-02-04 17:48:10 +0000 | [diff] [blame] | 2245 | if (reg != *vmcr_field) { |
| 2246 | *vmcr_field = reg; |
| 2247 | vgic_set_vmcr(vcpu, &vmcr); |
Christoffer Dall | fa20f5ae | 2013-09-23 14:55:57 -0700 | [diff] [blame] | 2248 | updated = true; |
Marc Zyngier | beee38b | 2014-02-04 17:48:10 +0000 | [diff] [blame] | 2249 | } |
Christoffer Dall | fa20f5ae | 2013-09-23 14:55:57 -0700 | [diff] [blame] | 2250 | } |
| 2251 | return updated; |
Christoffer Dall | c07a019 | 2013-10-25 21:17:31 +0100 | [diff] [blame] | 2252 | } |
| 2253 | |
Christoffer Dall | fa20f5ae | 2013-09-23 14:55:57 -0700 | [diff] [blame] | 2254 | static bool handle_mmio_abpr(struct kvm_vcpu *vcpu, |
| 2255 | struct kvm_exit_mmio *mmio, phys_addr_t offset) |
| 2256 | { |
| 2257 | return handle_cpu_mmio_misc(vcpu, mmio, GIC_CPU_ALIAS_BINPOINT); |
| 2258 | } |
| 2259 | |
| 2260 | static bool handle_cpu_mmio_ident(struct kvm_vcpu *vcpu, |
| 2261 | struct kvm_exit_mmio *mmio, |
| 2262 | phys_addr_t offset) |
| 2263 | { |
| 2264 | u32 reg; |
| 2265 | |
| 2266 | if (mmio->is_write) |
| 2267 | return false; |
| 2268 | |
| 2269 | /* GICC_IIDR */ |
| 2270 | reg = (PRODUCT_ID_KVM << 20) | |
| 2271 | (GICC_ARCH_VERSION_V2 << 16) | |
| 2272 | (IMPLEMENTER_ARM << 0); |
| 2273 | mmio_data_write(mmio, ~0, reg); |
| 2274 | return false; |
| 2275 | } |
| 2276 | |
| 2277 | /* |
| 2278 | * CPU Interface Register accesses - these are not accessed by the VM, but by |
| 2279 | * user space for saving and restoring VGIC state. |
| 2280 | */ |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 2281 | static const struct kvm_mmio_range vgic_cpu_ranges[] = { |
Christoffer Dall | c07a019 | 2013-10-25 21:17:31 +0100 | [diff] [blame] | 2282 | { |
| 2283 | .base = GIC_CPU_CTRL, |
| 2284 | .len = 12, |
| 2285 | .handle_mmio = handle_cpu_mmio_misc, |
| 2286 | }, |
| 2287 | { |
| 2288 | .base = GIC_CPU_ALIAS_BINPOINT, |
| 2289 | .len = 4, |
Christoffer Dall | fa20f5ae | 2013-09-23 14:55:57 -0700 | [diff] [blame] | 2290 | .handle_mmio = handle_mmio_abpr, |
Christoffer Dall | c07a019 | 2013-10-25 21:17:31 +0100 | [diff] [blame] | 2291 | }, |
| 2292 | { |
| 2293 | .base = GIC_CPU_ACTIVEPRIO, |
| 2294 | .len = 16, |
Christoffer Dall | fa20f5ae | 2013-09-23 14:55:57 -0700 | [diff] [blame] | 2295 | .handle_mmio = handle_mmio_raz_wi, |
Christoffer Dall | c07a019 | 2013-10-25 21:17:31 +0100 | [diff] [blame] | 2296 | }, |
| 2297 | { |
| 2298 | .base = GIC_CPU_IDENT, |
| 2299 | .len = 4, |
Christoffer Dall | fa20f5ae | 2013-09-23 14:55:57 -0700 | [diff] [blame] | 2300 | .handle_mmio = handle_cpu_mmio_ident, |
Christoffer Dall | c07a019 | 2013-10-25 21:17:31 +0100 | [diff] [blame] | 2301 | }, |
| 2302 | }; |
| 2303 | |
| 2304 | static int vgic_attr_regs_access(struct kvm_device *dev, |
| 2305 | struct kvm_device_attr *attr, |
| 2306 | u32 *reg, bool is_write) |
| 2307 | { |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 2308 | const struct kvm_mmio_range *r = NULL, *ranges; |
Christoffer Dall | c07a019 | 2013-10-25 21:17:31 +0100 | [diff] [blame] | 2309 | phys_addr_t offset; |
| 2310 | int ret, cpuid, c; |
| 2311 | struct kvm_vcpu *vcpu, *tmp_vcpu; |
| 2312 | struct vgic_dist *vgic; |
| 2313 | struct kvm_exit_mmio mmio; |
| 2314 | |
| 2315 | offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK; |
| 2316 | cpuid = (attr->attr & KVM_DEV_ARM_VGIC_CPUID_MASK) >> |
| 2317 | KVM_DEV_ARM_VGIC_CPUID_SHIFT; |
| 2318 | |
| 2319 | mutex_lock(&dev->kvm->lock); |
| 2320 | |
Peter Maydell | 6d3cfbe | 2014-12-04 15:02:24 +0000 | [diff] [blame] | 2321 | ret = vgic_init(dev->kvm); |
Marc Zyngier | 4956f2b | 2014-07-08 12:09:06 +0100 | [diff] [blame] | 2322 | if (ret) |
| 2323 | goto out; |
| 2324 | |
Christoffer Dall | c07a019 | 2013-10-25 21:17:31 +0100 | [diff] [blame] | 2325 | if (cpuid >= atomic_read(&dev->kvm->online_vcpus)) { |
| 2326 | ret = -EINVAL; |
| 2327 | goto out; |
| 2328 | } |
| 2329 | |
| 2330 | vcpu = kvm_get_vcpu(dev->kvm, cpuid); |
| 2331 | vgic = &dev->kvm->arch.vgic; |
| 2332 | |
| 2333 | mmio.len = 4; |
| 2334 | mmio.is_write = is_write; |
| 2335 | if (is_write) |
| 2336 | mmio_data_write(&mmio, ~0, *reg); |
| 2337 | switch (attr->group) { |
| 2338 | case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: |
| 2339 | mmio.phys_addr = vgic->vgic_dist_base + offset; |
| 2340 | ranges = vgic_dist_ranges; |
| 2341 | break; |
| 2342 | case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: |
| 2343 | mmio.phys_addr = vgic->vgic_cpu_base + offset; |
| 2344 | ranges = vgic_cpu_ranges; |
| 2345 | break; |
| 2346 | default: |
| 2347 | BUG(); |
| 2348 | } |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 2349 | r = vgic_find_range(ranges, &mmio, offset); |
Christoffer Dall | c07a019 | 2013-10-25 21:17:31 +0100 | [diff] [blame] | 2350 | |
| 2351 | if (unlikely(!r || !r->handle_mmio)) { |
| 2352 | ret = -ENXIO; |
| 2353 | goto out; |
| 2354 | } |
| 2355 | |
| 2356 | |
| 2357 | spin_lock(&vgic->lock); |
| 2358 | |
| 2359 | /* |
| 2360 | * Ensure that no other VCPU is running by checking the vcpu->cpu |
| 2361 | * field. If no other VPCUs are running we can safely access the VGIC |
| 2362 | * state, because even if another VPU is run after this point, that |
| 2363 | * VCPU will not touch the vgic state, because it will block on |
| 2364 | * getting the vgic->lock in kvm_vgic_sync_hwstate(). |
| 2365 | */ |
| 2366 | kvm_for_each_vcpu(c, tmp_vcpu, dev->kvm) { |
| 2367 | if (unlikely(tmp_vcpu->cpu != -1)) { |
| 2368 | ret = -EBUSY; |
| 2369 | goto out_vgic_unlock; |
| 2370 | } |
| 2371 | } |
| 2372 | |
Christoffer Dall | cbd333a | 2013-11-15 20:51:31 -0800 | [diff] [blame] | 2373 | /* |
| 2374 | * Move all pending IRQs from the LRs on all VCPUs so the pending |
| 2375 | * state can be properly represented in the register state accessible |
| 2376 | * through this API. |
| 2377 | */ |
| 2378 | kvm_for_each_vcpu(c, tmp_vcpu, dev->kvm) |
| 2379 | vgic_unqueue_irqs(tmp_vcpu); |
| 2380 | |
Christoffer Dall | c07a019 | 2013-10-25 21:17:31 +0100 | [diff] [blame] | 2381 | offset -= r->base; |
| 2382 | r->handle_mmio(vcpu, &mmio, offset); |
| 2383 | |
| 2384 | if (!is_write) |
| 2385 | *reg = mmio_data_read(&mmio, ~0); |
| 2386 | |
| 2387 | ret = 0; |
| 2388 | out_vgic_unlock: |
| 2389 | spin_unlock(&vgic->lock); |
| 2390 | out: |
| 2391 | mutex_unlock(&dev->kvm->lock); |
| 2392 | return ret; |
| 2393 | } |
| 2394 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 2395 | int vgic_set_common_attr(struct kvm_device *dev, struct kvm_device_attr *attr) |
Christoffer Dall | 7330672 | 2013-10-25 17:29:18 +0100 | [diff] [blame] | 2396 | { |
Christoffer Dall | ce01e4e | 2013-09-23 14:55:56 -0700 | [diff] [blame] | 2397 | int r; |
| 2398 | |
| 2399 | switch (attr->group) { |
| 2400 | case KVM_DEV_ARM_VGIC_GRP_ADDR: { |
| 2401 | u64 __user *uaddr = (u64 __user *)(long)attr->addr; |
| 2402 | u64 addr; |
| 2403 | unsigned long type = (unsigned long)attr->attr; |
| 2404 | |
| 2405 | if (copy_from_user(&addr, uaddr, sizeof(addr))) |
| 2406 | return -EFAULT; |
| 2407 | |
| 2408 | r = kvm_vgic_addr(dev->kvm, type, &addr, true); |
| 2409 | return (r == -ENODEV) ? -ENXIO : r; |
| 2410 | } |
Marc Zyngier | a98f26f | 2014-07-08 12:09:07 +0100 | [diff] [blame] | 2411 | case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: { |
| 2412 | u32 __user *uaddr = (u32 __user *)(long)attr->addr; |
| 2413 | u32 val; |
| 2414 | int ret = 0; |
| 2415 | |
| 2416 | if (get_user(val, uaddr)) |
| 2417 | return -EFAULT; |
| 2418 | |
| 2419 | /* |
| 2420 | * We require: |
| 2421 | * - at least 32 SPIs on top of the 16 SGIs and 16 PPIs |
| 2422 | * - at most 1024 interrupts |
| 2423 | * - a multiple of 32 interrupts |
| 2424 | */ |
| 2425 | if (val < (VGIC_NR_PRIVATE_IRQS + 32) || |
| 2426 | val > VGIC_MAX_IRQS || |
| 2427 | (val & 31)) |
| 2428 | return -EINVAL; |
| 2429 | |
| 2430 | mutex_lock(&dev->kvm->lock); |
| 2431 | |
Christoffer Dall | c52edf5 | 2014-12-09 14:28:09 +0100 | [diff] [blame] | 2432 | if (vgic_ready(dev->kvm) || dev->kvm->arch.vgic.nr_irqs) |
Marc Zyngier | a98f26f | 2014-07-08 12:09:07 +0100 | [diff] [blame] | 2433 | ret = -EBUSY; |
| 2434 | else |
| 2435 | dev->kvm->arch.vgic.nr_irqs = val; |
| 2436 | |
| 2437 | mutex_unlock(&dev->kvm->lock); |
| 2438 | |
| 2439 | return ret; |
| 2440 | } |
Eric Auger | 065c003 | 2014-12-15 18:43:33 +0100 | [diff] [blame] | 2441 | case KVM_DEV_ARM_VGIC_GRP_CTRL: { |
| 2442 | switch (attr->attr) { |
| 2443 | case KVM_DEV_ARM_VGIC_CTRL_INIT: |
| 2444 | r = vgic_init(dev->kvm); |
| 2445 | return r; |
| 2446 | } |
| 2447 | break; |
| 2448 | } |
Christoffer Dall | ce01e4e | 2013-09-23 14:55:56 -0700 | [diff] [blame] | 2449 | } |
| 2450 | |
Christoffer Dall | 7330672 | 2013-10-25 17:29:18 +0100 | [diff] [blame] | 2451 | return -ENXIO; |
| 2452 | } |
| 2453 | |
Andre Przywara | b60da14 | 2014-08-21 11:08:27 +0100 | [diff] [blame] | 2454 | static int vgic_set_attr(struct kvm_device *dev, struct kvm_device_attr *attr) |
| 2455 | { |
| 2456 | int ret; |
| 2457 | |
| 2458 | ret = vgic_set_common_attr(dev, attr); |
| 2459 | if (ret != -ENXIO) |
| 2460 | return ret; |
| 2461 | |
| 2462 | switch (attr->group) { |
| 2463 | case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: |
| 2464 | case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: { |
| 2465 | u32 __user *uaddr = (u32 __user *)(long)attr->addr; |
| 2466 | u32 reg; |
| 2467 | |
| 2468 | if (get_user(reg, uaddr)) |
| 2469 | return -EFAULT; |
| 2470 | |
| 2471 | return vgic_attr_regs_access(dev, attr, ®, true); |
| 2472 | } |
| 2473 | |
| 2474 | } |
| 2475 | |
| 2476 | return -ENXIO; |
| 2477 | } |
| 2478 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 2479 | int vgic_get_common_attr(struct kvm_device *dev, struct kvm_device_attr *attr) |
Christoffer Dall | 7330672 | 2013-10-25 17:29:18 +0100 | [diff] [blame] | 2480 | { |
Christoffer Dall | ce01e4e | 2013-09-23 14:55:56 -0700 | [diff] [blame] | 2481 | int r = -ENXIO; |
| 2482 | |
| 2483 | switch (attr->group) { |
| 2484 | case KVM_DEV_ARM_VGIC_GRP_ADDR: { |
| 2485 | u64 __user *uaddr = (u64 __user *)(long)attr->addr; |
| 2486 | u64 addr; |
| 2487 | unsigned long type = (unsigned long)attr->attr; |
| 2488 | |
| 2489 | r = kvm_vgic_addr(dev->kvm, type, &addr, false); |
| 2490 | if (r) |
| 2491 | return (r == -ENODEV) ? -ENXIO : r; |
| 2492 | |
| 2493 | if (copy_to_user(uaddr, &addr, sizeof(addr))) |
| 2494 | return -EFAULT; |
Christoffer Dall | c07a019 | 2013-10-25 21:17:31 +0100 | [diff] [blame] | 2495 | break; |
Christoffer Dall | ce01e4e | 2013-09-23 14:55:56 -0700 | [diff] [blame] | 2496 | } |
Marc Zyngier | a98f26f | 2014-07-08 12:09:07 +0100 | [diff] [blame] | 2497 | case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: { |
| 2498 | u32 __user *uaddr = (u32 __user *)(long)attr->addr; |
Andre Przywara | b60da14 | 2014-08-21 11:08:27 +0100 | [diff] [blame] | 2499 | |
Marc Zyngier | a98f26f | 2014-07-08 12:09:07 +0100 | [diff] [blame] | 2500 | r = put_user(dev->kvm->arch.vgic.nr_irqs, uaddr); |
| 2501 | break; |
| 2502 | } |
Christoffer Dall | c07a019 | 2013-10-25 21:17:31 +0100 | [diff] [blame] | 2503 | |
Christoffer Dall | ce01e4e | 2013-09-23 14:55:56 -0700 | [diff] [blame] | 2504 | } |
| 2505 | |
| 2506 | return r; |
Christoffer Dall | 7330672 | 2013-10-25 17:29:18 +0100 | [diff] [blame] | 2507 | } |
| 2508 | |
Andre Przywara | b60da14 | 2014-08-21 11:08:27 +0100 | [diff] [blame] | 2509 | static int vgic_get_attr(struct kvm_device *dev, struct kvm_device_attr *attr) |
| 2510 | { |
| 2511 | int ret; |
| 2512 | |
| 2513 | ret = vgic_get_common_attr(dev, attr); |
| 2514 | if (ret != -ENXIO) |
| 2515 | return ret; |
| 2516 | |
| 2517 | switch (attr->group) { |
| 2518 | case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: |
| 2519 | case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: { |
| 2520 | u32 __user *uaddr = (u32 __user *)(long)attr->addr; |
| 2521 | u32 reg = 0; |
| 2522 | |
| 2523 | ret = vgic_attr_regs_access(dev, attr, ®, false); |
| 2524 | if (ret) |
| 2525 | return ret; |
| 2526 | return put_user(reg, uaddr); |
| 2527 | } |
| 2528 | |
| 2529 | } |
| 2530 | |
| 2531 | return -ENXIO; |
| 2532 | } |
| 2533 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 2534 | int vgic_has_attr_regs(const struct kvm_mmio_range *ranges, phys_addr_t offset) |
Christoffer Dall | c07a019 | 2013-10-25 21:17:31 +0100 | [diff] [blame] | 2535 | { |
| 2536 | struct kvm_exit_mmio dev_attr_mmio; |
| 2537 | |
| 2538 | dev_attr_mmio.len = 4; |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 2539 | if (vgic_find_range(ranges, &dev_attr_mmio, offset)) |
Christoffer Dall | c07a019 | 2013-10-25 21:17:31 +0100 | [diff] [blame] | 2540 | return 0; |
| 2541 | else |
| 2542 | return -ENXIO; |
| 2543 | } |
| 2544 | |
Christoffer Dall | 7330672 | 2013-10-25 17:29:18 +0100 | [diff] [blame] | 2545 | static int vgic_has_attr(struct kvm_device *dev, struct kvm_device_attr *attr) |
| 2546 | { |
Christoffer Dall | c07a019 | 2013-10-25 21:17:31 +0100 | [diff] [blame] | 2547 | phys_addr_t offset; |
| 2548 | |
Christoffer Dall | ce01e4e | 2013-09-23 14:55:56 -0700 | [diff] [blame] | 2549 | switch (attr->group) { |
| 2550 | case KVM_DEV_ARM_VGIC_GRP_ADDR: |
| 2551 | switch (attr->attr) { |
| 2552 | case KVM_VGIC_V2_ADDR_TYPE_DIST: |
| 2553 | case KVM_VGIC_V2_ADDR_TYPE_CPU: |
| 2554 | return 0; |
| 2555 | } |
| 2556 | break; |
Christoffer Dall | c07a019 | 2013-10-25 21:17:31 +0100 | [diff] [blame] | 2557 | case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: |
| 2558 | offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK; |
| 2559 | return vgic_has_attr_regs(vgic_dist_ranges, offset); |
| 2560 | case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: |
| 2561 | offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK; |
| 2562 | return vgic_has_attr_regs(vgic_cpu_ranges, offset); |
Marc Zyngier | a98f26f | 2014-07-08 12:09:07 +0100 | [diff] [blame] | 2563 | case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: |
| 2564 | return 0; |
Eric Auger | 065c003 | 2014-12-15 18:43:33 +0100 | [diff] [blame] | 2565 | case KVM_DEV_ARM_VGIC_GRP_CTRL: |
| 2566 | switch (attr->attr) { |
| 2567 | case KVM_DEV_ARM_VGIC_CTRL_INIT: |
| 2568 | return 0; |
| 2569 | } |
Christoffer Dall | ce01e4e | 2013-09-23 14:55:56 -0700 | [diff] [blame] | 2570 | } |
Christoffer Dall | 7330672 | 2013-10-25 17:29:18 +0100 | [diff] [blame] | 2571 | return -ENXIO; |
| 2572 | } |
| 2573 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 2574 | void vgic_destroy(struct kvm_device *dev) |
Christoffer Dall | 7330672 | 2013-10-25 17:29:18 +0100 | [diff] [blame] | 2575 | { |
| 2576 | kfree(dev); |
| 2577 | } |
| 2578 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame^] | 2579 | int vgic_create(struct kvm_device *dev, u32 type) |
Christoffer Dall | 7330672 | 2013-10-25 17:29:18 +0100 | [diff] [blame] | 2580 | { |
Andre Przywara | 59892136 | 2014-06-03 09:33:10 +0200 | [diff] [blame] | 2581 | return kvm_vgic_create(dev->kvm, type); |
Christoffer Dall | 7330672 | 2013-10-25 17:29:18 +0100 | [diff] [blame] | 2582 | } |
| 2583 | |
Andre Przywara | ea2f83a | 2014-10-26 23:17:00 +0000 | [diff] [blame] | 2584 | struct kvm_device_ops kvm_arm_vgic_v2_ops = { |
Christoffer Dall | 7330672 | 2013-10-25 17:29:18 +0100 | [diff] [blame] | 2585 | .name = "kvm-arm-vgic", |
| 2586 | .create = vgic_create, |
| 2587 | .destroy = vgic_destroy, |
| 2588 | .set_attr = vgic_set_attr, |
| 2589 | .get_attr = vgic_get_attr, |
| 2590 | .has_attr = vgic_has_attr, |
| 2591 | }; |
Will Deacon | c06a841 | 2014-09-02 10:27:34 +0100 | [diff] [blame] | 2592 | |
| 2593 | static void vgic_init_maintenance_interrupt(void *info) |
| 2594 | { |
| 2595 | enable_percpu_irq(vgic->maint_irq, 0); |
| 2596 | } |
| 2597 | |
| 2598 | static int vgic_cpu_notify(struct notifier_block *self, |
| 2599 | unsigned long action, void *cpu) |
| 2600 | { |
| 2601 | switch (action) { |
| 2602 | case CPU_STARTING: |
| 2603 | case CPU_STARTING_FROZEN: |
| 2604 | vgic_init_maintenance_interrupt(NULL); |
| 2605 | break; |
| 2606 | case CPU_DYING: |
| 2607 | case CPU_DYING_FROZEN: |
| 2608 | disable_percpu_irq(vgic->maint_irq); |
| 2609 | break; |
| 2610 | } |
| 2611 | |
| 2612 | return NOTIFY_OK; |
| 2613 | } |
| 2614 | |
| 2615 | static struct notifier_block vgic_cpu_nb = { |
| 2616 | .notifier_call = vgic_cpu_notify, |
| 2617 | }; |
| 2618 | |
| 2619 | static const struct of_device_id vgic_ids[] = { |
| 2620 | { .compatible = "arm,cortex-a15-gic", .data = vgic_v2_probe, }, |
| 2621 | { .compatible = "arm,gic-v3", .data = vgic_v3_probe, }, |
| 2622 | {}, |
| 2623 | }; |
| 2624 | |
| 2625 | int kvm_vgic_hyp_init(void) |
| 2626 | { |
| 2627 | const struct of_device_id *matched_id; |
Christoffer Dall | a875daf | 2014-09-18 18:15:32 -0700 | [diff] [blame] | 2628 | const int (*vgic_probe)(struct device_node *,const struct vgic_ops **, |
| 2629 | const struct vgic_params **); |
Will Deacon | c06a841 | 2014-09-02 10:27:34 +0100 | [diff] [blame] | 2630 | struct device_node *vgic_node; |
| 2631 | int ret; |
| 2632 | |
| 2633 | vgic_node = of_find_matching_node_and_match(NULL, |
| 2634 | vgic_ids, &matched_id); |
| 2635 | if (!vgic_node) { |
| 2636 | kvm_err("error: no compatible GIC node found\n"); |
| 2637 | return -ENODEV; |
| 2638 | } |
| 2639 | |
| 2640 | vgic_probe = matched_id->data; |
| 2641 | ret = vgic_probe(vgic_node, &vgic_ops, &vgic); |
| 2642 | if (ret) |
| 2643 | return ret; |
| 2644 | |
| 2645 | ret = request_percpu_irq(vgic->maint_irq, vgic_maintenance_handler, |
| 2646 | "vgic", kvm_get_running_vcpus()); |
| 2647 | if (ret) { |
| 2648 | kvm_err("Cannot register interrupt %d\n", vgic->maint_irq); |
| 2649 | return ret; |
| 2650 | } |
| 2651 | |
| 2652 | ret = __register_cpu_notifier(&vgic_cpu_nb); |
| 2653 | if (ret) { |
| 2654 | kvm_err("Cannot register vgic CPU notifier\n"); |
| 2655 | goto out_free_irq; |
| 2656 | } |
| 2657 | |
| 2658 | /* Callback into for arch code for setup */ |
| 2659 | vgic_arch_setup(vgic); |
| 2660 | |
| 2661 | on_each_cpu(vgic_init_maintenance_interrupt, NULL, 1); |
| 2662 | |
Andre Przywara | ea2f83a | 2014-10-26 23:17:00 +0000 | [diff] [blame] | 2663 | return 0; |
Will Deacon | c06a841 | 2014-09-02 10:27:34 +0100 | [diff] [blame] | 2664 | |
| 2665 | out_free_irq: |
| 2666 | free_percpu_irq(vgic->maint_irq, kvm_get_running_vcpus()); |
| 2667 | return ret; |
| 2668 | } |