| David E. Box | 997ab40 | 2013-12-19 10:37:22 -0800 | [diff] [blame] | 1 | /* |
| 2 | * intel_baytrail.h: MailBox access support for Intel BayTrail platforms |
| 3 | */ |
| 4 | |
| 5 | #ifndef INTEL_BAYTRAIL_MBI_SYMS_H |
| 6 | #define INTEL_BAYTRAIL_MBI_SYMS_H |
| 7 | |
| 8 | #define BT_MBI_MCR_OFFSET 0xD0 |
| 9 | #define BT_MBI_MDR_OFFSET 0xD4 |
| 10 | #define BT_MBI_MCRX_OFFSET 0xD8 |
| 11 | |
| 12 | #define BT_MBI_RD_MASK 0xFEFFFFFF |
| 13 | #define BT_MBI_WR_MASK 0X01000000 |
| 14 | |
| 15 | #define BT_MBI_MASK_HI 0xFFFFFF00 |
| 16 | #define BT_MBI_MASK_LO 0x000000FF |
| 17 | #define BT_MBI_ENABLE 0xF0 |
| 18 | |
| 19 | /* BT-SB unit access methods */ |
| 20 | #define BT_MBI_UNIT_AUNIT 0x00 |
| 21 | #define BT_MBI_UNIT_SMC 0x01 |
| 22 | #define BT_MBI_UNIT_CPU 0x02 |
| 23 | #define BT_MBI_UNIT_BUNIT 0x03 |
| 24 | #define BT_MBI_UNIT_PMC 0x04 |
| 25 | #define BT_MBI_UNIT_GFX 0x06 |
| 26 | #define BT_MBI_UNIT_SMI 0x0C |
| 27 | #define BT_MBI_UNIT_USB 0x43 |
| 28 | #define BT_MBI_UNIT_SATA 0xA3 |
| 29 | #define BT_MBI_UNIT_PCIE 0xA6 |
| 30 | |
| 31 | /* Read/write opcodes */ |
| 32 | #define BT_MBI_AUNIT_READ 0x10 |
| 33 | #define BT_MBI_AUNIT_WRITE 0x11 |
| 34 | #define BT_MBI_SMC_READ 0x10 |
| 35 | #define BT_MBI_SMC_WRITE 0x11 |
| 36 | #define BT_MBI_CPU_READ 0x10 |
| 37 | #define BT_MBI_CPU_WRITE 0x11 |
| 38 | #define BT_MBI_BUNIT_READ 0x10 |
| 39 | #define BT_MBI_BUNIT_WRITE 0x11 |
| 40 | #define BT_MBI_PMC_READ 0x06 |
| 41 | #define BT_MBI_PMC_WRITE 0x07 |
| 42 | #define BT_MBI_GFX_READ 0x00 |
| 43 | #define BT_MBI_GFX_WRITE 0x01 |
| 44 | #define BT_MBI_SMIO_READ 0x06 |
| 45 | #define BT_MBI_SMIO_WRITE 0x07 |
| 46 | #define BT_MBI_USB_READ 0x06 |
| 47 | #define BT_MBI_USB_WRITE 0x07 |
| 48 | #define BT_MBI_SATA_READ 0x00 |
| 49 | #define BT_MBI_SATA_WRITE 0x01 |
| 50 | #define BT_MBI_PCIE_READ 0x00 |
| 51 | #define BT_MBI_PCIE_WRITE 0x01 |
| 52 | |
| 53 | /** |
| 54 | * bt_mbi_read() - MailBox Interface read command |
| 55 | * @port: port indicating subunit being accessed |
| 56 | * @opcode: port specific read or write opcode |
| 57 | * @offset: register address offset |
| 58 | * @mdr: register data to be read |
| 59 | * |
| 60 | * Locking is handled by spinlock - cannot sleep. |
| 61 | * Return: Nonzero on error |
| 62 | */ |
| 63 | int bt_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr); |
| 64 | |
| 65 | /** |
| 66 | * bt_mbi_write() - MailBox unmasked write command |
| 67 | * @port: port indicating subunit being accessed |
| 68 | * @opcode: port specific read or write opcode |
| 69 | * @offset: register address offset |
| 70 | * @mdr: register data to be written |
| 71 | * |
| 72 | * Locking is handled by spinlock - cannot sleep. |
| 73 | * Return: Nonzero on error |
| 74 | */ |
| 75 | int bt_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr); |
| 76 | |
| 77 | /** |
| 78 | * bt_mbi_modify() - MailBox masked write command |
| 79 | * @port: port indicating subunit being accessed |
| 80 | * @opcode: port specific read or write opcode |
| 81 | * @offset: register address offset |
| 82 | * @mdr: register data being modified |
| 83 | * @mask: mask indicating bits in mdr to be modified |
| 84 | * |
| 85 | * Locking is handled by spinlock - cannot sleep. |
| 86 | * Return: Nonzero on error |
| 87 | */ |
| 88 | int bt_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask); |
| 89 | |
| 90 | #endif /* INTEL_BAYTRAIL_MBI_SYMS_H */ |