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Shawn Guo289569f2010-12-18 21:39:28 +08001/*
2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/irq.h>
Shawn Guo83a84ef2012-08-20 21:34:56 +080022#include <linux/irqdomain.h>
Shawn Guo289569f2010-12-18 21:39:28 +080023#include <linux/io.h>
Shawn Guo83a84ef2012-08-20 21:34:56 +080024#include <linux/of.h>
25#include <linux/of_irq.h>
Shawn Guo4e0a1b82012-08-20 10:14:56 +080026#include <asm/exception.h>
Shawn Guo289569f2010-12-18 21:39:28 +080027#include <mach/mxs.h>
28#include <mach/common.h>
29
30#define HW_ICOLL_VECTOR 0x0000
31#define HW_ICOLL_LEVELACK 0x0010
32#define HW_ICOLL_CTRL 0x0020
Shawn Guo4e0a1b82012-08-20 10:14:56 +080033#define HW_ICOLL_STAT_OFFSET 0x0070
Shawn Guo289569f2010-12-18 21:39:28 +080034#define HW_ICOLL_INTERRUPTn_SET(n) (0x0124 + (n) * 0x10)
35#define HW_ICOLL_INTERRUPTn_CLR(n) (0x0128 + (n) * 0x10)
36#define BM_ICOLL_INTERRUPTn_ENABLE 0x00000004
37#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1
38
Shawn Guo83a84ef2012-08-20 21:34:56 +080039#define ICOLL_NUM_IRQS 128
40
Shawn Guo289569f2010-12-18 21:39:28 +080041static void __iomem *icoll_base = MXS_IO_ADDRESS(MXS_ICOLL_BASE_ADDR);
Shawn Guo83a84ef2012-08-20 21:34:56 +080042static struct irq_domain *icoll_domain;
Shawn Guo289569f2010-12-18 21:39:28 +080043
Uwe Kleine-Königbf0c11182011-02-18 21:31:41 +010044static void icoll_ack_irq(struct irq_data *d)
Shawn Guo289569f2010-12-18 21:39:28 +080045{
46 /*
47 * The Interrupt Collector is able to prioritize irqs.
48 * Currently only level 0 is used. So acking can use
49 * BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 unconditionally.
50 */
51 __raw_writel(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0,
52 icoll_base + HW_ICOLL_LEVELACK);
53}
54
Uwe Kleine-Königbf0c11182011-02-18 21:31:41 +010055static void icoll_mask_irq(struct irq_data *d)
Shawn Guo289569f2010-12-18 21:39:28 +080056{
57 __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE,
Shawn Guo83a84ef2012-08-20 21:34:56 +080058 icoll_base + HW_ICOLL_INTERRUPTn_CLR(d->hwirq));
Shawn Guo289569f2010-12-18 21:39:28 +080059}
60
Uwe Kleine-Königbf0c11182011-02-18 21:31:41 +010061static void icoll_unmask_irq(struct irq_data *d)
Shawn Guo289569f2010-12-18 21:39:28 +080062{
63 __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE,
Shawn Guo83a84ef2012-08-20 21:34:56 +080064 icoll_base + HW_ICOLL_INTERRUPTn_SET(d->hwirq));
Shawn Guo289569f2010-12-18 21:39:28 +080065}
66
67static struct irq_chip mxs_icoll_chip = {
Uwe Kleine-Königbf0c11182011-02-18 21:31:41 +010068 .irq_ack = icoll_ack_irq,
69 .irq_mask = icoll_mask_irq,
70 .irq_unmask = icoll_unmask_irq,
Shawn Guo289569f2010-12-18 21:39:28 +080071};
72
Shawn Guo4e0a1b82012-08-20 10:14:56 +080073asmlinkage void __exception_irq_entry icoll_handle_irq(struct pt_regs *regs)
74{
75 u32 irqnr;
76
77 do {
78 irqnr = __raw_readl(icoll_base + HW_ICOLL_STAT_OFFSET);
79 if (irqnr != 0x7f) {
80 __raw_writel(irqnr, icoll_base + HW_ICOLL_VECTOR);
Shawn Guo83a84ef2012-08-20 21:34:56 +080081 irqnr = irq_find_mapping(icoll_domain, irqnr);
Shawn Guo4e0a1b82012-08-20 10:14:56 +080082 handle_IRQ(irqnr, regs);
83 continue;
84 }
85 break;
86 } while (1);
87}
88
Shawn Guo83a84ef2012-08-20 21:34:56 +080089static int icoll_irq_domain_map(struct irq_domain *d, unsigned int virq,
90 irq_hw_number_t hw)
Shawn Guo289569f2010-12-18 21:39:28 +080091{
Shawn Guo83a84ef2012-08-20 21:34:56 +080092 irq_set_chip_and_handler(virq, &mxs_icoll_chip, handle_level_irq);
93 set_irq_flags(virq, IRQF_VALID);
Shawn Guo289569f2010-12-18 21:39:28 +080094
Shawn Guo83a84ef2012-08-20 21:34:56 +080095 return 0;
96}
97
98static struct irq_domain_ops icoll_irq_domain_ops = {
99 .map = icoll_irq_domain_map,
100 .xlate = irq_domain_xlate_onecell,
101};
102
103void __init icoll_of_init(struct device_node *np,
104 struct device_node *interrupt_parent)
105{
Shawn Guo289569f2010-12-18 21:39:28 +0800106 /*
107 * Interrupt Collector reset, which initializes the priority
108 * for each irq to level 0.
109 */
110 mxs_reset_block(icoll_base + HW_ICOLL_CTRL);
111
Shawn Guo83a84ef2012-08-20 21:34:56 +0800112 icoll_domain = irq_domain_add_linear(np, ICOLL_NUM_IRQS,
113 &icoll_irq_domain_ops, NULL);
114 WARN_ON(!icoll_domain);
115}
116
117static const struct of_device_id icoll_of_match[] __initconst = {
118 {.compatible = "fsl,icoll", .data = icoll_of_init},
119 { /* sentinel */ }
120};
121
122void __init icoll_init_irq(void)
123{
124 of_irq_init(icoll_of_match);
Shawn Guo289569f2010-12-18 21:39:28 +0800125}