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gerrit-public.fairphone.software / kernel / msm-4.9 / 84043ac26ed120826db8e6198531da888c6e57b0 / . / arch / arm / mach-omap2 / cm2xxx_3xxx.c
blob: 7f07ab02a5b3f8d706daff3ff4f34e27fc7fb0ae [file] [log] [blame]
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]1/*
2 * OMAP2/3 CM module functions
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]13#include <linux/types.h>
14#include <linux/delay.h>
15#include <linux/spinlock.h>
16#include <linux/list.h>
17#include <linux/errno.h>
18#include <linux/err.h>
19#include <linux/io.h>
20
Tony Lindgrendbc04162012-08-31 10:59:07 -0700[diff] [blame]21#include "soc.h"
Tony Lindgrenee0839c2012-02-24 10:34:35 -0800[diff] [blame]22#include "iomap.h"
Tony Lindgren4e653312011-11-10 22:45:17 +0100[diff] [blame]23#include "common.h"
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]24#include "cm.h"
Paul Walmsley59fb6592010-12-21 15:30:55 -0700[diff] [blame]25#include "cm2xxx_3xxx.h"
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]26#include "cm-regbits-24xx.h"
27#include "cm-regbits-34xx.h"
28
Paul Walmsley92618ff2011-02-25 15:39:27 -0700[diff] [blame]29/* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
Paul Walmsley0fd0c212011-02-25 15:49:53 -0700[diff] [blame]30#define DPLL_AUTOIDLE_DISABLE 0x0
31#define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP 0x3
32
Paul Walmsley92618ff2011-02-25 15:39:27 -0700[diff] [blame]33/* CM_AUTOIDLE_PLL.AUTO_* bit values for APLLs (OMAP2xxx only) */
34#define OMAP2XXX_APLL_AUTOIDLE_DISABLE 0x0
35#define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP 0x3
36
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]37static const u8 cm_idlest_offs[] = {
Paul Walmsleye9b0a2f2012-09-23 17:28:25 -0600[diff] [blame]38 CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3, OMAP24XX_CM_IDLEST4
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]39};
40
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]41u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
Paul Walmsley59fb6592010-12-21 15:30:55 -0700[diff] [blame]42{
43 return __raw_readl(cm_base + module + idx);
44}
45
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]46void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx)
Paul Walmsley59fb6592010-12-21 15:30:55 -0700[diff] [blame]47{
48 __raw_writel(val, cm_base + module + idx);
49}
50
51/* Read-modify-write a register in a CM module. Caller must lock */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]52u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
Paul Walmsley59fb6592010-12-21 15:30:55 -0700[diff] [blame]53{
54 u32 v;
55
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]56 v = omap2_cm_read_mod_reg(module, idx);
Paul Walmsley59fb6592010-12-21 15:30:55 -0700[diff] [blame]57 v &= ~mask;
58 v |= bits;
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]59 omap2_cm_write_mod_reg(v, module, idx);
Paul Walmsley59fb6592010-12-21 15:30:55 -0700[diff] [blame]60
61 return v;
62}
63
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]64u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
Paul Walmsley59fb6592010-12-21 15:30:55 -0700[diff] [blame]65{
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]66 return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx);
Paul Walmsley59fb6592010-12-21 15:30:55 -0700[diff] [blame]67}
68
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]69u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
Paul Walmsley59fb6592010-12-21 15:30:55 -0700[diff] [blame]70{
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]71 return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
Paul Walmsley59fb6592010-12-21 15:30:55 -0700[diff] [blame]72}
73
Paul Walmsley55ae3502010-12-21 21:05:15 -0700[diff] [blame]74/*
75 *
76 */
77
78static void _write_clktrctrl(u8 c, s16 module, u32 mask)
79{
80 u32 v;
81
82 v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
83 v &= ~mask;
84 v |= c << __ffs(mask);
85 omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
86}
87
88bool omap2_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
89{
90 u32 v;
91 bool ret = 0;
92
93 BUG_ON(!cpu_is_omap24xx() && !cpu_is_omap34xx());
94
95 v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
96 v &= mask;
97 v >>= __ffs(mask);
98
99 if (cpu_is_omap24xx())
100 ret = (v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
101 else
102 ret = (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
103
104 return ret;
105}
106
107void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
108{
109 _write_clktrctrl(OMAP24XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
110}
111
112void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
113{
114 _write_clktrctrl(OMAP24XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
115}
116
117void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
118{
119 _write_clktrctrl(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
120}
121
122void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
123{
124 _write_clktrctrl(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
125}
126
127void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask)
128{
129 _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, module, mask);
130}
131
132void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask)
133{
134 _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, module, mask);
135}
136
Paul Walmsley0fd0c212011-02-25 15:49:53 -0700[diff] [blame]137/*
138 * DPLL autoidle control
139 */
140
141static void _omap2xxx_set_dpll_autoidle(u8 m)
142{
143 u32 v;
144
145 v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
146 v &= ~OMAP24XX_AUTO_DPLL_MASK;
147 v |= m << OMAP24XX_AUTO_DPLL_SHIFT;
148 omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
149}
150
151void omap2xxx_cm_set_dpll_disable_autoidle(void)
152{
153 _omap2xxx_set_dpll_autoidle(OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP);
154}
155
156void omap2xxx_cm_set_dpll_auto_low_power_stop(void)
157{
158 _omap2xxx_set_dpll_autoidle(DPLL_AUTOIDLE_DISABLE);
159}
Paul Walmsley55ae3502010-12-21 21:05:15 -0700[diff] [blame]160
161/*
Paul Walmsley92618ff2011-02-25 15:39:27 -0700[diff] [blame]162 * APLL autoidle control
163 */
164
165static void _omap2xxx_set_apll_autoidle(u8 m, u32 mask)
166{
167 u32 v;
168
169 v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
170 v &= ~mask;
171 v |= m << __ffs(mask);
172 omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
173}
174
175void omap2xxx_cm_set_apll54_disable_autoidle(void)
176{
177 _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
178 OMAP24XX_AUTO_54M_MASK);
179}
180
181void omap2xxx_cm_set_apll54_auto_low_power_stop(void)
182{
183 _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
184 OMAP24XX_AUTO_54M_MASK);
185}
186
187void omap2xxx_cm_set_apll96_disable_autoidle(void)
188{
189 _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
190 OMAP24XX_AUTO_96M_MASK);
191}
192
193void omap2xxx_cm_set_apll96_auto_low_power_stop(void)
194{
195 _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
196 OMAP24XX_AUTO_96M_MASK);
197}
198
199/*
Paul Walmsley55ae3502010-12-21 21:05:15 -0700[diff] [blame]200 *
201 */
202
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]203/**
204 * omap2_cm_wait_idlest_ready - wait for a module to leave idle or standby
205 * @prcm_mod: PRCM module offset
206 * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
207 * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
208 *
209 * XXX document
210 */
211int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
212{
213 int ena = 0, i = 0;
214 u8 cm_idlest_reg;
215 u32 mask;
216
217 if (!idlest_id || (idlest_id > ARRAY_SIZE(cm_idlest_offs)))
218 return -EINVAL;
219
220 cm_idlest_reg = cm_idlest_offs[idlest_id - 1];
221
Kevin Hilman64056162010-07-26 16:34:28 -0600[diff] [blame]222 mask = 1 << idlest_shift;
223
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]224 if (cpu_is_omap24xx())
Kevin Hilman64056162010-07-26 16:34:28 -0600[diff] [blame]225 ena = mask;
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]226 else if (cpu_is_omap34xx())
227 ena = 0;
228 else
229 BUG();
230
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]231 omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena),
Paul Walmsley6f8b7ff2009-12-08 16:33:16 -0700[diff] [blame]232 MAX_MODULE_READY_TIME, i);
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]233
234 return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
235}
236
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]237/*
238 * Context save/restore code - OMAP3 only
239 */
240#ifdef CONFIG_ARCH_OMAP3
241struct omap3_cm_regs {
242 u32 iva2_cm_clksel1;
243 u32 iva2_cm_clksel2;
244 u32 cm_sysconfig;
245 u32 sgx_cm_clksel;
246 u32 dss_cm_clksel;
247 u32 cam_cm_clksel;
248 u32 per_cm_clksel;
249 u32 emu_cm_clksel;
250 u32 emu_cm_clkstctrl;
Eduardo Valentina8ae6452011-04-13 18:21:07 +0300[diff] [blame]251 u32 pll_cm_autoidle;
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]252 u32 pll_cm_autoidle2;
253 u32 pll_cm_clksel4;
254 u32 pll_cm_clksel5;
255 u32 pll_cm_clken2;
256 u32 cm_polctrl;
257 u32 iva2_cm_fclken;
258 u32 iva2_cm_clken_pll;
259 u32 core_cm_fclken1;
260 u32 core_cm_fclken3;
261 u32 sgx_cm_fclken;
262 u32 wkup_cm_fclken;
263 u32 dss_cm_fclken;
264 u32 cam_cm_fclken;
265 u32 per_cm_fclken;
266 u32 usbhost_cm_fclken;
267 u32 core_cm_iclken1;
268 u32 core_cm_iclken2;
269 u32 core_cm_iclken3;
270 u32 sgx_cm_iclken;
271 u32 wkup_cm_iclken;
272 u32 dss_cm_iclken;
273 u32 cam_cm_iclken;
274 u32 per_cm_iclken;
275 u32 usbhost_cm_iclken;
276 u32 iva2_cm_autoidle2;
277 u32 mpu_cm_autoidle2;
278 u32 iva2_cm_clkstctrl;
279 u32 mpu_cm_clkstctrl;
280 u32 core_cm_clkstctrl;
281 u32 sgx_cm_clkstctrl;
282 u32 dss_cm_clkstctrl;
283 u32 cam_cm_clkstctrl;
284 u32 per_cm_clkstctrl;
285 u32 neon_cm_clkstctrl;
286 u32 usbhost_cm_clkstctrl;
287 u32 core_cm_autoidle1;
288 u32 core_cm_autoidle2;
289 u32 core_cm_autoidle3;
290 u32 wkup_cm_autoidle;
291 u32 dss_cm_autoidle;
292 u32 cam_cm_autoidle;
293 u32 per_cm_autoidle;
294 u32 usbhost_cm_autoidle;
295 u32 sgx_cm_sleepdep;
296 u32 dss_cm_sleepdep;
297 u32 cam_cm_sleepdep;
298 u32 per_cm_sleepdep;
299 u32 usbhost_cm_sleepdep;
300 u32 cm_clkout_ctrl;
301};
302
303static struct omap3_cm_regs cm_context;
304
305void omap3_cm_save_context(void)
306{
307 cm_context.iva2_cm_clksel1 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]308 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]309 cm_context.iva2_cm_clksel2 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]310 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]311 cm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
312 cm_context.sgx_cm_clksel =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]313 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]314 cm_context.dss_cm_clksel =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]315 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]316 cm_context.cam_cm_clksel =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]317 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]318 cm_context.per_cm_clksel =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]319 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]320 cm_context.emu_cm_clksel =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]321 omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]322 cm_context.emu_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]323 omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
Eduardo Valentina8ae6452011-04-13 18:21:07 +0300[diff] [blame]324 /*
325 * As per erratum i671, ROM code does not respect the PER DPLL
326 * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
327 * In this case, even though this register has been saved in
328 * scratchpad contents, we need to restore AUTO_PERIPH_DPLL
329 * by ourselves. So, we need to save it anyway.
330 */
331 cm_context.pll_cm_autoidle =
332 omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]333 cm_context.pll_cm_autoidle2 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]334 omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]335 cm_context.pll_cm_clksel4 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]336 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]337 cm_context.pll_cm_clksel5 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]338 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]339 cm_context.pll_cm_clken2 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]340 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]341 cm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
342 cm_context.iva2_cm_fclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]343 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
344 cm_context.iva2_cm_clken_pll =
345 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]346 cm_context.core_cm_fclken1 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]347 omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]348 cm_context.core_cm_fclken3 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]349 omap2_cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]350 cm_context.sgx_cm_fclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]351 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]352 cm_context.wkup_cm_fclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]353 omap2_cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]354 cm_context.dss_cm_fclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]355 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]356 cm_context.cam_cm_fclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]357 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]358 cm_context.per_cm_fclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]359 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]360 cm_context.usbhost_cm_fclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]361 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]362 cm_context.core_cm_iclken1 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]363 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]364 cm_context.core_cm_iclken2 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]365 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]366 cm_context.core_cm_iclken3 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]367 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]368 cm_context.sgx_cm_iclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]369 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]370 cm_context.wkup_cm_iclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]371 omap2_cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]372 cm_context.dss_cm_iclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]373 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]374 cm_context.cam_cm_iclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]375 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]376 cm_context.per_cm_iclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]377 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]378 cm_context.usbhost_cm_iclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]379 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]380 cm_context.iva2_cm_autoidle2 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]381 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]382 cm_context.mpu_cm_autoidle2 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]383 omap2_cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]384 cm_context.iva2_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]385 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]386 cm_context.mpu_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]387 omap2_cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]388 cm_context.core_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]389 omap2_cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]390 cm_context.sgx_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]391 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]392 cm_context.dss_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]393 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]394 cm_context.cam_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]395 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]396 cm_context.per_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]397 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]398 cm_context.neon_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]399 omap2_cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]400 cm_context.usbhost_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]401 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
402 OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]403 cm_context.core_cm_autoidle1 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]404 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]405 cm_context.core_cm_autoidle2 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]406 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]407 cm_context.core_cm_autoidle3 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]408 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]409 cm_context.wkup_cm_autoidle =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]410 omap2_cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]411 cm_context.dss_cm_autoidle =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]412 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]413 cm_context.cam_cm_autoidle =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]414 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]415 cm_context.per_cm_autoidle =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]416 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]417 cm_context.usbhost_cm_autoidle =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]418 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]419 cm_context.sgx_cm_sleepdep =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]420 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
421 OMAP3430_CM_SLEEPDEP);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]422 cm_context.dss_cm_sleepdep =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]423 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]424 cm_context.cam_cm_sleepdep =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]425 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]426 cm_context.per_cm_sleepdep =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]427 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]428 cm_context.usbhost_cm_sleepdep =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]429 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
430 OMAP3430_CM_SLEEPDEP);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]431 cm_context.cm_clkout_ctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]432 omap2_cm_read_mod_reg(OMAP3430_CCR_MOD,
433 OMAP3_CM_CLKOUT_CTRL_OFFSET);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]434}
435
436void omap3_cm_restore_context(void)
437{
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]438 omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
439 CM_CLKSEL1);
440 omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
441 CM_CLKSEL2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]442 __raw_writel(cm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]443 omap2_cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
444 CM_CLKSEL);
445 omap2_cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
446 CM_CLKSEL);
447 omap2_cm_write_mod_reg(cm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
448 CM_CLKSEL);
449 omap2_cm_write_mod_reg(cm_context.per_cm_clksel, OMAP3430_PER_MOD,
450 CM_CLKSEL);
451 omap2_cm_write_mod_reg(cm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
452 CM_CLKSEL1);
453 omap2_cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
454 OMAP2_CM_CLKSTCTRL);
Eduardo Valentina8ae6452011-04-13 18:21:07 +0300[diff] [blame]455 /*
456 * As per erratum i671, ROM code does not respect the PER DPLL
457 * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
458 * In this case, we need to restore AUTO_PERIPH_DPLL by ourselves.
459 */
460 omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle, PLL_MOD,
461 CM_AUTOIDLE);
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]462 omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD,
463 CM_AUTOIDLE2);
464 omap2_cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD,
465 OMAP3430ES2_CM_CLKSEL4);
466 omap2_cm_write_mod_reg(cm_context.pll_cm_clksel5, PLL_MOD,
467 OMAP3430ES2_CM_CLKSEL5);
468 omap2_cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD,
469 OMAP3430ES2_CM_CLKEN2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]470 __raw_writel(cm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]471 omap2_cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
472 CM_FCLKEN);
473 omap2_cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
474 OMAP3430_CM_CLKEN_PLL);
475 omap2_cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD,
476 CM_FCLKEN1);
477 omap2_cm_write_mod_reg(cm_context.core_cm_fclken3, CORE_MOD,
478 OMAP3430ES2_CM_FCLKEN3);
479 omap2_cm_write_mod_reg(cm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
480 CM_FCLKEN);
481 omap2_cm_write_mod_reg(cm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
482 omap2_cm_write_mod_reg(cm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
483 CM_FCLKEN);
484 omap2_cm_write_mod_reg(cm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
485 CM_FCLKEN);
486 omap2_cm_write_mod_reg(cm_context.per_cm_fclken, OMAP3430_PER_MOD,
487 CM_FCLKEN);
488 omap2_cm_write_mod_reg(cm_context.usbhost_cm_fclken,
489 OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
490 omap2_cm_write_mod_reg(cm_context.core_cm_iclken1, CORE_MOD,
491 CM_ICLKEN1);
492 omap2_cm_write_mod_reg(cm_context.core_cm_iclken2, CORE_MOD,
493 CM_ICLKEN2);
494 omap2_cm_write_mod_reg(cm_context.core_cm_iclken3, CORE_MOD,
495 CM_ICLKEN3);
496 omap2_cm_write_mod_reg(cm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
497 CM_ICLKEN);
498 omap2_cm_write_mod_reg(cm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
499 omap2_cm_write_mod_reg(cm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
500 CM_ICLKEN);
501 omap2_cm_write_mod_reg(cm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
502 CM_ICLKEN);
503 omap2_cm_write_mod_reg(cm_context.per_cm_iclken, OMAP3430_PER_MOD,
504 CM_ICLKEN);
505 omap2_cm_write_mod_reg(cm_context.usbhost_cm_iclken,
506 OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
507 omap2_cm_write_mod_reg(cm_context.iva2_cm_autoidle2, OMAP3430_IVA2_MOD,
508 CM_AUTOIDLE2);
509 omap2_cm_write_mod_reg(cm_context.mpu_cm_autoidle2, MPU_MOD,
510 CM_AUTOIDLE2);
511 omap2_cm_write_mod_reg(cm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
512 OMAP2_CM_CLKSTCTRL);
513 omap2_cm_write_mod_reg(cm_context.mpu_cm_clkstctrl, MPU_MOD,
514 OMAP2_CM_CLKSTCTRL);
515 omap2_cm_write_mod_reg(cm_context.core_cm_clkstctrl, CORE_MOD,
516 OMAP2_CM_CLKSTCTRL);
517 omap2_cm_write_mod_reg(cm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
518 OMAP2_CM_CLKSTCTRL);
519 omap2_cm_write_mod_reg(cm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
520 OMAP2_CM_CLKSTCTRL);
521 omap2_cm_write_mod_reg(cm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
522 OMAP2_CM_CLKSTCTRL);
523 omap2_cm_write_mod_reg(cm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
524 OMAP2_CM_CLKSTCTRL);
525 omap2_cm_write_mod_reg(cm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
526 OMAP2_CM_CLKSTCTRL);
527 omap2_cm_write_mod_reg(cm_context.usbhost_cm_clkstctrl,
528 OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);
529 omap2_cm_write_mod_reg(cm_context.core_cm_autoidle1, CORE_MOD,
530 CM_AUTOIDLE1);
531 omap2_cm_write_mod_reg(cm_context.core_cm_autoidle2, CORE_MOD,
532 CM_AUTOIDLE2);
533 omap2_cm_write_mod_reg(cm_context.core_cm_autoidle3, CORE_MOD,
534 CM_AUTOIDLE3);
535 omap2_cm_write_mod_reg(cm_context.wkup_cm_autoidle, WKUP_MOD,
536 CM_AUTOIDLE);
537 omap2_cm_write_mod_reg(cm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
538 CM_AUTOIDLE);
539 omap2_cm_write_mod_reg(cm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
540 CM_AUTOIDLE);
541 omap2_cm_write_mod_reg(cm_context.per_cm_autoidle, OMAP3430_PER_MOD,
542 CM_AUTOIDLE);
543 omap2_cm_write_mod_reg(cm_context.usbhost_cm_autoidle,
544 OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
545 omap2_cm_write_mod_reg(cm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
546 OMAP3430_CM_SLEEPDEP);
547 omap2_cm_write_mod_reg(cm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
548 OMAP3430_CM_SLEEPDEP);
549 omap2_cm_write_mod_reg(cm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
550 OMAP3430_CM_SLEEPDEP);
551 omap2_cm_write_mod_reg(cm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
552 OMAP3430_CM_SLEEPDEP);
553 omap2_cm_write_mod_reg(cm_context.usbhost_cm_sleepdep,
554 OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
555 omap2_cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
556 OMAP3_CM_CLKOUT_CTRL_OFFSET);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]557}
558#endif