blob: c3540e033e8dc9c1cfc68054b8ab14a7435e25c6 [file] [log] [blame]
Thierry Reding307e28e2012-09-20 17:06:06 +02001/include/ "tegra20.dtsi"
2
3/ {
4 model = "Avionic Design Tamonten SOM";
5 compatible = "ad,tamonten", "nvidia,tegra20";
6
7 memory {
8 reg = <0x00000000 0x20000000>;
9 };
10
11 pinmux {
12 pinctrl-names = "default";
13 pinctrl-0 = <&state_default>;
14
15 state_default: pinmux {
16 ata {
17 nvidia,pins = "ata";
18 nvidia,function = "ide";
19 };
20 atb {
21 nvidia,pins = "atb", "gma", "gme";
22 nvidia,function = "sdio4";
23 };
24 atc {
25 nvidia,pins = "atc";
26 nvidia,function = "nand";
27 };
28 atd {
29 nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
30 "spia", "spib", "spic";
31 nvidia,function = "gmi";
32 };
33 cdev1 {
34 nvidia,pins = "cdev1";
35 nvidia,function = "plla_out";
36 };
37 cdev2 {
38 nvidia,pins = "cdev2";
39 nvidia,function = "pllp_out4";
40 };
41 crtp {
42 nvidia,pins = "crtp";
43 nvidia,function = "crt";
44 };
45 csus {
46 nvidia,pins = "csus";
47 nvidia,function = "vi_sensor_clk";
48 };
49 dap1 {
50 nvidia,pins = "dap1";
51 nvidia,function = "dap1";
52 };
53 dap2 {
54 nvidia,pins = "dap2";
55 nvidia,function = "dap2";
56 };
57 dap3 {
58 nvidia,pins = "dap3";
59 nvidia,function = "dap3";
60 };
61 dap4 {
62 nvidia,pins = "dap4";
63 nvidia,function = "dap4";
64 };
Thierry Reding307e28e2012-09-20 17:06:06 +020065 dta {
66 nvidia,pins = "dta", "dtd";
67 nvidia,function = "sdio2";
68 };
69 dtb {
70 nvidia,pins = "dtb", "dtc", "dte";
71 nvidia,function = "rsvd1";
72 };
73 dtf {
74 nvidia,pins = "dtf";
75 nvidia,function = "i2c3";
76 };
77 gmc {
78 nvidia,pins = "gmc";
79 nvidia,function = "uartd";
80 };
81 gpu7 {
82 nvidia,pins = "gpu7";
83 nvidia,function = "rtck";
84 };
85 gpv {
86 nvidia,pins = "gpv", "slxa", "slxk";
87 nvidia,function = "pcie";
88 };
89 hdint {
Thierry Redingec319902012-11-09 14:04:50 +010090 nvidia,pins = "hdint";
Thierry Reding307e28e2012-09-20 17:06:06 +020091 nvidia,function = "hdmi";
92 };
93 i2cp {
94 nvidia,pins = "i2cp";
95 nvidia,function = "i2cp";
96 };
97 irrx {
98 nvidia,pins = "irrx", "irtx";
99 nvidia,function = "uarta";
100 };
101 kbca {
102 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
103 "kbce", "kbcf";
104 nvidia,function = "kbc";
105 };
106 lcsn {
107 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
108 "ld3", "ld4", "ld5", "ld6", "ld7",
109 "ld8", "ld9", "ld10", "ld11", "ld12",
110 "ld13", "ld14", "ld15", "ld16", "ld17",
111 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
112 "lhs", "lm0", "lm1", "lpp", "lpw0",
113 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
114 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
115 "lvs";
116 nvidia,function = "displaya";
117 };
118 owc {
119 nvidia,pins = "owc", "spdi", "spdo", "uac";
120 nvidia,function = "rsvd2";
121 };
122 pmc {
123 nvidia,pins = "pmc";
124 nvidia,function = "pwr_on";
125 };
126 rm {
127 nvidia,pins = "rm";
128 nvidia,function = "i2c1";
129 };
130 sdb {
131 nvidia,pins = "sdb", "sdc", "sdd";
132 nvidia,function = "pwm";
133 };
134 sdio1 {
135 nvidia,pins = "sdio1";
136 nvidia,function = "sdio1";
137 };
138 slxc {
139 nvidia,pins = "slxc", "slxd";
140 nvidia,function = "spdif";
141 };
142 spid {
143 nvidia,pins = "spid", "spie", "spif";
144 nvidia,function = "spi1";
145 };
146 spig {
147 nvidia,pins = "spig", "spih";
148 nvidia,function = "spi2_alt";
149 };
150 uaa {
151 nvidia,pins = "uaa", "uab", "uda";
152 nvidia,function = "ulpi";
153 };
154 uad {
155 nvidia,pins = "uad";
156 nvidia,function = "irda";
157 };
158 uca {
159 nvidia,pins = "uca", "ucb";
160 nvidia,function = "uartc";
161 };
162 conf_ata {
163 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
164 "cdev1", "cdev2", "dap1", "dtb", "gma",
165 "gmb", "gmc", "gmd", "gme", "gpu7",
166 "gpv", "i2cp", "pta", "rm", "slxa",
167 "slxk", "spia", "spib", "uac";
168 nvidia,pull = <0>;
169 nvidia,tristate = <0>;
170 };
171 conf_ck32 {
172 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
173 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
174 nvidia,pull = <0>;
175 };
176 conf_csus {
177 nvidia,pins = "csus", "spid", "spif";
178 nvidia,pull = <1>;
179 nvidia,tristate = <1>;
180 };
181 conf_crtp {
182 nvidia,pins = "crtp", "dap2", "dap3", "dap4",
183 "dtc", "dte", "dtf", "gpu", "sdio1",
184 "slxc", "slxd", "spdi", "spdo", "spig",
185 "uda";
186 nvidia,pull = <0>;
187 nvidia,tristate = <1>;
188 };
189 conf_ddc {
190 nvidia,pins = "ddc", "dta", "dtd", "kbca",
191 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
192 "sdc";
193 nvidia,pull = <2>;
194 nvidia,tristate = <0>;
195 };
196 conf_hdint {
197 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
198 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
199 "lvp0", "owc", "sdb";
200 nvidia,tristate = <1>;
201 };
202 conf_irrx {
203 nvidia,pins = "irrx", "irtx", "sdd", "spic",
204 "spie", "spih", "uaa", "uab", "uad",
205 "uca", "ucb";
206 nvidia,pull = <2>;
207 nvidia,tristate = <1>;
208 };
209 conf_lc {
210 nvidia,pins = "lc", "ls";
211 nvidia,pull = <2>;
212 };
213 conf_ld0 {
214 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
215 "ld5", "ld6", "ld7", "ld8", "ld9",
216 "ld10", "ld11", "ld12", "ld13", "ld14",
217 "ld15", "ld16", "ld17", "ldi", "lhp0",
218 "lhp1", "lhp2", "lhs", "lm0", "lpp",
219 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
220 "lvs", "pmc";
221 nvidia,tristate = <0>;
222 };
223 conf_ld17_0 {
224 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
225 "ld23_22";
226 nvidia,pull = <1>;
227 };
228 };
Thierry Redingec319902012-11-09 14:04:50 +0100229
230 state_i2cmux_ddc: pinmux_i2cmux_ddc {
231 ddc {
232 nvidia,pins = "ddc";
233 nvidia,function = "i2c2";
234 };
235 pta {
236 nvidia,pins = "pta";
237 nvidia,function = "rsvd4";
238 };
239 };
240
241 state_i2cmux_pta: pinmux_i2cmux_pta {
242 ddc {
243 nvidia,pins = "ddc";
244 nvidia,function = "rsvd4";
245 };
246 pta {
247 nvidia,pins = "pta";
248 nvidia,function = "i2c2";
249 };
250 };
251
252 state_i2cmux_idle: pinmux_i2cmux_idle {
253 ddc {
254 nvidia,pins = "ddc";
255 nvidia,function = "rsvd4";
256 };
257 pta {
258 nvidia,pins = "pta";
259 nvidia,function = "rsvd4";
260 };
261 };
Thierry Reding307e28e2012-09-20 17:06:06 +0200262 };
263
264 i2s@70002800 {
265 status = "okay";
266 };
267
268 serial@70006300 {
269 clock-frequency = <216000000>;
270 status = "okay";
271 };
272
273 i2c@7000c000 {
274 clock-frequency = <400000>;
275 status = "okay";
276 };
277
Thierry Redingec319902012-11-09 14:04:50 +0100278 i2c@7000c400 {
279 clock-frequency = <100000>;
280 status = "okay";
281 };
282
283 i2cmux {
284 compatible = "i2c-mux-pinctrl";
285 #address-cells = <1>;
286 #size-cells = <0>;
287
288 i2c-parent = <&{/i2c@7000c400}>;
289
290 pinctrl-names = "ddc", "pta", "idle";
291 pinctrl-0 = <&state_i2cmux_ddc>;
292 pinctrl-1 = <&state_i2cmux_pta>;
293 pinctrl-2 = <&state_i2cmux_idle>;
294
295 i2c@0 {
296 reg = <0>;
297 #address-cells = <1>;
298 #size-cells = <0>;
299 };
300
301 i2c@1 {
302 reg = <1>;
303 #address-cells = <1>;
304 #size-cells = <0>;
305 };
306 };
307
Thierry Reding307e28e2012-09-20 17:06:06 +0200308 i2c@7000d000 {
309 clock-frequency = <400000>;
310 status = "okay";
311
312 pmic: tps6586x@34 {
313 compatible = "ti,tps6586x";
314 reg = <0x34>;
315 interrupts = <0 86 0x4>;
316
317 ti,system-power-controller;
318
319 #gpio-cells = <2>;
320 gpio-controller;
321
322 sys-supply = <&vdd_5v0_reg>;
323 vin-sm0-supply = <&sys_reg>;
324 vin-sm1-supply = <&sys_reg>;
325 vin-sm2-supply = <&sys_reg>;
326 vinldo01-supply = <&sm2_reg>;
327 vinldo23-supply = <&sm2_reg>;
328 vinldo4-supply = <&sm2_reg>;
329 vinldo678-supply = <&sm2_reg>;
330 vinldo9-supply = <&sm2_reg>;
331
332 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600333 sys_reg: sys {
Thierry Reding307e28e2012-09-20 17:06:06 +0200334 regulator-name = "vdd_sys";
335 regulator-always-on;
336 };
337
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600338 sm0 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200339 regulator-name = "vdd_sys_sm0,vdd_core";
340 regulator-min-microvolt = <1200000>;
341 regulator-max-microvolt = <1200000>;
342 regulator-always-on;
343 };
344
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600345 sm1 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200346 regulator-name = "vdd_sys_sm1,vdd_cpu";
347 regulator-min-microvolt = <1000000>;
348 regulator-max-microvolt = <1000000>;
349 regulator-always-on;
350 };
351
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600352 sm2_reg: sm2 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200353 regulator-name = "vdd_sys_sm2,vin_ldo*";
354 regulator-min-microvolt = <3700000>;
355 regulator-max-microvolt = <3700000>;
356 regulator-always-on;
357 };
358
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600359 ldo0 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200360 regulator-name = "vdd_ldo0,vddio_pex_clk";
361 regulator-min-microvolt = <3300000>;
362 regulator-max-microvolt = <3300000>;
363 };
364
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600365 ldo1 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200366 regulator-name = "vdd_ldo1,avdd_pll*";
367 regulator-min-microvolt = <1100000>;
368 regulator-max-microvolt = <1100000>;
369 regulator-always-on;
370 };
371
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600372 ldo2 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200373 regulator-name = "vdd_ldo2,vdd_rtc";
374 regulator-min-microvolt = <1200000>;
375 regulator-max-microvolt = <1200000>;
376 };
377
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600378 ldo3 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200379 regulator-name = "vdd_ldo3,avdd_usb*";
380 regulator-min-microvolt = <3300000>;
381 regulator-max-microvolt = <3300000>;
382 regulator-always-on;
383 };
384
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600385 ldo4 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200386 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
387 regulator-min-microvolt = <1800000>;
388 regulator-max-microvolt = <1800000>;
389 regulator-always-on;
390 };
391
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600392 ldo5 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200393 regulator-name = "vdd_ldo5,vcore_mmc";
394 regulator-min-microvolt = <2850000>;
395 regulator-max-microvolt = <2850000>;
396 };
397
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600398 ldo6 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200399 regulator-name = "vdd_ldo6,avdd_vdac";
400 /*
401 * According to the Tegra 2 Automotive
402 * DataSheet, a typical value for this
403 * would be 2.8V, but the PMIC only
404 * supports 2.85V.
405 */
406 regulator-min-microvolt = <2850000>;
407 regulator-max-microvolt = <2850000>;
408 };
409
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600410 ldo7 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200411 regulator-name = "vdd_ldo7,avdd_hdmi";
412 regulator-min-microvolt = <3300000>;
413 regulator-max-microvolt = <3300000>;
414 };
415
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600416 ldo8 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200417 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
418 regulator-min-microvolt = <1800000>;
419 regulator-max-microvolt = <1800000>;
420 };
421
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600422 ldo9 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200423 regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
424 /*
425 * According to the Tegra 2 Automotive
426 * DataSheet, a typical value for this
427 * would be 2.8V, but the PMIC only
428 * supports 2.85V.
429 */
430 regulator-min-microvolt = <2850000>;
431 regulator-max-microvolt = <2850000>;
432 regulator-always-on;
433 };
434
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600435 ldo_rtc {
Thierry Reding307e28e2012-09-20 17:06:06 +0200436 regulator-name = "vdd_rtc_out";
437 regulator-min-microvolt = <3300000>;
438 regulator-max-microvolt = <3300000>;
439 regulator-always-on;
440 };
441 };
442 };
443 };
444
445 pmc {
446 nvidia,invert-interrupt;
447 };
448
449 usb@c5008000 {
450 status = "okay";
451 };
452
453 sdhci@c8000600 {
454 cd-gpios = <&gpio 58 0>; /* gpio PH2 */
455 wp-gpios = <&gpio 59 0>; /* gpio PH3 */
456 bus-width = <4>;
457 status = "okay";
458 };
459
460 regulators {
461 compatible = "simple-bus";
462
463 #address-cells = <1>;
464 #size-cells = <0>;
465
466 vdd_5v0_reg: regulator@0 {
467 compatible = "regulator-fixed";
468 reg = <0>;
469 regulator-name = "vdd_5v0";
470 regulator-min-microvolt = <5000000>;
471 regulator-max-microvolt = <5000000>;
472 regulator-always-on;
473 };
474 };
475};