Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 1 | /* |
| 2 | * SH RSPI driver |
| 3 | * |
| 4 | * Copyright (C) 2012 Renesas Solutions Corp. |
| 5 | * |
| 6 | * Based on spi-sh.c: |
| 7 | * Copyright (C) 2011 Renesas Solutions Corp. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; version 2 of the License. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 21 | * |
| 22 | */ |
| 23 | |
| 24 | #include <linux/module.h> |
| 25 | #include <linux/kernel.h> |
| 26 | #include <linux/sched.h> |
| 27 | #include <linux/errno.h> |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 28 | #include <linux/interrupt.h> |
| 29 | #include <linux/platform_device.h> |
| 30 | #include <linux/io.h> |
| 31 | #include <linux/clk.h> |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 32 | #include <linux/dmaengine.h> |
| 33 | #include <linux/dma-mapping.h> |
| 34 | #include <linux/sh_dma.h> |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 35 | #include <linux/spi/spi.h> |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 36 | #include <linux/spi/rspi.h> |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 37 | |
Geert Uytterhoeven | 6ab4865 | 2014-01-12 11:27:37 +0100 | [diff] [blame] | 38 | #define RSPI_SPCR 0x00 /* Control Register */ |
| 39 | #define RSPI_SSLP 0x01 /* Slave Select Polarity Register */ |
| 40 | #define RSPI_SPPCR 0x02 /* Pin Control Register */ |
| 41 | #define RSPI_SPSR 0x03 /* Status Register */ |
| 42 | #define RSPI_SPDR 0x04 /* Data Register */ |
| 43 | #define RSPI_SPSCR 0x08 /* Sequence Control Register */ |
| 44 | #define RSPI_SPSSR 0x09 /* Sequence Status Register */ |
| 45 | #define RSPI_SPBR 0x0a /* Bit Rate Register */ |
| 46 | #define RSPI_SPDCR 0x0b /* Data Control Register */ |
| 47 | #define RSPI_SPCKD 0x0c /* Clock Delay Register */ |
| 48 | #define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */ |
| 49 | #define RSPI_SPND 0x0e /* Next-Access Delay Register */ |
| 50 | #define RSPI_SPCR2 0x0f /* Control Register 2 */ |
| 51 | #define RSPI_SPCMD0 0x10 /* Command Register 0 */ |
| 52 | #define RSPI_SPCMD1 0x12 /* Command Register 1 */ |
| 53 | #define RSPI_SPCMD2 0x14 /* Command Register 2 */ |
| 54 | #define RSPI_SPCMD3 0x16 /* Command Register 3 */ |
| 55 | #define RSPI_SPCMD4 0x18 /* Command Register 4 */ |
| 56 | #define RSPI_SPCMD5 0x1a /* Command Register 5 */ |
| 57 | #define RSPI_SPCMD6 0x1c /* Command Register 6 */ |
| 58 | #define RSPI_SPCMD7 0x1e /* Command Register 7 */ |
| 59 | #define RSPI_SPBFCR 0x20 /* Buffer Control Register */ |
| 60 | #define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */ |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 61 | |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 62 | /*qspi only */ |
Geert Uytterhoeven | fbe5072 | 2014-01-12 11:27:38 +0100 | [diff] [blame] | 63 | #define QSPI_SPBFCR 0x18 /* Buffer Control Register */ |
| 64 | #define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */ |
| 65 | #define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */ |
| 66 | #define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */ |
| 67 | #define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */ |
| 68 | #define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */ |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 69 | |
Geert Uytterhoeven | 6ab4865 | 2014-01-12 11:27:37 +0100 | [diff] [blame] | 70 | /* SPCR - Control Register */ |
| 71 | #define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */ |
| 72 | #define SPCR_SPE 0x40 /* Function Enable */ |
| 73 | #define SPCR_SPTIE 0x20 /* Transmit Interrupt Enable */ |
| 74 | #define SPCR_SPEIE 0x10 /* Error Interrupt Enable */ |
| 75 | #define SPCR_MSTR 0x08 /* Master/Slave Mode Select */ |
| 76 | #define SPCR_MODFEN 0x04 /* Mode Fault Error Detection Enable */ |
| 77 | /* RSPI on SH only */ |
| 78 | #define SPCR_TXMD 0x02 /* TX Only Mode (vs. Full Duplex) */ |
| 79 | #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */ |
Geert Uytterhoeven | fbe5072 | 2014-01-12 11:27:38 +0100 | [diff] [blame] | 80 | /* QSPI on R-Car M2 only */ |
| 81 | #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */ |
| 82 | #define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */ |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 83 | |
Geert Uytterhoeven | 6ab4865 | 2014-01-12 11:27:37 +0100 | [diff] [blame] | 84 | /* SSLP - Slave Select Polarity Register */ |
| 85 | #define SSLP_SSL1P 0x02 /* SSL1 Signal Polarity Setting */ |
| 86 | #define SSLP_SSL0P 0x01 /* SSL0 Signal Polarity Setting */ |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 87 | |
Geert Uytterhoeven | 6ab4865 | 2014-01-12 11:27:37 +0100 | [diff] [blame] | 88 | /* SPPCR - Pin Control Register */ |
| 89 | #define SPPCR_MOIFE 0x20 /* MOSI Idle Value Fixing Enable */ |
| 90 | #define SPPCR_MOIFV 0x10 /* MOSI Idle Fixed Value */ |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 91 | #define SPPCR_SPOM 0x04 |
Geert Uytterhoeven | 6ab4865 | 2014-01-12 11:27:37 +0100 | [diff] [blame] | 92 | #define SPPCR_SPLP2 0x02 /* Loopback Mode 2 (non-inverting) */ |
| 93 | #define SPPCR_SPLP 0x01 /* Loopback Mode (inverting) */ |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 94 | |
Geert Uytterhoeven | fbe5072 | 2014-01-12 11:27:38 +0100 | [diff] [blame] | 95 | #define SPPCR_IO3FV 0x04 /* Single-/Dual-SPI Mode IO3 Output Fixed Value */ |
| 96 | #define SPPCR_IO2FV 0x04 /* Single-/Dual-SPI Mode IO2 Output Fixed Value */ |
| 97 | |
Geert Uytterhoeven | 6ab4865 | 2014-01-12 11:27:37 +0100 | [diff] [blame] | 98 | /* SPSR - Status Register */ |
| 99 | #define SPSR_SPRF 0x80 /* Receive Buffer Full Flag */ |
| 100 | #define SPSR_TEND 0x40 /* Transmit End */ |
| 101 | #define SPSR_SPTEF 0x20 /* Transmit Buffer Empty Flag */ |
| 102 | #define SPSR_PERF 0x08 /* Parity Error Flag */ |
| 103 | #define SPSR_MODF 0x04 /* Mode Fault Error Flag */ |
| 104 | #define SPSR_IDLNF 0x02 /* RSPI Idle Flag */ |
| 105 | #define SPSR_OVRF 0x01 /* Overrun Error Flag */ |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 106 | |
Geert Uytterhoeven | 6ab4865 | 2014-01-12 11:27:37 +0100 | [diff] [blame] | 107 | /* SPSCR - Sequence Control Register */ |
| 108 | #define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */ |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 109 | |
Geert Uytterhoeven | 6ab4865 | 2014-01-12 11:27:37 +0100 | [diff] [blame] | 110 | /* SPSSR - Sequence Status Register */ |
| 111 | #define SPSSR_SPECM_MASK 0x70 /* Command Error Mask */ |
| 112 | #define SPSSR_SPCP_MASK 0x07 /* Command Pointer Mask */ |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 113 | |
Geert Uytterhoeven | 6ab4865 | 2014-01-12 11:27:37 +0100 | [diff] [blame] | 114 | /* SPDCR - Data Control Register */ |
| 115 | #define SPDCR_TXDMY 0x80 /* Dummy Data Transmission Enable */ |
| 116 | #define SPDCR_SPLW1 0x40 /* Access Width Specification (RZ) */ |
| 117 | #define SPDCR_SPLW0 0x20 /* Access Width Specification (RZ) */ |
| 118 | #define SPDCR_SPLLWORD (SPDCR_SPLW1 | SPDCR_SPLW0) |
| 119 | #define SPDCR_SPLWORD SPDCR_SPLW1 |
| 120 | #define SPDCR_SPLBYTE SPDCR_SPLW0 |
| 121 | #define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */ |
| 122 | #define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select */ |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 123 | #define SPDCR_SLSEL1 0x08 |
| 124 | #define SPDCR_SLSEL0 0x04 |
Geert Uytterhoeven | 6ab4865 | 2014-01-12 11:27:37 +0100 | [diff] [blame] | 125 | #define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select */ |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 126 | #define SPDCR_SPFC1 0x02 |
| 127 | #define SPDCR_SPFC0 0x01 |
Geert Uytterhoeven | 6ab4865 | 2014-01-12 11:27:37 +0100 | [diff] [blame] | 128 | #define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) */ |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 129 | |
Geert Uytterhoeven | 6ab4865 | 2014-01-12 11:27:37 +0100 | [diff] [blame] | 130 | /* SPCKD - Clock Delay Register */ |
| 131 | #define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */ |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 132 | |
Geert Uytterhoeven | 6ab4865 | 2014-01-12 11:27:37 +0100 | [diff] [blame] | 133 | /* SSLND - Slave Select Negation Delay Register */ |
| 134 | #define SSLND_SLNDL_MASK 0x07 /* SSL Negation Delay Setting (1-8) */ |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 135 | |
Geert Uytterhoeven | 6ab4865 | 2014-01-12 11:27:37 +0100 | [diff] [blame] | 136 | /* SPND - Next-Access Delay Register */ |
| 137 | #define SPND_SPNDL_MASK 0x07 /* Next-Access Delay Setting (1-8) */ |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 138 | |
Geert Uytterhoeven | 6ab4865 | 2014-01-12 11:27:37 +0100 | [diff] [blame] | 139 | /* SPCR2 - Control Register 2 */ |
| 140 | #define SPCR2_PTE 0x08 /* Parity Self-Test Enable */ |
| 141 | #define SPCR2_SPIE 0x04 /* Idle Interrupt Enable */ |
| 142 | #define SPCR2_SPOE 0x02 /* Odd Parity Enable (vs. Even) */ |
| 143 | #define SPCR2_SPPE 0x01 /* Parity Enable */ |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 144 | |
Geert Uytterhoeven | 6ab4865 | 2014-01-12 11:27:37 +0100 | [diff] [blame] | 145 | /* SPCMDn - Command Registers */ |
| 146 | #define SPCMD_SCKDEN 0x8000 /* Clock Delay Setting Enable */ |
| 147 | #define SPCMD_SLNDEN 0x4000 /* SSL Negation Delay Setting Enable */ |
| 148 | #define SPCMD_SPNDEN 0x2000 /* Next-Access Delay Enable */ |
| 149 | #define SPCMD_LSBF 0x1000 /* LSB First */ |
| 150 | #define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */ |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 151 | #define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK) |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 152 | #define SPCMD_SPB_8BIT 0x0000 /* qspi only */ |
| 153 | #define SPCMD_SPB_16BIT 0x0100 |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 154 | #define SPCMD_SPB_20BIT 0x0000 |
| 155 | #define SPCMD_SPB_24BIT 0x0100 |
| 156 | #define SPCMD_SPB_32BIT 0x0200 |
Geert Uytterhoeven | 6ab4865 | 2014-01-12 11:27:37 +0100 | [diff] [blame] | 157 | #define SPCMD_SSLKP 0x0080 /* SSL Signal Level Keeping */ |
Geert Uytterhoeven | fbe5072 | 2014-01-12 11:27:38 +0100 | [diff] [blame] | 158 | #define SPCMD_SPIMOD_MASK 0x0060 /* SPI Operating Mode (QSPI only) */ |
| 159 | #define SPCMD_SPIMOD1 0x0040 |
| 160 | #define SPCMD_SPIMOD0 0x0020 |
| 161 | #define SPCMD_SPIMOD_SINGLE 0 |
| 162 | #define SPCMD_SPIMOD_DUAL SPCMD_SPIMOD0 |
| 163 | #define SPCMD_SPIMOD_QUAD SPCMD_SPIMOD1 |
| 164 | #define SPCMD_SPRW 0x0010 /* SPI Read/Write Access (Dual/Quad) */ |
Geert Uytterhoeven | 6ab4865 | 2014-01-12 11:27:37 +0100 | [diff] [blame] | 165 | #define SPCMD_SSLA_MASK 0x0030 /* SSL Assert Signal Setting (RSPI) */ |
| 166 | #define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */ |
| 167 | #define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */ |
| 168 | #define SPCMD_CPHA 0x0001 /* Clock Phase Setting */ |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 169 | |
Geert Uytterhoeven | 6ab4865 | 2014-01-12 11:27:37 +0100 | [diff] [blame] | 170 | /* SPBFCR - Buffer Control Register */ |
| 171 | #define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset (qspi only) */ |
| 172 | #define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset (qspi only) */ |
| 173 | #define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */ |
| 174 | #define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */ |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 175 | |
Geert Uytterhoeven | 2aae80b | 2013-12-24 10:49:33 +0100 | [diff] [blame] | 176 | #define DUMMY_DATA 0x00 |
| 177 | |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 178 | struct rspi_data { |
| 179 | void __iomem *addr; |
| 180 | u32 max_speed_hz; |
| 181 | struct spi_master *master; |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 182 | wait_queue_head_t wait; |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 183 | struct clk *clk; |
Geert Uytterhoeven | 97b95c1 | 2013-12-24 10:49:34 +0100 | [diff] [blame] | 184 | u8 spsr; |
Geert Uytterhoeven | 348e515 | 2014-01-12 11:27:43 +0100 | [diff] [blame] | 185 | u16 spcmd; |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 186 | const struct spi_ops *ops; |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 187 | |
| 188 | /* for dmaengine */ |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 189 | struct dma_chan *chan_tx; |
| 190 | struct dma_chan *chan_rx; |
| 191 | int irq; |
| 192 | |
| 193 | unsigned dma_width_16bit:1; |
| 194 | unsigned dma_callbacked:1; |
Geert Uytterhoeven | 74da768 | 2014-01-24 09:43:53 +0100 | [diff] [blame] | 195 | unsigned byte_access:1; |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 196 | }; |
| 197 | |
Geert Uytterhoeven | baf588f | 2013-12-24 10:49:32 +0100 | [diff] [blame] | 198 | static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset) |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 199 | { |
| 200 | iowrite8(data, rspi->addr + offset); |
| 201 | } |
| 202 | |
Geert Uytterhoeven | baf588f | 2013-12-24 10:49:32 +0100 | [diff] [blame] | 203 | static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset) |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 204 | { |
| 205 | iowrite16(data, rspi->addr + offset); |
| 206 | } |
| 207 | |
Geert Uytterhoeven | baf588f | 2013-12-24 10:49:32 +0100 | [diff] [blame] | 208 | static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset) |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 209 | { |
| 210 | iowrite32(data, rspi->addr + offset); |
| 211 | } |
| 212 | |
Geert Uytterhoeven | baf588f | 2013-12-24 10:49:32 +0100 | [diff] [blame] | 213 | static u8 rspi_read8(const struct rspi_data *rspi, u16 offset) |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 214 | { |
| 215 | return ioread8(rspi->addr + offset); |
| 216 | } |
| 217 | |
Geert Uytterhoeven | baf588f | 2013-12-24 10:49:32 +0100 | [diff] [blame] | 218 | static u16 rspi_read16(const struct rspi_data *rspi, u16 offset) |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 219 | { |
| 220 | return ioread16(rspi->addr + offset); |
| 221 | } |
| 222 | |
Geert Uytterhoeven | 74da768 | 2014-01-24 09:43:53 +0100 | [diff] [blame] | 223 | static void rspi_write_data(const struct rspi_data *rspi, u16 data) |
| 224 | { |
| 225 | if (rspi->byte_access) |
| 226 | rspi_write8(rspi, data, RSPI_SPDR); |
| 227 | else /* 16 bit */ |
| 228 | rspi_write16(rspi, data, RSPI_SPDR); |
| 229 | } |
| 230 | |
| 231 | static u16 rspi_read_data(const struct rspi_data *rspi) |
| 232 | { |
| 233 | if (rspi->byte_access) |
| 234 | return rspi_read8(rspi, RSPI_SPDR); |
| 235 | else /* 16 bit */ |
| 236 | return rspi_read16(rspi, RSPI_SPDR); |
| 237 | } |
| 238 | |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 239 | /* optional functions */ |
| 240 | struct spi_ops { |
Geert Uytterhoeven | 74da768 | 2014-01-24 09:43:53 +0100 | [diff] [blame] | 241 | int (*set_config_register)(struct rspi_data *rspi, int access_size); |
Geert Uytterhoeven | eb557f7 | 2014-01-24 09:43:55 +0100 | [diff] [blame] | 242 | int (*transfer_one)(struct spi_master *master, struct spi_device *spi, |
| 243 | struct spi_transfer *xfer); |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 244 | }; |
| 245 | |
| 246 | /* |
| 247 | * functions for RSPI |
| 248 | */ |
Geert Uytterhoeven | 74da768 | 2014-01-24 09:43:53 +0100 | [diff] [blame] | 249 | static int rspi_set_config_register(struct rspi_data *rspi, int access_size) |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 250 | { |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 251 | int spbr; |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 252 | |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 253 | /* Sets output mode(CMOS) and MOSI signal(from previous transfer) */ |
| 254 | rspi_write8(rspi, 0x00, RSPI_SPPCR); |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 255 | |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 256 | /* Sets transfer bit rate */ |
| 257 | spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz) - 1; |
| 258 | rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); |
| 259 | |
Geert Uytterhoeven | 74da768 | 2014-01-24 09:43:53 +0100 | [diff] [blame] | 260 | /* Disable dummy transmission, set 16-bit word access, 1 frame */ |
| 261 | rspi_write8(rspi, 0, RSPI_SPDCR); |
| 262 | rspi->byte_access = 0; |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 263 | |
| 264 | /* Sets RSPCK, SSL, next-access delay value */ |
| 265 | rspi_write8(rspi, 0x00, RSPI_SPCKD); |
| 266 | rspi_write8(rspi, 0x00, RSPI_SSLND); |
| 267 | rspi_write8(rspi, 0x00, RSPI_SPND); |
| 268 | |
| 269 | /* Sets parity, interrupt mask */ |
| 270 | rspi_write8(rspi, 0x00, RSPI_SPCR2); |
| 271 | |
| 272 | /* Sets SPCMD */ |
Geert Uytterhoeven | 348e515 | 2014-01-12 11:27:43 +0100 | [diff] [blame] | 273 | rspi_write16(rspi, SPCMD_SPB_8_TO_16(access_size) | rspi->spcmd, |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 274 | RSPI_SPCMD0); |
| 275 | |
| 276 | /* Sets RSPI mode */ |
| 277 | rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); |
| 278 | |
| 279 | return 0; |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 280 | } |
| 281 | |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 282 | /* |
| 283 | * functions for QSPI |
| 284 | */ |
Geert Uytterhoeven | 74da768 | 2014-01-24 09:43:53 +0100 | [diff] [blame] | 285 | static int qspi_set_config_register(struct rspi_data *rspi, int access_size) |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 286 | { |
| 287 | u16 spcmd; |
| 288 | int spbr; |
| 289 | |
| 290 | /* Sets output mode(CMOS) and MOSI signal(from previous transfer) */ |
| 291 | rspi_write8(rspi, 0x00, RSPI_SPPCR); |
| 292 | |
| 293 | /* Sets transfer bit rate */ |
| 294 | spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz); |
| 295 | rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); |
| 296 | |
Geert Uytterhoeven | 74da768 | 2014-01-24 09:43:53 +0100 | [diff] [blame] | 297 | /* Disable dummy transmission, set byte access */ |
| 298 | rspi_write8(rspi, 0, RSPI_SPDCR); |
| 299 | rspi->byte_access = 1; |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 300 | |
| 301 | /* Sets RSPCK, SSL, next-access delay value */ |
| 302 | rspi_write8(rspi, 0x00, RSPI_SPCKD); |
| 303 | rspi_write8(rspi, 0x00, RSPI_SSLND); |
| 304 | rspi_write8(rspi, 0x00, RSPI_SPND); |
| 305 | |
| 306 | /* Data Length Setting */ |
| 307 | if (access_size == 8) |
| 308 | spcmd = SPCMD_SPB_8BIT; |
| 309 | else if (access_size == 16) |
| 310 | spcmd = SPCMD_SPB_16BIT; |
Laurent Pinchart | 8e1c809 | 2013-11-27 01:41:44 +0100 | [diff] [blame] | 311 | else |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 312 | spcmd = SPCMD_SPB_32BIT; |
| 313 | |
Geert Uytterhoeven | 348e515 | 2014-01-12 11:27:43 +0100 | [diff] [blame] | 314 | spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | rspi->spcmd | SPCMD_SPNDEN; |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 315 | |
| 316 | /* Resets transfer data length */ |
| 317 | rspi_write32(rspi, 0, QSPI_SPBMUL0); |
| 318 | |
| 319 | /* Resets transmit and receive buffer */ |
| 320 | rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR); |
| 321 | /* Sets buffer to allow normal operation */ |
| 322 | rspi_write8(rspi, 0x00, QSPI_SPBFCR); |
| 323 | |
| 324 | /* Sets SPCMD */ |
| 325 | rspi_write16(rspi, spcmd, RSPI_SPCMD0); |
| 326 | |
| 327 | /* Enables SPI function in a master mode */ |
| 328 | rspi_write8(rspi, SPCR_SPE | SPCR_MSTR, RSPI_SPCR); |
| 329 | |
| 330 | return 0; |
| 331 | } |
| 332 | |
| 333 | #define set_config_register(spi, n) spi->ops->set_config_register(spi, n) |
| 334 | |
Geert Uytterhoeven | baf588f | 2013-12-24 10:49:32 +0100 | [diff] [blame] | 335 | static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable) |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 336 | { |
| 337 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR); |
| 338 | } |
| 339 | |
Geert Uytterhoeven | baf588f | 2013-12-24 10:49:32 +0100 | [diff] [blame] | 340 | static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable) |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 341 | { |
| 342 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR); |
| 343 | } |
| 344 | |
| 345 | static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask, |
| 346 | u8 enable_bit) |
| 347 | { |
| 348 | int ret; |
| 349 | |
| 350 | rspi->spsr = rspi_read8(rspi, RSPI_SPSR); |
| 351 | rspi_enable_irq(rspi, enable_bit); |
| 352 | ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ); |
| 353 | if (ret == 0 && !(rspi->spsr & wait_mask)) |
| 354 | return -ETIMEDOUT; |
| 355 | |
| 356 | return 0; |
| 357 | } |
| 358 | |
Geert Uytterhoeven | 35301c9 | 2014-01-24 09:43:54 +0100 | [diff] [blame] | 359 | static int rspi_data_out(struct rspi_data *rspi, u8 data) |
| 360 | { |
| 361 | if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) { |
| 362 | dev_err(&rspi->master->dev, "transmit timeout\n"); |
| 363 | return -ETIMEDOUT; |
| 364 | } |
| 365 | rspi_write_data(rspi, data); |
| 366 | return 0; |
| 367 | } |
| 368 | |
| 369 | static int rspi_data_in(struct rspi_data *rspi) |
| 370 | { |
| 371 | u8 data; |
| 372 | |
| 373 | if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) { |
| 374 | dev_err(&rspi->master->dev, "receive timeout\n"); |
| 375 | return -ETIMEDOUT; |
| 376 | } |
| 377 | data = rspi_read_data(rspi); |
| 378 | return data; |
| 379 | } |
| 380 | |
| 381 | static int rspi_data_out_in(struct rspi_data *rspi, u8 data) |
| 382 | { |
| 383 | int ret; |
| 384 | |
| 385 | ret = rspi_data_out(rspi, data); |
| 386 | if (ret < 0) |
| 387 | return ret; |
| 388 | |
| 389 | return rspi_data_in(rspi); |
| 390 | } |
| 391 | |
Geert Uytterhoeven | 91949a2 | 2014-01-24 09:43:51 +0100 | [diff] [blame] | 392 | static int qspi_send_pio(struct rspi_data *rspi, struct spi_transfer *t) |
Hiep Cao Minh | cb52c67 | 2013-10-10 17:14:03 +0900 | [diff] [blame] | 393 | { |
Geert Uytterhoeven | 35301c9 | 2014-01-24 09:43:54 +0100 | [diff] [blame] | 394 | int remain = t->len, ret; |
Geert Uytterhoeven | c132f09 | 2013-12-24 10:49:31 +0100 | [diff] [blame] | 395 | const u8 *data = t->tx_buf; |
Hiep Cao Minh | cb52c67 | 2013-10-10 17:14:03 +0900 | [diff] [blame] | 396 | |
| 397 | rspi_write8(rspi, SPBFCR_TXRST, QSPI_SPBFCR); |
| 398 | rspi_write8(rspi, 0x00, QSPI_SPBFCR); |
| 399 | |
Hiep Cao Minh | cb52c67 | 2013-10-10 17:14:03 +0900 | [diff] [blame] | 400 | while (remain > 0) { |
Geert Uytterhoeven | 35301c9 | 2014-01-24 09:43:54 +0100 | [diff] [blame] | 401 | /* dummy read */ |
| 402 | ret = rspi_data_out_in(rspi, *data++); |
| 403 | if (ret < 0) |
| 404 | return ret; |
Hiep Cao Minh | cb52c67 | 2013-10-10 17:14:03 +0900 | [diff] [blame] | 405 | remain--; |
| 406 | } |
| 407 | |
Geert Uytterhoeven | b7ed6b8 | 2014-01-14 10:20:32 +0100 | [diff] [blame] | 408 | /* Waiting for the last transmission */ |
Hiep Cao Minh | cb52c67 | 2013-10-10 17:14:03 +0900 | [diff] [blame] | 409 | rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); |
| 410 | |
| 411 | return 0; |
| 412 | } |
| 413 | |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 414 | static void rspi_dma_complete(void *arg) |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 415 | { |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 416 | struct rspi_data *rspi = arg; |
| 417 | |
| 418 | rspi->dma_callbacked = 1; |
| 419 | wake_up_interruptible(&rspi->wait); |
| 420 | } |
| 421 | |
Geert Uytterhoeven | c132f09 | 2013-12-24 10:49:31 +0100 | [diff] [blame] | 422 | static int rspi_dma_map_sg(struct scatterlist *sg, const void *buf, |
| 423 | unsigned len, struct dma_chan *chan, |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 424 | enum dma_transfer_direction dir) |
| 425 | { |
| 426 | sg_init_table(sg, 1); |
| 427 | sg_set_buf(sg, buf, len); |
| 428 | sg_dma_len(sg) = len; |
| 429 | return dma_map_sg(chan->device->dev, sg, 1, dir); |
| 430 | } |
| 431 | |
| 432 | static void rspi_dma_unmap_sg(struct scatterlist *sg, struct dma_chan *chan, |
| 433 | enum dma_transfer_direction dir) |
| 434 | { |
| 435 | dma_unmap_sg(chan->device->dev, sg, 1, dir); |
| 436 | } |
| 437 | |
| 438 | static void rspi_memory_to_8bit(void *buf, const void *data, unsigned len) |
| 439 | { |
| 440 | u16 *dst = buf; |
| 441 | const u8 *src = data; |
| 442 | |
| 443 | while (len) { |
| 444 | *dst++ = (u16)(*src++); |
| 445 | len--; |
| 446 | } |
| 447 | } |
| 448 | |
| 449 | static void rspi_memory_from_8bit(void *buf, const void *data, unsigned len) |
| 450 | { |
| 451 | u8 *dst = buf; |
| 452 | const u16 *src = data; |
| 453 | |
| 454 | while (len) { |
| 455 | *dst++ = (u8)*src++; |
| 456 | len--; |
| 457 | } |
| 458 | } |
| 459 | |
| 460 | static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t) |
| 461 | { |
| 462 | struct scatterlist sg; |
Geert Uytterhoeven | c132f09 | 2013-12-24 10:49:31 +0100 | [diff] [blame] | 463 | const void *buf = NULL; |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 464 | struct dma_async_tx_descriptor *desc; |
| 465 | unsigned len; |
| 466 | int ret = 0; |
| 467 | |
| 468 | if (rspi->dma_width_16bit) { |
Geert Uytterhoeven | c132f09 | 2013-12-24 10:49:31 +0100 | [diff] [blame] | 469 | void *tmp; |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 470 | /* |
| 471 | * If DMAC bus width is 16-bit, the driver allocates a dummy |
| 472 | * buffer. And, the driver converts original data into the |
| 473 | * DMAC data as the following format: |
| 474 | * original data: 1st byte, 2nd byte ... |
| 475 | * DMAC data: 1st byte, dummy, 2nd byte, dummy ... |
| 476 | */ |
| 477 | len = t->len * 2; |
Geert Uytterhoeven | c132f09 | 2013-12-24 10:49:31 +0100 | [diff] [blame] | 478 | tmp = kmalloc(len, GFP_KERNEL); |
| 479 | if (!tmp) |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 480 | return -ENOMEM; |
Geert Uytterhoeven | c132f09 | 2013-12-24 10:49:31 +0100 | [diff] [blame] | 481 | rspi_memory_to_8bit(tmp, t->tx_buf, t->len); |
| 482 | buf = tmp; |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 483 | } else { |
| 484 | len = t->len; |
Geert Uytterhoeven | c132f09 | 2013-12-24 10:49:31 +0100 | [diff] [blame] | 485 | buf = t->tx_buf; |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 486 | } |
| 487 | |
| 488 | if (!rspi_dma_map_sg(&sg, buf, len, rspi->chan_tx, DMA_TO_DEVICE)) { |
| 489 | ret = -EFAULT; |
| 490 | goto end_nomap; |
| 491 | } |
| 492 | desc = dmaengine_prep_slave_sg(rspi->chan_tx, &sg, 1, DMA_TO_DEVICE, |
| 493 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 494 | if (!desc) { |
| 495 | ret = -EIO; |
| 496 | goto end; |
| 497 | } |
| 498 | |
| 499 | /* |
| 500 | * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be |
| 501 | * called. So, this driver disables the IRQ while DMA transfer. |
| 502 | */ |
| 503 | disable_irq(rspi->irq); |
| 504 | |
| 505 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD, RSPI_SPCR); |
| 506 | rspi_enable_irq(rspi, SPCR_SPTIE); |
| 507 | rspi->dma_callbacked = 0; |
| 508 | |
| 509 | desc->callback = rspi_dma_complete; |
| 510 | desc->callback_param = rspi; |
| 511 | dmaengine_submit(desc); |
| 512 | dma_async_issue_pending(rspi->chan_tx); |
| 513 | |
| 514 | ret = wait_event_interruptible_timeout(rspi->wait, |
| 515 | rspi->dma_callbacked, HZ); |
| 516 | if (ret > 0 && rspi->dma_callbacked) |
| 517 | ret = 0; |
| 518 | else if (!ret) |
| 519 | ret = -ETIMEDOUT; |
| 520 | rspi_disable_irq(rspi, SPCR_SPTIE); |
| 521 | |
| 522 | enable_irq(rspi->irq); |
| 523 | |
| 524 | end: |
| 525 | rspi_dma_unmap_sg(&sg, rspi->chan_tx, DMA_TO_DEVICE); |
| 526 | end_nomap: |
| 527 | if (rspi->dma_width_16bit) |
| 528 | kfree(buf); |
| 529 | |
| 530 | return ret; |
| 531 | } |
| 532 | |
Geert Uytterhoeven | baf588f | 2013-12-24 10:49:32 +0100 | [diff] [blame] | 533 | static void rspi_receive_init(const struct rspi_data *rspi) |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 534 | { |
Geert Uytterhoeven | 97b95c1 | 2013-12-24 10:49:34 +0100 | [diff] [blame] | 535 | u8 spsr; |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 536 | |
| 537 | spsr = rspi_read8(rspi, RSPI_SPSR); |
| 538 | if (spsr & SPSR_SPRF) |
Geert Uytterhoeven | 74da768 | 2014-01-24 09:43:53 +0100 | [diff] [blame] | 539 | rspi_read_data(rspi); /* dummy read */ |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 540 | if (spsr & SPSR_OVRF) |
| 541 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF, |
Geert Uytterhoeven | df900e6 | 2013-12-23 19:34:24 +0100 | [diff] [blame] | 542 | RSPI_SPSR); |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 543 | } |
| 544 | |
Geert Uytterhoeven | baf588f | 2013-12-24 10:49:32 +0100 | [diff] [blame] | 545 | static void qspi_receive_init(const struct rspi_data *rspi) |
Hiep Cao Minh | cb52c67 | 2013-10-10 17:14:03 +0900 | [diff] [blame] | 546 | { |
Geert Uytterhoeven | 97b95c1 | 2013-12-24 10:49:34 +0100 | [diff] [blame] | 547 | u8 spsr; |
Hiep Cao Minh | cb52c67 | 2013-10-10 17:14:03 +0900 | [diff] [blame] | 548 | |
| 549 | spsr = rspi_read8(rspi, RSPI_SPSR); |
| 550 | if (spsr & SPSR_SPRF) |
Geert Uytterhoeven | 74da768 | 2014-01-24 09:43:53 +0100 | [diff] [blame] | 551 | rspi_read_data(rspi); /* dummy read */ |
Hiep Cao Minh | cb52c67 | 2013-10-10 17:14:03 +0900 | [diff] [blame] | 552 | rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR); |
| 553 | rspi_write8(rspi, 0x00, QSPI_SPBFCR); |
| 554 | } |
| 555 | |
Geert Uytterhoeven | 91949a2 | 2014-01-24 09:43:51 +0100 | [diff] [blame] | 556 | static int qspi_receive_pio(struct rspi_data *rspi, struct spi_transfer *t) |
Hiep Cao Minh | cb52c67 | 2013-10-10 17:14:03 +0900 | [diff] [blame] | 557 | { |
Geert Uytterhoeven | 35301c9 | 2014-01-24 09:43:54 +0100 | [diff] [blame] | 558 | int remain = t->len, ret; |
| 559 | u8 *data = t->rx_buf; |
Hiep Cao Minh | cb52c67 | 2013-10-10 17:14:03 +0900 | [diff] [blame] | 560 | |
| 561 | qspi_receive_init(rspi); |
| 562 | |
Hiep Cao Minh | cb52c67 | 2013-10-10 17:14:03 +0900 | [diff] [blame] | 563 | while (remain > 0) { |
Hiep Cao Minh | cb52c67 | 2013-10-10 17:14:03 +0900 | [diff] [blame] | 564 | /* dummy write for generate clock */ |
Geert Uytterhoeven | 35301c9 | 2014-01-24 09:43:54 +0100 | [diff] [blame] | 565 | ret = rspi_data_out_in(rspi, DUMMY_DATA); |
| 566 | if (ret < 0) |
| 567 | return ret; |
| 568 | *data++ = ret; |
Hiep Cao Minh | cb52c67 | 2013-10-10 17:14:03 +0900 | [diff] [blame] | 569 | remain--; |
| 570 | } |
| 571 | |
| 572 | return 0; |
| 573 | } |
| 574 | |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 575 | static int rspi_receive_dma(struct rspi_data *rspi, struct spi_transfer *t) |
| 576 | { |
| 577 | struct scatterlist sg, sg_dummy; |
| 578 | void *dummy = NULL, *rx_buf = NULL; |
| 579 | struct dma_async_tx_descriptor *desc, *desc_dummy; |
| 580 | unsigned len; |
| 581 | int ret = 0; |
| 582 | |
| 583 | if (rspi->dma_width_16bit) { |
| 584 | /* |
| 585 | * If DMAC bus width is 16-bit, the driver allocates a dummy |
| 586 | * buffer. And, finally the driver converts the DMAC data into |
| 587 | * actual data as the following format: |
| 588 | * DMAC data: 1st byte, dummy, 2nd byte, dummy ... |
| 589 | * actual data: 1st byte, 2nd byte ... |
| 590 | */ |
| 591 | len = t->len * 2; |
| 592 | rx_buf = kmalloc(len, GFP_KERNEL); |
| 593 | if (!rx_buf) |
| 594 | return -ENOMEM; |
| 595 | } else { |
| 596 | len = t->len; |
| 597 | rx_buf = t->rx_buf; |
| 598 | } |
| 599 | |
| 600 | /* prepare dummy transfer to generate SPI clocks */ |
| 601 | dummy = kzalloc(len, GFP_KERNEL); |
| 602 | if (!dummy) { |
| 603 | ret = -ENOMEM; |
| 604 | goto end_nomap; |
| 605 | } |
| 606 | if (!rspi_dma_map_sg(&sg_dummy, dummy, len, rspi->chan_tx, |
| 607 | DMA_TO_DEVICE)) { |
| 608 | ret = -EFAULT; |
| 609 | goto end_nomap; |
| 610 | } |
| 611 | desc_dummy = dmaengine_prep_slave_sg(rspi->chan_tx, &sg_dummy, 1, |
| 612 | DMA_TO_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 613 | if (!desc_dummy) { |
| 614 | ret = -EIO; |
| 615 | goto end_dummy_mapped; |
| 616 | } |
| 617 | |
| 618 | /* prepare receive transfer */ |
| 619 | if (!rspi_dma_map_sg(&sg, rx_buf, len, rspi->chan_rx, |
| 620 | DMA_FROM_DEVICE)) { |
| 621 | ret = -EFAULT; |
| 622 | goto end_dummy_mapped; |
| 623 | |
| 624 | } |
| 625 | desc = dmaengine_prep_slave_sg(rspi->chan_rx, &sg, 1, DMA_FROM_DEVICE, |
| 626 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 627 | if (!desc) { |
| 628 | ret = -EIO; |
| 629 | goto end; |
| 630 | } |
| 631 | |
| 632 | rspi_receive_init(rspi); |
| 633 | |
| 634 | /* |
| 635 | * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be |
| 636 | * called. So, this driver disables the IRQ while DMA transfer. |
| 637 | */ |
| 638 | disable_irq(rspi->irq); |
| 639 | |
| 640 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD, RSPI_SPCR); |
| 641 | rspi_enable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE); |
| 642 | rspi->dma_callbacked = 0; |
| 643 | |
| 644 | desc->callback = rspi_dma_complete; |
| 645 | desc->callback_param = rspi; |
| 646 | dmaengine_submit(desc); |
| 647 | dma_async_issue_pending(rspi->chan_rx); |
| 648 | |
| 649 | desc_dummy->callback = NULL; /* No callback */ |
| 650 | dmaengine_submit(desc_dummy); |
| 651 | dma_async_issue_pending(rspi->chan_tx); |
| 652 | |
| 653 | ret = wait_event_interruptible_timeout(rspi->wait, |
| 654 | rspi->dma_callbacked, HZ); |
| 655 | if (ret > 0 && rspi->dma_callbacked) |
| 656 | ret = 0; |
| 657 | else if (!ret) |
| 658 | ret = -ETIMEDOUT; |
| 659 | rspi_disable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE); |
| 660 | |
| 661 | enable_irq(rspi->irq); |
| 662 | |
| 663 | end: |
| 664 | rspi_dma_unmap_sg(&sg, rspi->chan_rx, DMA_FROM_DEVICE); |
| 665 | end_dummy_mapped: |
| 666 | rspi_dma_unmap_sg(&sg_dummy, rspi->chan_tx, DMA_TO_DEVICE); |
| 667 | end_nomap: |
| 668 | if (rspi->dma_width_16bit) { |
| 669 | if (!ret) |
| 670 | rspi_memory_from_8bit(t->rx_buf, rx_buf, t->len); |
| 671 | kfree(rx_buf); |
| 672 | } |
| 673 | kfree(dummy); |
| 674 | |
| 675 | return ret; |
| 676 | } |
| 677 | |
Geert Uytterhoeven | baf588f | 2013-12-24 10:49:32 +0100 | [diff] [blame] | 678 | static int rspi_is_dma(const struct rspi_data *rspi, struct spi_transfer *t) |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 679 | { |
| 680 | if (t->tx_buf && rspi->chan_tx) |
| 681 | return 1; |
| 682 | /* If the module receives data by DMAC, it also needs TX DMAC */ |
| 683 | if (t->rx_buf && rspi->chan_tx && rspi->chan_rx) |
| 684 | return 1; |
| 685 | |
| 686 | return 0; |
| 687 | } |
| 688 | |
Geert Uytterhoeven | 8449fd7 | 2014-01-24 09:43:56 +0100 | [diff] [blame^] | 689 | static int rspi_transfer_out_in(struct rspi_data *rspi, |
| 690 | struct spi_transfer *xfer) |
| 691 | { |
| 692 | int remain = xfer->len, ret; |
| 693 | const u8 *tx_buf = xfer->tx_buf; |
| 694 | u8 *rx_buf = xfer->rx_buf; |
| 695 | u8 spcr, data; |
| 696 | |
| 697 | rspi_receive_init(rspi); |
| 698 | |
| 699 | spcr = rspi_read8(rspi, RSPI_SPCR); |
| 700 | if (rx_buf) |
| 701 | spcr &= ~SPCR_TXMD; |
| 702 | else |
| 703 | spcr |= SPCR_TXMD; |
| 704 | rspi_write8(rspi, spcr, RSPI_SPCR); |
| 705 | |
| 706 | while (remain > 0) { |
| 707 | data = tx_buf ? *tx_buf++ : DUMMY_DATA; |
| 708 | ret = rspi_data_out(rspi, data); |
| 709 | if (ret < 0) |
| 710 | return ret; |
| 711 | if (rx_buf) { |
| 712 | ret = rspi_data_in(rspi); |
| 713 | if (ret < 0) |
| 714 | return ret; |
| 715 | *rx_buf++ = ret; |
| 716 | } |
| 717 | remain--; |
| 718 | } |
| 719 | |
| 720 | /* Wait for the last transmission */ |
| 721 | rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); |
| 722 | |
| 723 | return 0; |
| 724 | } |
| 725 | |
Geert Uytterhoeven | 79d2349 | 2014-01-24 09:43:52 +0100 | [diff] [blame] | 726 | static int rspi_transfer_one(struct spi_master *master, struct spi_device *spi, |
| 727 | struct spi_transfer *xfer) |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 728 | { |
Geert Uytterhoeven | 79d2349 | 2014-01-24 09:43:52 +0100 | [diff] [blame] | 729 | struct rspi_data *rspi = spi_master_get_devdata(master); |
Geert Uytterhoeven | 8449fd7 | 2014-01-24 09:43:56 +0100 | [diff] [blame^] | 730 | int ret; |
| 731 | |
| 732 | if (!rspi_is_dma(rspi, xfer)) |
| 733 | return rspi_transfer_out_in(rspi, xfer); |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 734 | |
Geert Uytterhoeven | 79d2349 | 2014-01-24 09:43:52 +0100 | [diff] [blame] | 735 | if (xfer->tx_buf) { |
Geert Uytterhoeven | 8449fd7 | 2014-01-24 09:43:56 +0100 | [diff] [blame^] | 736 | ret = rspi_send_dma(rspi, xfer); |
Geert Uytterhoeven | 79d2349 | 2014-01-24 09:43:52 +0100 | [diff] [blame] | 737 | if (ret < 0) |
| 738 | return ret; |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 739 | } |
Geert Uytterhoeven | 8449fd7 | 2014-01-24 09:43:56 +0100 | [diff] [blame^] | 740 | if (xfer->rx_buf) |
| 741 | return rspi_receive_dma(rspi, xfer); |
| 742 | |
| 743 | return 0; |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 744 | } |
| 745 | |
Geert Uytterhoeven | eb557f7 | 2014-01-24 09:43:55 +0100 | [diff] [blame] | 746 | static int qspi_transfer_one(struct spi_master *master, struct spi_device *spi, |
| 747 | struct spi_transfer *xfer) |
| 748 | { |
| 749 | struct rspi_data *rspi = spi_master_get_devdata(master); |
| 750 | int ret = 0; |
| 751 | |
| 752 | if (xfer->tx_buf) { |
| 753 | ret = qspi_send_pio(rspi, xfer); |
| 754 | if (ret < 0) |
| 755 | return ret; |
| 756 | } |
| 757 | if (xfer->rx_buf) |
| 758 | ret = qspi_receive_pio(rspi, xfer); |
| 759 | return ret; |
| 760 | } |
| 761 | |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 762 | static int rspi_setup(struct spi_device *spi) |
| 763 | { |
| 764 | struct rspi_data *rspi = spi_master_get_devdata(spi->master); |
| 765 | |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 766 | rspi->max_speed_hz = spi->max_speed_hz; |
| 767 | |
Geert Uytterhoeven | 348e515 | 2014-01-12 11:27:43 +0100 | [diff] [blame] | 768 | rspi->spcmd = SPCMD_SSLKP; |
| 769 | if (spi->mode & SPI_CPOL) |
| 770 | rspi->spcmd |= SPCMD_CPOL; |
| 771 | if (spi->mode & SPI_CPHA) |
| 772 | rspi->spcmd |= SPCMD_CPHA; |
| 773 | |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 774 | set_config_register(rspi, 8); |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 775 | |
| 776 | return 0; |
| 777 | } |
| 778 | |
Geert Uytterhoeven | 79d2349 | 2014-01-24 09:43:52 +0100 | [diff] [blame] | 779 | static void rspi_cleanup(struct spi_device *spi) |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 780 | { |
Geert Uytterhoeven | 79d2349 | 2014-01-24 09:43:52 +0100 | [diff] [blame] | 781 | } |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 782 | |
Geert Uytterhoeven | 79d2349 | 2014-01-24 09:43:52 +0100 | [diff] [blame] | 783 | static int rspi_prepare_message(struct spi_master *master, |
| 784 | struct spi_message *message) |
| 785 | { |
| 786 | struct rspi_data *rspi = spi_master_get_devdata(master); |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 787 | |
Geert Uytterhoeven | 79d2349 | 2014-01-24 09:43:52 +0100 | [diff] [blame] | 788 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR); |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 789 | return 0; |
| 790 | } |
| 791 | |
Geert Uytterhoeven | 79d2349 | 2014-01-24 09:43:52 +0100 | [diff] [blame] | 792 | static int rspi_unprepare_message(struct spi_master *master, |
| 793 | struct spi_message *message) |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 794 | { |
Geert Uytterhoeven | 79d2349 | 2014-01-24 09:43:52 +0100 | [diff] [blame] | 795 | struct rspi_data *rspi = spi_master_get_devdata(master); |
| 796 | |
| 797 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR); |
| 798 | return 0; |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 799 | } |
| 800 | |
| 801 | static irqreturn_t rspi_irq(int irq, void *_sr) |
| 802 | { |
Geert Uytterhoeven | c132f09 | 2013-12-24 10:49:31 +0100 | [diff] [blame] | 803 | struct rspi_data *rspi = _sr; |
Geert Uytterhoeven | 97b95c1 | 2013-12-24 10:49:34 +0100 | [diff] [blame] | 804 | u8 spsr; |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 805 | irqreturn_t ret = IRQ_NONE; |
Geert Uytterhoeven | 97b95c1 | 2013-12-24 10:49:34 +0100 | [diff] [blame] | 806 | u8 disable_irq = 0; |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 807 | |
| 808 | rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); |
| 809 | if (spsr & SPSR_SPRF) |
| 810 | disable_irq |= SPCR_SPRIE; |
| 811 | if (spsr & SPSR_SPTEF) |
| 812 | disable_irq |= SPCR_SPTIE; |
| 813 | |
| 814 | if (disable_irq) { |
| 815 | ret = IRQ_HANDLED; |
| 816 | rspi_disable_irq(rspi, disable_irq); |
| 817 | wake_up(&rspi->wait); |
| 818 | } |
| 819 | |
| 820 | return ret; |
| 821 | } |
| 822 | |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 823 | static int rspi_request_dma(struct rspi_data *rspi, |
Shimoda, Yoshihiro | 0243c53 | 2012-08-02 17:17:33 +0900 | [diff] [blame] | 824 | struct platform_device *pdev) |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 825 | { |
Geert Uytterhoeven | baf588f | 2013-12-24 10:49:32 +0100 | [diff] [blame] | 826 | const struct rspi_plat_data *rspi_pd = dev_get_platdata(&pdev->dev); |
Guennadi Liakhovetski | e2b0509 | 2013-08-02 15:03:42 +0200 | [diff] [blame] | 827 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 828 | dma_cap_mask_t mask; |
Shimoda, Yoshihiro | 0243c53 | 2012-08-02 17:17:33 +0900 | [diff] [blame] | 829 | struct dma_slave_config cfg; |
| 830 | int ret; |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 831 | |
Guennadi Liakhovetski | e2b0509 | 2013-08-02 15:03:42 +0200 | [diff] [blame] | 832 | if (!res || !rspi_pd) |
Shimoda, Yoshihiro | 0243c53 | 2012-08-02 17:17:33 +0900 | [diff] [blame] | 833 | return 0; /* The driver assumes no error. */ |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 834 | |
| 835 | rspi->dma_width_16bit = rspi_pd->dma_width_16bit; |
| 836 | |
| 837 | /* If the module receives data by DMAC, it also needs TX DMAC */ |
| 838 | if (rspi_pd->dma_rx_id && rspi_pd->dma_tx_id) { |
| 839 | dma_cap_zero(mask); |
| 840 | dma_cap_set(DMA_SLAVE, mask); |
Shimoda, Yoshihiro | 0243c53 | 2012-08-02 17:17:33 +0900 | [diff] [blame] | 841 | rspi->chan_rx = dma_request_channel(mask, shdma_chan_filter, |
| 842 | (void *)rspi_pd->dma_rx_id); |
| 843 | if (rspi->chan_rx) { |
| 844 | cfg.slave_id = rspi_pd->dma_rx_id; |
| 845 | cfg.direction = DMA_DEV_TO_MEM; |
Guennadi Liakhovetski | e2b0509 | 2013-08-02 15:03:42 +0200 | [diff] [blame] | 846 | cfg.dst_addr = 0; |
| 847 | cfg.src_addr = res->start + RSPI_SPDR; |
Shimoda, Yoshihiro | 0243c53 | 2012-08-02 17:17:33 +0900 | [diff] [blame] | 848 | ret = dmaengine_slave_config(rspi->chan_rx, &cfg); |
| 849 | if (!ret) |
| 850 | dev_info(&pdev->dev, "Use DMA when rx.\n"); |
| 851 | else |
| 852 | return ret; |
| 853 | } |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 854 | } |
| 855 | if (rspi_pd->dma_tx_id) { |
| 856 | dma_cap_zero(mask); |
| 857 | dma_cap_set(DMA_SLAVE, mask); |
Shimoda, Yoshihiro | 0243c53 | 2012-08-02 17:17:33 +0900 | [diff] [blame] | 858 | rspi->chan_tx = dma_request_channel(mask, shdma_chan_filter, |
| 859 | (void *)rspi_pd->dma_tx_id); |
| 860 | if (rspi->chan_tx) { |
| 861 | cfg.slave_id = rspi_pd->dma_tx_id; |
| 862 | cfg.direction = DMA_MEM_TO_DEV; |
Guennadi Liakhovetski | e2b0509 | 2013-08-02 15:03:42 +0200 | [diff] [blame] | 863 | cfg.dst_addr = res->start + RSPI_SPDR; |
| 864 | cfg.src_addr = 0; |
Shimoda, Yoshihiro | 0243c53 | 2012-08-02 17:17:33 +0900 | [diff] [blame] | 865 | ret = dmaengine_slave_config(rspi->chan_tx, &cfg); |
| 866 | if (!ret) |
| 867 | dev_info(&pdev->dev, "Use DMA when tx\n"); |
| 868 | else |
| 869 | return ret; |
| 870 | } |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 871 | } |
Shimoda, Yoshihiro | 0243c53 | 2012-08-02 17:17:33 +0900 | [diff] [blame] | 872 | |
| 873 | return 0; |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 874 | } |
| 875 | |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 876 | static void rspi_release_dma(struct rspi_data *rspi) |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 877 | { |
| 878 | if (rspi->chan_tx) |
| 879 | dma_release_channel(rspi->chan_tx); |
| 880 | if (rspi->chan_rx) |
| 881 | dma_release_channel(rspi->chan_rx); |
| 882 | } |
| 883 | |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 884 | static int rspi_remove(struct platform_device *pdev) |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 885 | { |
Laurent Pinchart | 5ffbe2d | 2013-11-27 01:41:45 +0100 | [diff] [blame] | 886 | struct rspi_data *rspi = platform_get_drvdata(pdev); |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 887 | |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 888 | rspi_release_dma(rspi); |
Geert Uytterhoeven | fcb4ed7 | 2014-01-14 10:20:33 +0100 | [diff] [blame] | 889 | clk_disable(rspi->clk); |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 890 | |
| 891 | return 0; |
| 892 | } |
| 893 | |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 894 | static int rspi_probe(struct platform_device *pdev) |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 895 | { |
| 896 | struct resource *res; |
| 897 | struct spi_master *master; |
| 898 | struct rspi_data *rspi; |
| 899 | int ret, irq; |
| 900 | char clk_name[16]; |
Geert Uytterhoeven | baf588f | 2013-12-24 10:49:32 +0100 | [diff] [blame] | 901 | const struct rspi_plat_data *rspi_pd = dev_get_platdata(&pdev->dev); |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 902 | const struct spi_ops *ops; |
| 903 | const struct platform_device_id *id_entry = pdev->id_entry; |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 904 | |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 905 | ops = (struct spi_ops *)id_entry->driver_data; |
| 906 | /* ops parameter check */ |
| 907 | if (!ops->set_config_register) { |
| 908 | dev_err(&pdev->dev, "there is no set_config_register\n"); |
| 909 | return -ENODEV; |
| 910 | } |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 911 | |
| 912 | irq = platform_get_irq(pdev, 0); |
| 913 | if (irq < 0) { |
| 914 | dev_err(&pdev->dev, "platform_get_irq error\n"); |
| 915 | return -ENODEV; |
| 916 | } |
| 917 | |
| 918 | master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data)); |
| 919 | if (master == NULL) { |
| 920 | dev_err(&pdev->dev, "spi_alloc_master error.\n"); |
| 921 | return -ENOMEM; |
| 922 | } |
| 923 | |
| 924 | rspi = spi_master_get_devdata(master); |
Jingoo Han | 24b5a82 | 2013-05-23 19:20:40 +0900 | [diff] [blame] | 925 | platform_set_drvdata(pdev, rspi); |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 926 | rspi->ops = ops; |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 927 | rspi->master = master; |
Laurent Pinchart | 5d79e9a | 2013-11-27 01:41:46 +0100 | [diff] [blame] | 928 | |
| 929 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 930 | rspi->addr = devm_ioremap_resource(&pdev->dev, res); |
| 931 | if (IS_ERR(rspi->addr)) { |
| 932 | ret = PTR_ERR(rspi->addr); |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 933 | goto error1; |
| 934 | } |
| 935 | |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 936 | snprintf(clk_name, sizeof(clk_name), "%s%d", id_entry->name, pdev->id); |
Laurent Pinchart | 5d79e9a | 2013-11-27 01:41:46 +0100 | [diff] [blame] | 937 | rspi->clk = devm_clk_get(&pdev->dev, clk_name); |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 938 | if (IS_ERR(rspi->clk)) { |
| 939 | dev_err(&pdev->dev, "cannot get clock\n"); |
| 940 | ret = PTR_ERR(rspi->clk); |
Laurent Pinchart | 5d79e9a | 2013-11-27 01:41:46 +0100 | [diff] [blame] | 941 | goto error1; |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 942 | } |
| 943 | clk_enable(rspi->clk); |
| 944 | |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 945 | init_waitqueue_head(&rspi->wait); |
| 946 | |
Geert Uytterhoeven | efd85ac | 2013-12-23 19:34:23 +0100 | [diff] [blame] | 947 | if (rspi_pd && rspi_pd->num_chipselect) |
| 948 | master->num_chipselect = rspi_pd->num_chipselect; |
| 949 | else |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 950 | master->num_chipselect = 2; /* default */ |
| 951 | |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 952 | master->bus_num = pdev->id; |
| 953 | master->setup = rspi_setup; |
Geert Uytterhoeven | eb557f7 | 2014-01-24 09:43:55 +0100 | [diff] [blame] | 954 | master->transfer_one = ops->transfer_one; |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 955 | master->cleanup = rspi_cleanup; |
Geert Uytterhoeven | 79d2349 | 2014-01-24 09:43:52 +0100 | [diff] [blame] | 956 | master->prepare_message = rspi_prepare_message; |
| 957 | master->unprepare_message = rspi_unprepare_message; |
Geert Uytterhoeven | 348e515 | 2014-01-12 11:27:43 +0100 | [diff] [blame] | 958 | master->mode_bits = SPI_CPHA | SPI_CPOL; |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 959 | |
Laurent Pinchart | 5d79e9a | 2013-11-27 01:41:46 +0100 | [diff] [blame] | 960 | ret = devm_request_irq(&pdev->dev, irq, rspi_irq, 0, |
| 961 | dev_name(&pdev->dev), rspi); |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 962 | if (ret < 0) { |
| 963 | dev_err(&pdev->dev, "request_irq error\n"); |
Geert Uytterhoeven | fcb4ed7 | 2014-01-14 10:20:33 +0100 | [diff] [blame] | 964 | goto error2; |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 965 | } |
| 966 | |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 967 | rspi->irq = irq; |
Shimoda, Yoshihiro | 0243c53 | 2012-08-02 17:17:33 +0900 | [diff] [blame] | 968 | ret = rspi_request_dma(rspi, pdev); |
| 969 | if (ret < 0) { |
| 970 | dev_err(&pdev->dev, "rspi_request_dma failed.\n"); |
Geert Uytterhoeven | fcb4ed7 | 2014-01-14 10:20:33 +0100 | [diff] [blame] | 971 | goto error3; |
Shimoda, Yoshihiro | 0243c53 | 2012-08-02 17:17:33 +0900 | [diff] [blame] | 972 | } |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 973 | |
Jingoo Han | 9e03d05 | 2013-12-04 14:13:50 +0900 | [diff] [blame] | 974 | ret = devm_spi_register_master(&pdev->dev, master); |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 975 | if (ret < 0) { |
| 976 | dev_err(&pdev->dev, "spi_register_master error.\n"); |
Geert Uytterhoeven | fcb4ed7 | 2014-01-14 10:20:33 +0100 | [diff] [blame] | 977 | goto error3; |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 978 | } |
| 979 | |
| 980 | dev_info(&pdev->dev, "probed\n"); |
| 981 | |
| 982 | return 0; |
| 983 | |
Geert Uytterhoeven | fcb4ed7 | 2014-01-14 10:20:33 +0100 | [diff] [blame] | 984 | error3: |
Laurent Pinchart | 5d79e9a | 2013-11-27 01:41:46 +0100 | [diff] [blame] | 985 | rspi_release_dma(rspi); |
Geert Uytterhoeven | fcb4ed7 | 2014-01-14 10:20:33 +0100 | [diff] [blame] | 986 | error2: |
| 987 | clk_disable(rspi->clk); |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 988 | error1: |
| 989 | spi_master_put(master); |
| 990 | |
| 991 | return ret; |
| 992 | } |
| 993 | |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 994 | static struct spi_ops rspi_ops = { |
| 995 | .set_config_register = rspi_set_config_register, |
Geert Uytterhoeven | eb557f7 | 2014-01-24 09:43:55 +0100 | [diff] [blame] | 996 | .transfer_one = rspi_transfer_one, |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 997 | }; |
| 998 | |
| 999 | static struct spi_ops qspi_ops = { |
| 1000 | .set_config_register = qspi_set_config_register, |
Geert Uytterhoeven | eb557f7 | 2014-01-24 09:43:55 +0100 | [diff] [blame] | 1001 | .transfer_one = qspi_transfer_one, |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 1002 | }; |
| 1003 | |
| 1004 | static struct platform_device_id spi_driver_ids[] = { |
| 1005 | { "rspi", (kernel_ulong_t)&rspi_ops }, |
| 1006 | { "qspi", (kernel_ulong_t)&qspi_ops }, |
| 1007 | {}, |
| 1008 | }; |
| 1009 | |
| 1010 | MODULE_DEVICE_TABLE(platform, spi_driver_ids); |
| 1011 | |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 1012 | static struct platform_driver rspi_driver = { |
| 1013 | .probe = rspi_probe, |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 1014 | .remove = rspi_remove, |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 1015 | .id_table = spi_driver_ids, |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 1016 | .driver = { |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 1017 | .name = "renesas_spi", |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 1018 | .owner = THIS_MODULE, |
| 1019 | }, |
| 1020 | }; |
| 1021 | module_platform_driver(rspi_driver); |
| 1022 | |
| 1023 | MODULE_DESCRIPTION("Renesas RSPI bus driver"); |
| 1024 | MODULE_LICENSE("GPL v2"); |
| 1025 | MODULE_AUTHOR("Yoshihiro Shimoda"); |
| 1026 | MODULE_ALIAS("platform:rspi"); |