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Catalin Marinas4f04d8f2012-03-05 11:49:27 +00001 Memory Layout on AArch64 Linux
2 ==============================
3
4Author: Catalin Marinas <catalin.marinas@arm.com>
5Date : 20 February 2012
6
7This document describes the virtual memory layout used by the AArch64
8Linux kernel. The architecture allows up to 4 levels of translation
9tables with a 4KB page size and up to 3 levels with a 64KB page size.
10
11AArch64 Linux uses 3 levels of translation tables with the 4KB page
12configuration, allowing 39-bit (512GB) virtual addresses for both user
13and kernel. With 64KB pages, only 2 levels of translation tables are
14used but the memory layout is the same.
15
16User addresses have bits 63:39 set to 0 while the kernel addresses have
17the same bits set to 1. TTBRx selection is given by bit 63 of the
18virtual address. The swapper_pg_dir contains only kernel (global)
19mappings while the user pgd contains only user (non-global) mappings.
20The swapper_pgd_dir address is written to TTBR1 and never written to
21TTBR0.
22
23
Catalin Marinas847264fb2013-10-23 16:50:07 +010024AArch64 Linux memory layout with 4KB pages:
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000025
26Start End Size Use
27-----------------------------------------------------------------------
280000000000000000 0000007fffffffff 512GB user
29
Catalin Marinase3978cd2012-10-23 14:51:16 +010030ffffff8000000000 ffffffbbfffeffff ~240GB vmalloc
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000031
Catalin Marinase3978cd2012-10-23 14:51:16 +010032ffffffbbffff0000 ffffffbbffffffff 64KB [guard page]
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000033
34ffffffbc00000000 ffffffbdffffffff 8GB vmemmap
35
Catalin Marinase3978cd2012-10-23 14:51:16 +010036ffffffbe00000000 ffffffbffbbfffff ~8GB [guard, future vmmemap]
37
Catalin Marinas2475ff92012-10-23 14:55:08 +010038ffffffbffbc00000 ffffffbffbdfffff 2MB earlyprintk device
39
Catalin Marinase3978cd2012-10-23 14:51:16 +010040ffffffbffbe00000 ffffffbffbe0ffff 64KB PCI I/O space
41
Catalin Marinase29a0742013-10-24 12:00:28 +010042ffffffbffbe10000 ffffffbcffffffff ~2MB [guard]
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000043
44ffffffbffc000000 ffffffbfffffffff 64MB modules
45
Tekkaman Ninja715a7112012-10-28 03:30:20 +000046ffffffc000000000 ffffffffffffffff 256GB kernel logical memory map
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000047
48
Catalin Marinas847264fb2013-10-23 16:50:07 +010049AArch64 Linux memory layout with 64KB pages:
50
51Start End Size Use
52-----------------------------------------------------------------------
530000000000000000 000003ffffffffff 4TB user
54
55fffffc0000000000 fffffdfbfffeffff ~2TB vmalloc
56
57fffffdfbffff0000 fffffdfbffffffff 64KB [guard page]
58
59fffffdfc00000000 fffffdfdffffffff 8GB vmemmap
60
61fffffdfe00000000 fffffdfffbbfffff ~8GB [guard, future vmmemap]
62
63fffffdfffbc00000 fffffdfffbdfffff 2MB earlyprintk device
64
65fffffdfffbe00000 fffffdfffbe0ffff 64KB PCI I/O space
66
67fffffdfffbe10000 fffffdfffbffffff ~2MB [guard]
68
69fffffdfffc000000 fffffdffffffffff 64MB modules
70
71fffffe0000000000 ffffffffffffffff 2TB kernel logical memory map
72
73
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000074Translation table lookup with 4KB pages:
75
76+--------+--------+--------+--------+--------+--------+--------+--------+
77|63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0|
78+--------+--------+--------+--------+--------+--------+--------+--------+
79 | | | | | |
80 | | | | | v
81 | | | | | [11:0] in-page offset
82 | | | | +-> [20:12] L3 index
83 | | | +-----------> [29:21] L2 index
84 | | +---------------------> [38:30] L1 index
85 | +-------------------------------> [47:39] L0 index (not used)
86 +-------------------------------------------------> [63] TTBR0/1
87
88
89Translation table lookup with 64KB pages:
90
91+--------+--------+--------+--------+--------+--------+--------+--------+
92|63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0|
93+--------+--------+--------+--------+--------+--------+--------+--------+
94 | | | | |
95 | | | | v
96 | | | | [15:0] in-page offset
97 | | | +----------> [28:16] L3 index
98 | | +--------------------------> [41:29] L2 index (only 38:29 used)
99 | +-------------------------------> [47:42] L1 index (not used)
100 +-------------------------------------------------> [63] TTBR0/1
Marc Zyngieraa4a73a2013-05-02 14:31:03 +0100101
102When using KVM, the hypervisor maps kernel pages in EL2, at a fixed
103offset from the kernel VA (top 24bits of the kernel VA set to zero):
104
105Start End Size Use
106-----------------------------------------------------------------------
1070000004000000000 0000007fffffffff 256GB kernel objects mapped in HYP