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gerrit-public.fairphone.software / kernel / msm-4.9 / 849c6e7746e4f6317ace6aa7d2fcdcd844e99ddb / . / arch / arm / boot / dts / vf610-cosmic.dts
blob: de1b453c2932f7e4cb7ad3d6d4eb227c34357afd [file] [log] [blame]
Matt Porter931398e2013-09-23 11:14:44 -0400[diff] [blame]1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 * Copyright 2013 Linaro Limited
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 */
10
11/dts-v1/;
12#include "vf610.dtsi"
13
14/ {
15 model = "PHYTEC Cosmic/Cosmic+ Board";
16 compatible = "phytec,vf610-cosmic", "fsl,vf610";
17
18 chosen {
19 bootargs = "console=ttyLP1,115200";
20 };
21
22 memory {
23 reg = <0x80000000 0x10000000>;
24 };
25
26 clocks {
27 enet_ext {
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <50000000>;
31 };
32 };
33
34};
35
Olof Johanssonab699bc2014-11-04 22:28:12 -0800[diff] [blame]36&esdhc1 {
37 pinctrl-names = "default";
38 pinctrl-0 = <&pinctrl_esdhc1>;
39 bus-width = <4>;
40 status = "okay";
41};
42
Matt Porter931398e2013-09-23 11:14:44 -0400[diff] [blame]43&fec1 {
44 phy-mode = "rmii";
45 pinctrl-names = "default";
Shawn Guo07ed1ee2013-12-09 14:42:54 +0800[diff] [blame]46 pinctrl-0 = <&pinctrl_fec1>;
Matt Porter931398e2013-09-23 11:14:44 -0400[diff] [blame]47 status = "okay";
48};
49
Shawn Guo07ed1ee2013-12-09 14:42:54 +0800[diff] [blame]50&iomuxc {
51 vf610-cosmic {
Olof Johanssonab699bc2014-11-04 22:28:12 -0800[diff] [blame]52 pinctrl_esdhc1: esdhc1grp {
53 fsl,pins = <
54 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
55 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
56 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
57 VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
58 VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
59 VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
60 VF610_PAD_PTB28__GPIO_98 0x219d
61 >;
62 };
63
Shawn Guo07ed1ee2013-12-09 14:42:54 +0800[diff] [blame]64 pinctrl_fec1: fec1grp {
65 fsl,pins = <
66 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
67 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
68 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
69 VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1
70 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
71 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
72 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
73 VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
74 VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
75 >;
76 };
77
78 pinctrl_uart1: uart1grp {
79 fsl,pins = <
80 VF610_PAD_PTB4__UART1_TX 0x21a2
81 VF610_PAD_PTB5__UART1_RX 0x21a1
82 >;
83 };
84 };
85};
86
Matt Porter931398e2013-09-23 11:14:44 -0400[diff] [blame]87&uart1 {
88 pinctrl-names = "default";
Shawn Guo07ed1ee2013-12-09 14:42:54 +0800[diff] [blame]89 pinctrl-0 = <&pinctrl_uart1>;
Matt Porter931398e2013-09-23 11:14:44 -0400[diff] [blame]90 status = "okay";
91};