| Deepak Katragadda | 24ee246 | 2016-12-16 14:26:38 -0800 | [diff] [blame] | 1 | Qualcomm Technologies, Inc. Display Clock & Reset Controller Binding |
| 2 | ---------------------------------------------------- |
| 3 | |
| 4 | Required properties : |
| Deepak Katragadda | 443bd8d | 2017-08-28 22:30:19 +0530 | [diff] [blame] | 5 | - compatible : shall contain "qcom,dispcc-sdm845", "qcom,dispcc-sdm845-v2" or |
| 6 | "qcom,dispcc-sdm670". |
| Deepak Katragadda | 24ee246 | 2016-12-16 14:26:38 -0800 | [diff] [blame] | 7 | - reg : shall contain base register location and length. |
| 8 | - reg-names: names of registers listed in the same order as in |
| 9 | the reg property. |
| 10 | - #clock-cells : shall contain 1. |
| 11 | - #reset-cells : shall contain 1. |
| 12 | |
| 13 | Optional properties : |
| 14 | - vdd_<rail>-supply: The logic rail supply. |
| 15 | |
| 16 | Example: |
| 17 | clock_dispcc: qcom,dispcc@af00000 { |
| 18 | compatible = "qcom,dispcc-sdm845"; |
| 19 | reg = <0xaf00000 0x100000>; |
| 20 | reg-names = "cc_base"; |
| 21 | vdd_cx-supply = <&pm8998_s9_level>; |
| 22 | #clock-cells = <1>; |
| 23 | #reset-cells = <1>; |
| 24 | }; |