| Deepak Katragadda | 136dd25 | 2016-11-09 17:45:15 -0800 | [diff] [blame] | 1 | Qualcomm Technologies Video Clock & Reset Controller Binding |
| 2 | ---------------------------------------------------- |
| 3 | |
| 4 | Required properties : |
| Deepak Katragadda | 443bd8d | 2017-08-28 22:30:19 +0530 | [diff] [blame] | 5 | - compatible : shall contain "qcom,video_cc-sdm845", "qcom,video_cc-sdm845-v2" |
| 6 | or "qcom,video_cc-sdm670". |
| Deepak Katragadda | 6c846e3 | 2017-06-07 14:09:49 -0700 | [diff] [blame] | 7 | - reg : shall contain base register location and length. |
| Deepak Katragadda | 136dd25 | 2016-11-09 17:45:15 -0800 | [diff] [blame] | 8 | - reg-names: names of registers listed in the same order as in |
| 9 | the reg property. |
| Deepak Katragadda | 6c846e3 | 2017-06-07 14:09:49 -0700 | [diff] [blame] | 10 | - #clock-cells : shall contain 1. |
| 11 | - #reset-cells : shall contain 1. |
| Deepak Katragadda | 136dd25 | 2016-11-09 17:45:15 -0800 | [diff] [blame] | 12 | |
| 13 | Optional properties : |
| 14 | - vdd_<rail>-supply: The logic rail supply. |
| 15 | |
| 16 | Example: |
| 17 | clock_videocc: qcom,videocc@ab00000 { |
| Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 18 | compatible = "qcom,video_cc-sdm845"; |
| Deepak Katragadda | 136dd25 | 2016-11-09 17:45:15 -0800 | [diff] [blame] | 19 | reg = <0xab00000 0x10000>; |
| 20 | reg-names = "cc_base"; |
| 21 | vdd_cx-supply = <&pmcobalt_s9_level>; |
| 22 | #clock-cells = <1>; |
| 23 | #reset-cells = <1>; |
| 24 | }; |