Rajesh Kemisetti | ba56c48 | 2017-08-31 18:12:35 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | &soc { |
| 14 | |
| 15 | pil_gpu: qcom,kgsl-hyp { |
| 16 | compatible = "qcom,pil-tz-generic"; |
| 17 | qcom,pas-id = <13>; |
| 18 | qcom,firmware-name = "a615_zap"; |
| 19 | }; |
| 20 | |
| 21 | msm_bus: qcom,kgsl-busmon{ |
| 22 | label = "kgsl-busmon"; |
| 23 | compatible = "qcom,kgsl-busmon"; |
| 24 | }; |
| 25 | |
| 26 | gpubw: qcom,gpubw { |
| 27 | compatible = "qcom,devbw"; |
| 28 | governor = "bw_vbif"; |
| 29 | qcom,src-dst-ports = <26 512>; |
| 30 | qcom,bw-tbl = |
| 31 | < 0 /* off */ >, |
| 32 | < 381 /* 100 MHz */ >, |
| 33 | < 762 /* 200 MHz */ >, |
| 34 | < 1144 /* 300 MHz */ >, |
| 35 | < 1720 /* 451 MHz */ >, |
| 36 | < 2086 /* 547 MHz */ >, |
| 37 | < 2597 /* 681 MHz */ >, |
| 38 | < 3147 /* 825 MHz */ >, |
| 39 | < 3879 /* 1017 MHz */ >, |
| 40 | < 5161 /* 1353 MHz */ >, |
| 41 | < 5931 /* 1555 MHz */ >, |
| 42 | < 6881 /* 1804 MHz */ >; |
| 43 | }; |
| 44 | |
| 45 | msm_gpu: qcom,kgsl-3d0@5000000 { |
| 46 | label = "kgsl-3d0"; |
| 47 | compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d"; |
| 48 | status = "ok"; |
| 49 | reg = <0x5000000 0x40000>; |
| 50 | reg-names = "kgsl_3d0_reg_memory"; |
| 51 | interrupts = <0 300 0>; |
| 52 | interrupt-names = "kgsl_3d0_irq"; |
| 53 | qcom,id = <0>; |
| 54 | |
| 55 | qcom,chipid = <0x06010500>; |
| 56 | |
| 57 | qcom,initial-pwrlevel = <3>; |
| 58 | |
| 59 | qcom,gpu-quirk-hfi-use-reg; |
| 60 | |
| 61 | /* <HZ/12> */ |
| 62 | qcom,idle-timeout = <80>; |
| 63 | qcom,no-nap; |
| 64 | |
| 65 | qcom,highest-bank-bit = <14>; |
| 66 | |
| 67 | qcom,min-access-length = <64>; |
| 68 | |
| 69 | qcom,ubwc-mode = <2>; |
| 70 | |
| 71 | /* size in bytes */ |
| 72 | qcom,snapshot-size = <1048576>; |
| 73 | |
| 74 | /* base addr, size */ |
| 75 | qcom,gpu-qdss-stm = <0x161c0000 0x40000>; |
| 76 | |
| 77 | clocks = <&clock_gfx GPU_CC_GX_GFX3D_CLK>, |
| 78 | <&clock_gpucc GPU_CC_CXO_CLK>, |
| 79 | <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>, |
| 80 | <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, |
| 81 | <&clock_gpucc GPU_CC_CX_GMU_CLK>, |
| 82 | <&clock_gpucc GPU_CC_AHB_CLK>; |
| 83 | |
| 84 | clock-names = "core_clk", "rbbmtimer_clk", "mem_clk", |
| 85 | "mem_iface_clk", "gmu_clk", "ahb_clk"; |
| 86 | |
| 87 | /* Bus Scale Settings */ |
| 88 | qcom,gpubw-dev = <&gpubw>; |
| 89 | qcom,bus-control; |
| 90 | qcom,msm-bus,name = "grp3d"; |
| 91 | qcom,bus-width = <32>; |
| 92 | qcom,msm-bus,num-cases = <12>; |
| 93 | qcom,msm-bus,num-paths = <1>; |
| 94 | qcom,msm-bus,vectors-KBps = |
| 95 | <26 512 0 0>, |
| 96 | <26 512 0 400000>, /* 1 bus=100 */ |
| 97 | <26 512 0 800000>, /* 2 bus=200 */ |
| 98 | <26 512 0 1200000>, /* 3 bus=300 */ |
| 99 | <26 512 0 1804000>, /* 4 bus=451 */ |
| 100 | <26 512 0 2188000>, /* 5 bus=547 */ |
| 101 | <26 512 0 2724000>, /* 6 bus=681 */ |
| 102 | <26 512 0 3300000>, /* 7 bus=825 */ |
| 103 | <26 512 0 4068000>, /* 8 bus=1017 */ |
| 104 | <26 512 0 5412000>, /* 9 bus=1353 */ |
| 105 | <26 512 0 6220000>, /* 10 bus=1555 */ |
| 106 | <26 512 0 7216000>; /* 11 bus=1804 */ |
| 107 | |
| 108 | /* GDSC regulator names */ |
| 109 | regulator-names = "vddcx", "vdd"; |
| 110 | /* GDSC oxili regulators */ |
| 111 | vddcx-supply = <&gpu_cx_gdsc>; |
| 112 | vdd-supply = <&gpu_gx_gdsc>; |
| 113 | |
| 114 | /* GPU related llc slices */ |
| 115 | cache-slice-names = "gpu", "gpuhtw"; |
| 116 | cache-slices = <&llcc 12>, <&llcc 11>; |
| 117 | |
Rajesh Kemisetti | 6261ae7 | 2017-09-04 14:17:11 +0530 | [diff] [blame] | 118 | /* CPU latency parameter */ |
| 119 | qcom,pm-qos-active-latency = <660>; |
| 120 | qcom,pm-qos-wakeup-latency = <460>; |
| 121 | |
Rajesh Kemisetti | def2cf7 | 2017-09-04 09:46:15 +0530 | [diff] [blame] | 122 | /* Enable context aware freq. scaling */ |
| 123 | qcom,enable-ca-jump; |
| 124 | /* Context aware jump busy penalty in us */ |
| 125 | qcom,ca-busy-penalty = <12000>; |
| 126 | /* Context aware jump target power level */ |
| 127 | qcom,ca-target-pwrlevel = <1>; |
| 128 | |
Rajesh Kemisetti | ba56c48 | 2017-08-31 18:12:35 +0530 | [diff] [blame] | 129 | /* GPU Mempools */ |
| 130 | qcom,gpu-mempools { |
| 131 | #address-cells = <1>; |
| 132 | #size-cells = <0>; |
| 133 | compatible = "qcom,gpu-mempools"; |
| 134 | |
| 135 | /* 4K Page Pool configuration */ |
| 136 | qcom,gpu-mempool@0 { |
| 137 | reg = <0>; |
| 138 | qcom,mempool-page-size = <4096>; |
| 139 | qcom,mempool-allocate; |
| 140 | }; |
| 141 | /* 8K Page Pool configuration */ |
| 142 | qcom,gpu-mempool@1 { |
| 143 | reg = <1>; |
| 144 | qcom,mempool-page-size = <8192>; |
| 145 | qcom,mempool-allocate; |
| 146 | }; |
| 147 | /* 64K Page Pool configuration */ |
| 148 | qcom,gpu-mempool@2 { |
| 149 | reg = <2>; |
| 150 | qcom,mempool-page-size = <65536>; |
| 151 | qcom,mempool-reserved = <256>; |
| 152 | }; |
| 153 | /* 1M Page Pool configuration */ |
| 154 | qcom,gpu-mempool@3 { |
| 155 | reg = <3>; |
| 156 | qcom,mempool-page-size = <1048576>; |
| 157 | qcom,mempool-reserved = <32>; |
| 158 | }; |
| 159 | }; |
| 160 | |
| 161 | /* Power levels */ |
| 162 | qcom,gpu-pwrlevels { |
| 163 | #address-cells = <1>; |
| 164 | #size-cells = <0>; |
| 165 | |
| 166 | compatible = "qcom,gpu-pwrlevels"; |
| 167 | |
| 168 | /* SVS_L1 */ |
| 169 | qcom,gpu-pwrlevel@0 { |
| 170 | reg = <0>; |
| 171 | qcom,gpu-freq = <430000000>; |
| 172 | qcom,bus-freq = <11>; |
| 173 | qcom,bus-min = <10>; |
| 174 | qcom,bus-max = <11>; |
| 175 | }; |
| 176 | |
| 177 | /* SVS */ |
| 178 | qcom,gpu-pwrlevel@1 { |
| 179 | reg = <1>; |
| 180 | qcom,gpu-freq = <355000000>; |
| 181 | qcom,bus-freq = <9>; |
| 182 | qcom,bus-min = <8>; |
| 183 | qcom,bus-max = <10>; |
| 184 | }; |
| 185 | |
| 186 | /* LOW SVS */ |
| 187 | qcom,gpu-pwrlevel@2 { |
| 188 | reg = <2>; |
| 189 | qcom,gpu-freq = <267000000>; |
| 190 | qcom,bus-freq = <6>; |
| 191 | qcom,bus-min = <4>; |
| 192 | qcom,bus-max = <8>; |
| 193 | }; |
| 194 | |
| 195 | /* MIN SVS */ |
| 196 | qcom,gpu-pwrlevel@3 { |
| 197 | reg = <3>; |
| 198 | qcom,gpu-freq = <180000000>; |
| 199 | qcom,bus-freq = <4>; |
| 200 | qcom,bus-min = <3>; |
| 201 | qcom,bus-max = <5>; |
| 202 | }; |
| 203 | |
| 204 | /* XO */ |
| 205 | qcom,gpu-pwrlevel@4 { |
| 206 | reg = <4>; |
| 207 | qcom,gpu-freq = <0>; |
| 208 | qcom,bus-freq = <0>; |
| 209 | qcom,bus-min = <0>; |
| 210 | qcom,bus-max = <0>; |
| 211 | }; |
| 212 | }; |
| 213 | |
| 214 | }; |
| 215 | |
| 216 | kgsl_msm_iommu: qcom,kgsl-iommu { |
| 217 | compatible = "qcom,kgsl-smmu-v2"; |
| 218 | |
| 219 | reg = <0x05040000 0x10000>; |
| 220 | qcom,protect = <0x40000 0x10000>; |
| 221 | qcom,micro-mmu-control = <0x6000>; |
| 222 | |
| 223 | clocks =<&clock_gcc GCC_GPU_CFG_AHB_CLK>, |
| 224 | <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>, |
| 225 | <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>; |
| 226 | |
| 227 | clock-names = "iface_clk", "mem_clk", "mem_iface_clk"; |
| 228 | |
| 229 | qcom,secure_align_mask = <0xfff>; |
| 230 | qcom,retention; |
| 231 | qcom,hyp_secure_alloc; |
| 232 | |
| 233 | gfx3d_user: gfx3d_user { |
| 234 | compatible = "qcom,smmu-kgsl-cb"; |
| 235 | label = "gfx3d_user"; |
| 236 | iommus = <&kgsl_smmu 0>; |
| 237 | qcom,gpu-offset = <0x48000>; |
| 238 | }; |
| 239 | |
| 240 | gfx3d_secure: gfx3d_secure { |
| 241 | compatible = "qcom,smmu-kgsl-cb"; |
| 242 | iommus = <&kgsl_smmu 2>; |
| 243 | }; |
| 244 | }; |
| 245 | |
| 246 | gmu: qcom,gmu { |
| 247 | label = "kgsl-gmu"; |
| 248 | compatible = "qcom,gpu-gmu"; |
| 249 | |
| 250 | reg = |
| 251 | <0x506a000 0x31000>, |
| 252 | <0xb200000 0x300000>, |
| 253 | <0xc200000 0x10000>; |
| 254 | reg-names = |
| 255 | "kgsl_gmu_reg", |
| 256 | "kgsl_gmu_pdc_reg", |
| 257 | "kgsl_gmu_cpr_reg"; |
| 258 | |
| 259 | interrupts = <0 304 0>, <0 305 0>; |
| 260 | interrupt-names = "kgsl_hfi_irq", "kgsl_gmu_irq"; |
| 261 | |
| 262 | qcom,msm-bus,name = "cnoc"; |
| 263 | qcom,msm-bus,num-cases = <2>; |
| 264 | qcom,msm-bus,num-paths = <1>; |
| 265 | qcom,msm-bus,vectors-KBps = |
| 266 | <26 10036 0 0>, /* CNOC off */ |
| 267 | <26 10036 0 100>; /* CNOC on */ |
| 268 | |
| 269 | regulator-names = "vddcx", "vdd"; |
| 270 | vddcx-supply = <&gpu_cx_gdsc>; |
| 271 | vdd-supply = <&gpu_gx_gdsc>; |
| 272 | |
| 273 | |
| 274 | clocks = <&clock_gpucc GPU_CC_CX_GMU_CLK>, |
| 275 | <&clock_gpucc GPU_CC_CXO_CLK>, |
| 276 | <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>, |
| 277 | <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, |
| 278 | <&clock_gpucc GPU_CC_AHB_CLK>; |
| 279 | |
| 280 | clock-names = "gmu_clk", "cxo_clk", "axi_clk", |
| 281 | "memnoc_clk", "ahb_clk"; |
| 282 | |
| 283 | qcom,gmu-pwrlevels { |
| 284 | #address-cells = <1>; |
| 285 | #size-cells = <0>; |
| 286 | |
| 287 | compatible = "qcom,gmu-pwrlevels"; |
| 288 | |
| 289 | qcom,gmu-pwrlevel@0 { |
| 290 | reg = <0>; |
| 291 | qcom,gmu-freq = <200000000>; |
| 292 | }; |
| 293 | |
| 294 | qcom,gmu-pwrlevel@1 { |
| 295 | reg = <1>; |
| 296 | qcom,gmu-freq = <0>; |
| 297 | }; |
| 298 | }; |
| 299 | |
| 300 | gmu_user: gmu_user { |
| 301 | compatible = "qcom,smmu-gmu-user-cb"; |
| 302 | iommus = <&kgsl_smmu 4>; |
| 303 | }; |
| 304 | |
| 305 | gmu_kernel: gmu_kernel { |
| 306 | compatible = "qcom,smmu-gmu-kernel-cb"; |
| 307 | iommus = <&kgsl_smmu 5>; |
| 308 | }; |
| 309 | }; |
| 310 | }; |