Michal Simek | 5d1b79d | 2015-03-09 09:41:04 +0100 | [diff] [blame] | 1 | /* |
| 2 | * dts file for Xilinx ZynqMP |
| 3 | * |
| 4 | * (C) Copyright 2014 - 2015, Xilinx, Inc. |
| 5 | * |
| 6 | * Michal Simek <michal.simek@xilinx.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | */ |
| 13 | |
| 14 | / { |
| 15 | compatible = "xlnx,zynqmp"; |
| 16 | #address-cells = <2>; |
Michal Simek | 7393fd8 | 2016-02-11 13:26:28 +0100 | [diff] [blame] | 17 | #size-cells = <2>; |
Michal Simek | 5d1b79d | 2015-03-09 09:41:04 +0100 | [diff] [blame] | 18 | |
| 19 | cpus { |
| 20 | #address-cells = <1>; |
| 21 | #size-cells = <0>; |
| 22 | |
| 23 | cpu@0 { |
| 24 | compatible = "arm,cortex-a53", "arm,armv8"; |
| 25 | device_type = "cpu"; |
| 26 | enable-method = "psci"; |
| 27 | reg = <0x0>; |
| 28 | }; |
| 29 | |
| 30 | cpu@1 { |
| 31 | compatible = "arm,cortex-a53", "arm,armv8"; |
| 32 | device_type = "cpu"; |
| 33 | enable-method = "psci"; |
| 34 | reg = <0x1>; |
| 35 | }; |
| 36 | |
| 37 | cpu@2 { |
| 38 | compatible = "arm,cortex-a53", "arm,armv8"; |
| 39 | device_type = "cpu"; |
| 40 | enable-method = "psci"; |
| 41 | reg = <0x2>; |
| 42 | }; |
| 43 | |
| 44 | cpu@3 { |
| 45 | compatible = "arm,cortex-a53", "arm,armv8"; |
| 46 | device_type = "cpu"; |
| 47 | enable-method = "psci"; |
| 48 | reg = <0x3>; |
| 49 | }; |
| 50 | }; |
| 51 | |
| 52 | pmu { |
| 53 | compatible = "arm,armv8-pmuv3"; |
Michal Simek | 886e7dd | 2016-02-02 13:10:25 +0100 | [diff] [blame] | 54 | interrupt-parent = <&gic>; |
Michal Simek | 5d1b79d | 2015-03-09 09:41:04 +0100 | [diff] [blame] | 55 | interrupts = <0 143 4>, |
| 56 | <0 144 4>, |
| 57 | <0 145 4>, |
| 58 | <0 146 4>; |
| 59 | }; |
| 60 | |
| 61 | psci { |
| 62 | compatible = "arm,psci-0.2"; |
| 63 | method = "smc"; |
| 64 | }; |
| 65 | |
| 66 | timer { |
| 67 | compatible = "arm,armv8-timer"; |
| 68 | interrupt-parent = <&gic>; |
Marc Zyngier | f2a89d3 | 2016-08-01 10:54:16 +0100 | [diff] [blame] | 69 | interrupts = <1 13 0xf08>, |
| 70 | <1 14 0xf08>, |
| 71 | <1 11 0xf08>, |
| 72 | <1 10 0xf08>; |
Michal Simek | 5d1b79d | 2015-03-09 09:41:04 +0100 | [diff] [blame] | 73 | }; |
| 74 | |
Michal Simek | e360353 | 2016-11-15 14:53:13 +0100 | [diff] [blame] | 75 | amba_apu: amba_apu@0 { |
Michal Simek | 5d1b79d | 2015-03-09 09:41:04 +0100 | [diff] [blame] | 76 | compatible = "simple-bus"; |
| 77 | #address-cells = <2>; |
| 78 | #size-cells = <1>; |
Michal Simek | 7393fd8 | 2016-02-11 13:26:28 +0100 | [diff] [blame] | 79 | ranges = <0 0 0 0 0xffffffff>; |
Michal Simek | 5d1b79d | 2015-03-09 09:41:04 +0100 | [diff] [blame] | 80 | |
| 81 | gic: interrupt-controller@f9010000 { |
| 82 | compatible = "arm,gic-400", "arm,cortex-a15-gic"; |
| 83 | #interrupt-cells = <3>; |
| 84 | reg = <0x0 0xf9010000 0x10000>, |
Alexander Graf | e753dc0 | 2016-05-12 13:44:01 +0200 | [diff] [blame] | 85 | <0x0 0xf9020000 0x20000>, |
Michal Simek | 5d1b79d | 2015-03-09 09:41:04 +0100 | [diff] [blame] | 86 | <0x0 0xf9040000 0x20000>, |
Alexander Graf | e753dc0 | 2016-05-12 13:44:01 +0200 | [diff] [blame] | 87 | <0x0 0xf9060000 0x20000>; |
Michal Simek | 5d1b79d | 2015-03-09 09:41:04 +0100 | [diff] [blame] | 88 | interrupt-controller; |
| 89 | interrupt-parent = <&gic>; |
| 90 | interrupts = <1 9 0xf04>; |
| 91 | }; |
| 92 | }; |
| 93 | |
Michal Simek | 5087bcc | 2015-10-20 16:36:33 +0200 | [diff] [blame] | 94 | amba: amba { |
Michal Simek | 5d1b79d | 2015-03-09 09:41:04 +0100 | [diff] [blame] | 95 | compatible = "simple-bus"; |
| 96 | #address-cells = <2>; |
Michal Simek | 7393fd8 | 2016-02-11 13:26:28 +0100 | [diff] [blame] | 97 | #size-cells = <2>; |
Michal Simek | 5d1b79d | 2015-03-09 09:41:04 +0100 | [diff] [blame] | 98 | ranges; |
| 99 | |
Michal Simek | 3a8691f | 2015-07-27 11:15:38 +0200 | [diff] [blame] | 100 | can0: can@ff060000 { |
| 101 | compatible = "xlnx,zynq-can-1.0"; |
| 102 | status = "disabled"; |
Michal Simek | 3a8691f | 2015-07-27 11:15:38 +0200 | [diff] [blame] | 103 | clock-names = "can_clk", "pclk"; |
Michal Simek | 7393fd8 | 2016-02-11 13:26:28 +0100 | [diff] [blame] | 104 | reg = <0x0 0xff060000 0x0 0x1000>; |
Michal Simek | 3a8691f | 2015-07-27 11:15:38 +0200 | [diff] [blame] | 105 | interrupts = <0 23 4>; |
| 106 | interrupt-parent = <&gic>; |
| 107 | tx-fifo-depth = <0x40>; |
| 108 | rx-fifo-depth = <0x40>; |
| 109 | }; |
| 110 | |
| 111 | can1: can@ff070000 { |
| 112 | compatible = "xlnx,zynq-can-1.0"; |
| 113 | status = "disabled"; |
Michal Simek | 3a8691f | 2015-07-27 11:15:38 +0200 | [diff] [blame] | 114 | clock-names = "can_clk", "pclk"; |
Michal Simek | 7393fd8 | 2016-02-11 13:26:28 +0100 | [diff] [blame] | 115 | reg = <0x0 0xff070000 0x0 0x1000>; |
Michal Simek | 3a8691f | 2015-07-27 11:15:38 +0200 | [diff] [blame] | 116 | interrupts = <0 24 4>; |
| 117 | interrupt-parent = <&gic>; |
| 118 | tx-fifo-depth = <0x40>; |
| 119 | rx-fifo-depth = <0x40>; |
| 120 | }; |
| 121 | |
Michal Simek | 5d1b79d | 2015-03-09 09:41:04 +0100 | [diff] [blame] | 122 | gem0: ethernet@ff0b0000 { |
| 123 | compatible = "cdns,gem"; |
| 124 | status = "disabled"; |
| 125 | interrupt-parent = <&gic>; |
| 126 | interrupts = <0 57 4>, <0 57 4>; |
Michal Simek | 7393fd8 | 2016-02-11 13:26:28 +0100 | [diff] [blame] | 127 | reg = <0x0 0xff0b0000 0x0 0x1000>; |
Michal Simek | 5d1b79d | 2015-03-09 09:41:04 +0100 | [diff] [blame] | 128 | clock-names = "pclk", "hclk", "tx_clk"; |
Michal Simek | 5d1b79d | 2015-03-09 09:41:04 +0100 | [diff] [blame] | 129 | #address-cells = <1>; |
| 130 | #size-cells = <0>; |
| 131 | }; |
| 132 | |
| 133 | gem1: ethernet@ff0c0000 { |
| 134 | compatible = "cdns,gem"; |
| 135 | status = "disabled"; |
| 136 | interrupt-parent = <&gic>; |
| 137 | interrupts = <0 59 4>, <0 59 4>; |
Michal Simek | 7393fd8 | 2016-02-11 13:26:28 +0100 | [diff] [blame] | 138 | reg = <0x0 0xff0c0000 0x0 0x1000>; |
Michal Simek | 5d1b79d | 2015-03-09 09:41:04 +0100 | [diff] [blame] | 139 | clock-names = "pclk", "hclk", "tx_clk"; |
Michal Simek | 5d1b79d | 2015-03-09 09:41:04 +0100 | [diff] [blame] | 140 | #address-cells = <1>; |
| 141 | #size-cells = <0>; |
| 142 | }; |
| 143 | |
| 144 | gem2: ethernet@ff0d0000 { |
| 145 | compatible = "cdns,gem"; |
| 146 | status = "disabled"; |
| 147 | interrupt-parent = <&gic>; |
| 148 | interrupts = <0 61 4>, <0 61 4>; |
Michal Simek | 7393fd8 | 2016-02-11 13:26:28 +0100 | [diff] [blame] | 149 | reg = <0x0 0xff0d0000 0x0 0x1000>; |
Michal Simek | 5d1b79d | 2015-03-09 09:41:04 +0100 | [diff] [blame] | 150 | clock-names = "pclk", "hclk", "tx_clk"; |
Michal Simek | 5d1b79d | 2015-03-09 09:41:04 +0100 | [diff] [blame] | 151 | #address-cells = <1>; |
| 152 | #size-cells = <0>; |
| 153 | }; |
| 154 | |
| 155 | gem3: ethernet@ff0e0000 { |
| 156 | compatible = "cdns,gem"; |
| 157 | status = "disabled"; |
| 158 | interrupt-parent = <&gic>; |
| 159 | interrupts = <0 63 4>, <0 63 4>; |
Michal Simek | 7393fd8 | 2016-02-11 13:26:28 +0100 | [diff] [blame] | 160 | reg = <0x0 0xff0e0000 0x0 0x1000>; |
Michal Simek | 5d1b79d | 2015-03-09 09:41:04 +0100 | [diff] [blame] | 161 | clock-names = "pclk", "hclk", "tx_clk"; |
Michal Simek | 5d1b79d | 2015-03-09 09:41:04 +0100 | [diff] [blame] | 162 | #address-cells = <1>; |
| 163 | #size-cells = <0>; |
| 164 | }; |
| 165 | |
Michal Simek | 72e5df4 | 2016-02-11 13:08:44 +0100 | [diff] [blame] | 166 | gpio: gpio@ff0a0000 { |
| 167 | compatible = "xlnx,zynqmp-gpio-1.0"; |
| 168 | status = "disabled"; |
| 169 | #gpio-cells = <0x2>; |
Michal Simek | 72e5df4 | 2016-02-11 13:08:44 +0100 | [diff] [blame] | 170 | interrupt-parent = <&gic>; |
| 171 | interrupts = <0 16 4>; |
| 172 | interrupt-controller; |
| 173 | #interrupt-cells = <2>; |
Michal Simek | 7393fd8 | 2016-02-11 13:26:28 +0100 | [diff] [blame] | 174 | reg = <0x0 0xff0a0000 0x0 0x1000>; |
Michal Simek | 72e5df4 | 2016-02-11 13:08:44 +0100 | [diff] [blame] | 175 | }; |
| 176 | |
Michal Simek | 5d1b79d | 2015-03-09 09:41:04 +0100 | [diff] [blame] | 177 | i2c0: i2c@ff020000 { |
Moritz Fischer | 3209f3f | 2016-12-22 09:19:25 -0800 | [diff] [blame] | 178 | compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; |
Michal Simek | 5d1b79d | 2015-03-09 09:41:04 +0100 | [diff] [blame] | 179 | status = "disabled"; |
| 180 | interrupt-parent = <&gic>; |
| 181 | interrupts = <0 17 4>; |
Michal Simek | 7393fd8 | 2016-02-11 13:26:28 +0100 | [diff] [blame] | 182 | reg = <0x0 0xff020000 0x0 0x1000>; |
Michal Simek | 5d1b79d | 2015-03-09 09:41:04 +0100 | [diff] [blame] | 183 | #address-cells = <1>; |
| 184 | #size-cells = <0>; |
| 185 | }; |
| 186 | |
| 187 | i2c1: i2c@ff030000 { |
Moritz Fischer | 3209f3f | 2016-12-22 09:19:25 -0800 | [diff] [blame] | 188 | compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; |
Michal Simek | 5d1b79d | 2015-03-09 09:41:04 +0100 | [diff] [blame] | 189 | status = "disabled"; |
| 190 | interrupt-parent = <&gic>; |
| 191 | interrupts = <0 18 4>; |
Michal Simek | 7393fd8 | 2016-02-11 13:26:28 +0100 | [diff] [blame] | 192 | reg = <0x0 0xff030000 0x0 0x1000>; |
Michal Simek | 5d1b79d | 2015-03-09 09:41:04 +0100 | [diff] [blame] | 193 | #address-cells = <1>; |
| 194 | #size-cells = <0>; |
| 195 | }; |
| 196 | |
Michal Simek | 78b83b8 | 2016-08-09 15:13:02 +0200 | [diff] [blame] | 197 | pcie: pcie@fd0e0000 { |
| 198 | compatible = "xlnx,nwl-pcie-2.11"; |
| 199 | status = "disabled"; |
| 200 | #address-cells = <3>; |
| 201 | #size-cells = <2>; |
| 202 | #interrupt-cells = <1>; |
| 203 | msi-controller; |
| 204 | device_type = "pci"; |
| 205 | interrupt-parent = <&gic>; |
| 206 | interrupts = <0 118 4>, |
| 207 | <0 117 4>, |
| 208 | <0 116 4>, |
| 209 | <0 115 4>, /* MSI_1 [63...32] */ |
| 210 | <0 114 4>; /* MSI_0 [31...0] */ |
| 211 | interrupt-names = "misc", "dummy", "intx", |
| 212 | "msi1", "msi0"; |
| 213 | msi-parent = <&pcie>; |
| 214 | reg = <0x0 0xfd0e0000 0x0 0x1000>, |
| 215 | <0x0 0xfd480000 0x0 0x1000>, |
| 216 | <0x80 0x00000000 0x0 0x1000000>; |
| 217 | reg-names = "breg", "pcireg", "cfg"; |
| 218 | ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 |
| 219 | 0xe0000000 0x00000000 0x10000000 |
| 220 | /* non-prefetchable memory */ |
| 221 | 0x43000000 0x00000006 0x00000000 0x00000006 |
| 222 | 0x00000000 0x00000002 0x00000000>; |
| 223 | /* prefetchable memory */ |
| 224 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; |
| 225 | interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, |
| 226 | <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, |
| 227 | <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, |
| 228 | <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; |
| 229 | pcie_intc: legacy-interrupt-controller { |
| 230 | interrupt-controller; |
| 231 | #address-cells = <0>; |
| 232 | #interrupt-cells = <1>; |
| 233 | }; |
| 234 | }; |
| 235 | |
Suneel Garapati | 8fae442 | 2015-06-10 15:46:56 +0530 | [diff] [blame] | 236 | sata: ahci@fd0c0000 { |
| 237 | compatible = "ceva,ahci-1v84"; |
| 238 | status = "disabled"; |
Michal Simek | 7393fd8 | 2016-02-11 13:26:28 +0100 | [diff] [blame] | 239 | reg = <0x0 0xfd0c0000 0x0 0x2000>; |
Suneel Garapati | 8fae442 | 2015-06-10 15:46:56 +0530 | [diff] [blame] | 240 | interrupt-parent = <&gic>; |
| 241 | interrupts = <0 133 4>; |
Suneel Garapati | 8fae442 | 2015-06-10 15:46:56 +0530 | [diff] [blame] | 242 | }; |
| 243 | |
Michal Simek | 5d1b79d | 2015-03-09 09:41:04 +0100 | [diff] [blame] | 244 | sdhci0: sdhci@ff160000 { |
| 245 | compatible = "arasan,sdhci-8.9a"; |
| 246 | status = "disabled"; |
| 247 | interrupt-parent = <&gic>; |
| 248 | interrupts = <0 48 4>; |
Michal Simek | 7393fd8 | 2016-02-11 13:26:28 +0100 | [diff] [blame] | 249 | reg = <0x0 0xff160000 0x0 0x1000>; |
Michal Simek | 5d1b79d | 2015-03-09 09:41:04 +0100 | [diff] [blame] | 250 | clock-names = "clk_xin", "clk_ahb"; |
Michal Simek | 5d1b79d | 2015-03-09 09:41:04 +0100 | [diff] [blame] | 251 | }; |
| 252 | |
| 253 | sdhci1: sdhci@ff170000 { |
| 254 | compatible = "arasan,sdhci-8.9a"; |
| 255 | status = "disabled"; |
| 256 | interrupt-parent = <&gic>; |
| 257 | interrupts = <0 49 4>; |
Michal Simek | 7393fd8 | 2016-02-11 13:26:28 +0100 | [diff] [blame] | 258 | reg = <0x0 0xff170000 0x0 0x1000>; |
Michal Simek | 5d1b79d | 2015-03-09 09:41:04 +0100 | [diff] [blame] | 259 | clock-names = "clk_xin", "clk_ahb"; |
Michal Simek | 5d1b79d | 2015-03-09 09:41:04 +0100 | [diff] [blame] | 260 | }; |
| 261 | |
Michal Simek | ff92e36 | 2015-07-27 11:18:04 +0200 | [diff] [blame] | 262 | smmu: smmu@fd800000 { |
| 263 | compatible = "arm,mmu-500"; |
Michal Simek | 7393fd8 | 2016-02-11 13:26:28 +0100 | [diff] [blame] | 264 | reg = <0x0 0xfd800000 0x0 0x20000>; |
Michal Simek | ff92e36 | 2015-07-27 11:18:04 +0200 | [diff] [blame] | 265 | #global-interrupts = <1>; |
| 266 | interrupt-parent = <&gic>; |
| 267 | interrupts = <0 157 4>, |
| 268 | <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, |
| 269 | <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, |
| 270 | <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, |
| 271 | <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>; |
| 272 | }; |
| 273 | |
Michal Simek | f49310d | 2015-07-27 16:13:34 +0200 | [diff] [blame] | 274 | spi0: spi@ff040000 { |
| 275 | compatible = "cdns,spi-r1p6"; |
| 276 | status = "disabled"; |
| 277 | interrupt-parent = <&gic>; |
| 278 | interrupts = <0 19 4>; |
Michal Simek | 7393fd8 | 2016-02-11 13:26:28 +0100 | [diff] [blame] | 279 | reg = <0x0 0xff040000 0x0 0x1000>; |
Michal Simek | f49310d | 2015-07-27 16:13:34 +0200 | [diff] [blame] | 280 | clock-names = "ref_clk", "pclk"; |
Michal Simek | f49310d | 2015-07-27 16:13:34 +0200 | [diff] [blame] | 281 | #address-cells = <1>; |
| 282 | #size-cells = <0>; |
| 283 | }; |
| 284 | |
| 285 | spi1: spi@ff050000 { |
| 286 | compatible = "cdns,spi-r1p6"; |
| 287 | status = "disabled"; |
| 288 | interrupt-parent = <&gic>; |
| 289 | interrupts = <0 20 4>; |
Michal Simek | 7393fd8 | 2016-02-11 13:26:28 +0100 | [diff] [blame] | 290 | reg = <0x0 0xff050000 0x0 0x1000>; |
Michal Simek | f49310d | 2015-07-27 16:13:34 +0200 | [diff] [blame] | 291 | clock-names = "ref_clk", "pclk"; |
Michal Simek | f49310d | 2015-07-27 16:13:34 +0200 | [diff] [blame] | 292 | #address-cells = <1>; |
| 293 | #size-cells = <0>; |
| 294 | }; |
| 295 | |
Michal Simek | 8fd7a77 | 2015-07-27 16:09:29 +0200 | [diff] [blame] | 296 | ttc0: timer@ff110000 { |
| 297 | compatible = "cdns,ttc"; |
| 298 | status = "disabled"; |
| 299 | interrupt-parent = <&gic>; |
| 300 | interrupts = <0 36 4>, <0 37 4>, <0 38 4>; |
Michal Simek | 7393fd8 | 2016-02-11 13:26:28 +0100 | [diff] [blame] | 301 | reg = <0x0 0xff110000 0x0 0x1000>; |
Michal Simek | 8fd7a77 | 2015-07-27 16:09:29 +0200 | [diff] [blame] | 302 | timer-width = <32>; |
| 303 | }; |
| 304 | |
| 305 | ttc1: timer@ff120000 { |
| 306 | compatible = "cdns,ttc"; |
| 307 | status = "disabled"; |
| 308 | interrupt-parent = <&gic>; |
| 309 | interrupts = <0 39 4>, <0 40 4>, <0 41 4>; |
Michal Simek | 7393fd8 | 2016-02-11 13:26:28 +0100 | [diff] [blame] | 310 | reg = <0x0 0xff120000 0x0 0x1000>; |
Michal Simek | 8fd7a77 | 2015-07-27 16:09:29 +0200 | [diff] [blame] | 311 | timer-width = <32>; |
| 312 | }; |
| 313 | |
| 314 | ttc2: timer@ff130000 { |
| 315 | compatible = "cdns,ttc"; |
| 316 | status = "disabled"; |
| 317 | interrupt-parent = <&gic>; |
| 318 | interrupts = <0 42 4>, <0 43 4>, <0 44 4>; |
Michal Simek | 7393fd8 | 2016-02-11 13:26:28 +0100 | [diff] [blame] | 319 | reg = <0x0 0xff130000 0x0 0x1000>; |
Michal Simek | 8fd7a77 | 2015-07-27 16:09:29 +0200 | [diff] [blame] | 320 | timer-width = <32>; |
| 321 | }; |
| 322 | |
| 323 | ttc3: timer@ff140000 { |
| 324 | compatible = "cdns,ttc"; |
| 325 | status = "disabled"; |
| 326 | interrupt-parent = <&gic>; |
| 327 | interrupts = <0 45 4>, <0 46 4>, <0 47 4>; |
Michal Simek | 7393fd8 | 2016-02-11 13:26:28 +0100 | [diff] [blame] | 328 | reg = <0x0 0xff140000 0x0 0x1000>; |
Michal Simek | 8fd7a77 | 2015-07-27 16:09:29 +0200 | [diff] [blame] | 329 | timer-width = <32>; |
| 330 | }; |
| 331 | |
| 332 | uart0: serial@ff000000 { |
| 333 | compatible = "cdns,uart-r1p8"; |
| 334 | status = "disabled"; |
| 335 | interrupt-parent = <&gic>; |
| 336 | interrupts = <0 21 4>; |
Michal Simek | 7393fd8 | 2016-02-11 13:26:28 +0100 | [diff] [blame] | 337 | reg = <0x0 0xff000000 0x0 0x1000>; |
Michal Simek | 8fd7a77 | 2015-07-27 16:09:29 +0200 | [diff] [blame] | 338 | clock-names = "uart_clk", "pclk"; |
Michal Simek | 8fd7a77 | 2015-07-27 16:09:29 +0200 | [diff] [blame] | 339 | }; |
| 340 | |
| 341 | uart1: serial@ff010000 { |
| 342 | compatible = "cdns,uart-r1p8"; |
| 343 | status = "disabled"; |
| 344 | interrupt-parent = <&gic>; |
| 345 | interrupts = <0 22 4>; |
Michal Simek | 7393fd8 | 2016-02-11 13:26:28 +0100 | [diff] [blame] | 346 | reg = <0x0 0xff010000 0x0 0x1000>; |
Michal Simek | 8fd7a77 | 2015-07-27 16:09:29 +0200 | [diff] [blame] | 347 | clock-names = "uart_clk", "pclk"; |
Michal Simek | 8fd7a77 | 2015-07-27 16:09:29 +0200 | [diff] [blame] | 348 | }; |
| 349 | |
Michal Simek | 22eda14 | 2015-07-27 11:21:20 +0200 | [diff] [blame] | 350 | usb0: usb@fe200000 { |
| 351 | compatible = "snps,dwc3"; |
| 352 | status = "disabled"; |
| 353 | interrupt-parent = <&gic>; |
| 354 | interrupts = <0 65 4>; |
Michal Simek | 7393fd8 | 2016-02-11 13:26:28 +0100 | [diff] [blame] | 355 | reg = <0x0 0xfe200000 0x0 0x40000>; |
Michal Simek | 22eda14 | 2015-07-27 11:21:20 +0200 | [diff] [blame] | 356 | clock-names = "clk_xin", "clk_ahb"; |
Michal Simek | 22eda14 | 2015-07-27 11:21:20 +0200 | [diff] [blame] | 357 | }; |
| 358 | |
| 359 | usb1: usb@fe300000 { |
| 360 | compatible = "snps,dwc3"; |
| 361 | status = "disabled"; |
| 362 | interrupt-parent = <&gic>; |
| 363 | interrupts = <0 70 4>; |
Michal Simek | 7393fd8 | 2016-02-11 13:26:28 +0100 | [diff] [blame] | 364 | reg = <0x0 0xfe300000 0x0 0x40000>; |
Michal Simek | 22eda14 | 2015-07-27 11:21:20 +0200 | [diff] [blame] | 365 | clock-names = "clk_xin", "clk_ahb"; |
Michal Simek | 22eda14 | 2015-07-27 11:21:20 +0200 | [diff] [blame] | 366 | }; |
| 367 | |
Michal Simek | 5d1b79d | 2015-03-09 09:41:04 +0100 | [diff] [blame] | 368 | watchdog0: watchdog@fd4d0000 { |
| 369 | compatible = "cdns,wdt-r1p2"; |
| 370 | status = "disabled"; |
Michal Simek | 5d1b79d | 2015-03-09 09:41:04 +0100 | [diff] [blame] | 371 | interrupt-parent = <&gic>; |
Punnaiah Choudary Kalluri | 908c9e7 | 2015-11-04 12:34:17 +0530 | [diff] [blame] | 372 | interrupts = <0 113 1>; |
Michal Simek | 7393fd8 | 2016-02-11 13:26:28 +0100 | [diff] [blame] | 373 | reg = <0x0 0xfd4d0000 0x0 0x1000>; |
Michal Simek | 5d1b79d | 2015-03-09 09:41:04 +0100 | [diff] [blame] | 374 | timeout-sec = <10>; |
| 375 | }; |
| 376 | }; |
| 377 | }; |