Satyajit Desai | 66b6c45 | 2017-06-27 17:10:46 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2014-2017, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/module.h> |
| 15 | #include <linux/clk.h> |
| 16 | #include <linux/delay.h> |
| 17 | #include <linux/init.h> |
| 18 | #include <linux/types.h> |
| 19 | #include <linux/err.h> |
| 20 | #include <linux/slab.h> |
| 21 | #include <linux/smp.h> |
| 22 | #include <linux/export.h> |
| 23 | #include <linux/printk.h> |
| 24 | #include <linux/ratelimit.h> |
| 25 | #include <linux/coresight.h> |
| 26 | #include <linux/io.h> |
| 27 | #include <linux/platform_device.h> |
| 28 | #include <linux/bitops.h> |
| 29 | #include <linux/of.h> |
| 30 | #include <linux/notifier.h> |
| 31 | #include <linux/cpu.h> |
| 32 | #include <linux/spinlock.h> |
| 33 | #include <linux/mutex.h> |
| 34 | #include <soc/qcom/scm.h> |
| 35 | #include <soc/qcom/jtag.h> |
| 36 | #include <asm/smp_plat.h> |
| 37 | #include <asm/etmv4x.h> |
| 38 | #include <soc/qcom/socinfo.h> |
| 39 | |
| 40 | #define CORESIGHT_LAR (0xFB0) |
| 41 | |
| 42 | #define TIMEOUT_US (100) |
| 43 | |
| 44 | #define BM(lsb, msb) ((BIT(msb) - BIT(lsb)) + BIT(msb)) |
| 45 | #define BMVAL(val, lsb, msb) ((val & BM(lsb, msb)) >> lsb) |
| 46 | #define BVAL(val, n) ((val & BIT(n)) >> n) |
| 47 | |
| 48 | /* |
| 49 | * ETMv4 registers: |
| 50 | * 0x000 - 0x2FC: Trace registers |
| 51 | * 0x300 - 0x314: Management registers |
| 52 | * 0x318 - 0xEFC: Trace registers |
| 53 | * 0xF00: Management registers |
| 54 | * 0xFA0 - 0xFA4: Trace registers |
| 55 | * 0xFA8 - 0xFFC: Management registers |
| 56 | */ |
| 57 | |
| 58 | /* Trace registers (0x000-0x2FC) */ |
| 59 | /* Main control and configuration registers */ |
| 60 | #define TRCPRGCTLR (0x004) |
| 61 | #define TRCPROCSELR (0x008) |
| 62 | #define TRCSTATR (0x00C) |
| 63 | #define TRCCONFIGR (0x010) |
| 64 | #define TRCAUXCTLR (0x018) |
| 65 | #define TRCEVENTCTL0R (0x020) |
| 66 | #define TRCEVENTCTL1R (0x024) |
| 67 | #define TRCSTALLCTLR (0x02C) |
| 68 | #define TRCTSCTLR (0x030) |
| 69 | #define TRCSYNCPR (0x034) |
| 70 | #define TRCCCCTLR (0x038) |
| 71 | #define TRCBBCTLR (0x03C) |
| 72 | #define TRCTRACEIDR (0x040) |
| 73 | #define TRCQCTLR (0x044) |
| 74 | /* Filtering control registers */ |
| 75 | #define TRCVICTLR (0x080) |
| 76 | #define TRCVIIECTLR (0x084) |
| 77 | #define TRCVISSCTLR (0x088) |
| 78 | #define TRCVIPCSSCTLR (0x08C) |
| 79 | #define TRCVDCTLR (0x0A0) |
| 80 | #define TRCVDSACCTLR (0x0A4) |
| 81 | #define TRCVDARCCTLR (0x0A8) |
| 82 | /* Derived resources registers */ |
| 83 | #define TRCSEQEVRn(n) (0x100 + (n * 4)) |
| 84 | #define TRCSEQRSTEVR (0x118) |
| 85 | #define TRCSEQSTR (0x11C) |
| 86 | #define TRCEXTINSELR (0x120) |
| 87 | #define TRCCNTRLDVRn(n) (0x140 + (n * 4)) |
| 88 | #define TRCCNTCTLRn(n) (0x150 + (n * 4)) |
| 89 | #define TRCCNTVRn(n) (0x160 + (n * 4)) |
| 90 | /* ID registers */ |
| 91 | #define TRCIDR8 (0x180) |
| 92 | #define TRCIDR9 (0x184) |
| 93 | #define TRCIDR10 (0x188) |
| 94 | #define TRCIDR11 (0x18C) |
| 95 | #define TRCIDR12 (0x190) |
| 96 | #define TRCIDR13 (0x194) |
| 97 | #define TRCIMSPEC0 (0x1C0) |
| 98 | #define TRCIMSPECn(n) (0x1C0 + (n * 4)) |
| 99 | #define TRCIDR0 (0x1E0) |
| 100 | #define TRCIDR1 (0x1E4) |
| 101 | #define TRCIDR2 (0x1E8) |
| 102 | #define TRCIDR3 (0x1EC) |
| 103 | #define TRCIDR4 (0x1F0) |
| 104 | #define TRCIDR5 (0x1F4) |
| 105 | #define TRCIDR6 (0x1F8) |
| 106 | #define TRCIDR7 (0x1FC) |
| 107 | /* Resource selection registers */ |
| 108 | #define TRCRSCTLRn(n) (0x200 + (n * 4)) |
| 109 | /* Single-shot comparator registers */ |
| 110 | #define TRCSSCCRn(n) (0x280 + (n * 4)) |
| 111 | #define TRCSSCSRn(n) (0x2A0 + (n * 4)) |
| 112 | #define TRCSSPCICRn(n) (0x2C0 + (n * 4)) |
| 113 | /* Management registers (0x300-0x314) */ |
| 114 | #define TRCOSLAR (0x300) |
| 115 | #define TRCOSLSR (0x304) |
| 116 | #define TRCPDCR (0x310) |
| 117 | #define TRCPDSR (0x314) |
| 118 | /* Trace registers (0x318-0xEFC) */ |
| 119 | /* Comparator registers */ |
| 120 | #define TRCACVRn(n) (0x400 + (n * 8)) |
| 121 | #define TRCACATRn(n) (0x480 + (n * 8)) |
| 122 | #define TRCDVCVRn(n) (0x500 + (n * 16)) |
| 123 | #define TRCDVCMRn(n) (0x580 + (n * 16)) |
| 124 | #define TRCCIDCVRn(n) (0x600 + (n * 8)) |
| 125 | #define TRCVMIDCVRn(n) (0x640 + (n * 8)) |
| 126 | #define TRCCIDCCTLR0 (0x680) |
| 127 | #define TRCCIDCCTLR1 (0x684) |
| 128 | #define TRCVMIDCCTLR0 (0x688) |
| 129 | #define TRCVMIDCCTLR1 (0x68C) |
| 130 | /* Management register (0xF00) */ |
| 131 | /* Integration control registers */ |
| 132 | #define TRCITCTRL (0xF00) |
| 133 | /* Trace registers (0xFA0-0xFA4) */ |
| 134 | /* Claim tag registers */ |
| 135 | #define TRCCLAIMSET (0xFA0) |
| 136 | #define TRCCLAIMCLR (0xFA4) |
| 137 | /* Management registers (0xFA8-0xFFC) */ |
| 138 | #define TRCDEVAFF0 (0xFA8) |
| 139 | #define TRCDEVAFF1 (0xFAC) |
| 140 | #define TRCLAR (0xFB0) |
| 141 | #define TRCLSR (0xFB4) |
| 142 | #define TRCAUTHSTATUS (0xFB8) |
| 143 | #define TRCDEVARCH (0xFBC) |
| 144 | #define TRCDEVID (0xFC8) |
| 145 | #define TRCDEVTYPE (0xFCC) |
| 146 | #define TRCPIDR4 (0xFD0) |
| 147 | #define TRCPIDR5 (0xFD4) |
| 148 | #define TRCPIDR6 (0xFD8) |
| 149 | #define TRCPIDR7 (0xFDC) |
| 150 | #define TRCPIDR0 (0xFE0) |
| 151 | #define TRCPIDR1 (0xFE4) |
| 152 | #define TRCPIDR2 (0xFE8) |
| 153 | #define TRCPIDR3 (0xFEC) |
| 154 | #define TRCCIDR0 (0xFF0) |
| 155 | #define TRCCIDR1 (0xFF4) |
| 156 | #define TRCCIDR2 (0xFF8) |
| 157 | #define TRCCIDR3 (0xFFC) |
| 158 | |
| 159 | /* ETMv4 resources */ |
| 160 | #define ETM_MAX_NR_PE (8) |
| 161 | #define ETM_MAX_CNTR (4) |
| 162 | #define ETM_MAX_SEQ_STATES (4) |
| 163 | #define ETM_MAX_EXT_INP_SEL (4) |
| 164 | #define ETM_MAX_EXT_INP (256) |
| 165 | #define ETM_MAX_EXT_OUT (4) |
| 166 | #define ETM_MAX_SINGLE_ADDR_CMP (16) |
| 167 | #define ETM_MAX_ADDR_RANGE_CMP (ETM_MAX_SINGLE_ADDR_CMP / 2) |
| 168 | #define ETM_MAX_DATA_VAL_CMP (8) |
| 169 | #define ETM_MAX_CTXID_CMP (8) |
| 170 | #define ETM_MAX_VMID_CMP (8) |
| 171 | #define ETM_MAX_PE_CMP (8) |
| 172 | #define ETM_MAX_RES_SEL (32) |
| 173 | #define ETM_MAX_SS_CMP (8) |
| 174 | |
| 175 | #define ETM_CPMR_CLKEN (0x4) |
| 176 | #define ETM_ARCH_V4 (0x40) |
| 177 | #define ETM_ARCH_V4_2 (0x42) |
| 178 | |
| 179 | #define MAX_ETM_STATE_SIZE (165) |
| 180 | |
| 181 | #define TZ_DBG_ETM_FEAT_ID (0x8) |
| 182 | #define TZ_DBG_ETM_VER (0x400000) |
| 183 | #define HW_SOC_ID_M8953 (293) |
| 184 | |
| 185 | #define etm_writel(etm, val, off) \ |
| 186 | __raw_writel(val, etm->base + off) |
| 187 | #define etm_readl(etm, off) \ |
| 188 | __raw_readl(etm->base + off) |
| 189 | |
| 190 | #define etm_writeq(etm, val, off) \ |
| 191 | __raw_writeq(val, etm->base + off) |
| 192 | #define etm_readq(etm, off) \ |
| 193 | __raw_readq(etm->base + off) |
| 194 | |
| 195 | #define ETM_LOCK(base) \ |
| 196 | do { \ |
| 197 | mb(); /* ensure configuration take effect before we lock it */ \ |
| 198 | etm_writel(base, 0x0, CORESIGHT_LAR); \ |
| 199 | } while (0) |
| 200 | |
| 201 | #define ETM_UNLOCK(base) \ |
| 202 | do { \ |
| 203 | etm_writel(base, CORESIGHT_UNLOCK, CORESIGHT_LAR); \ |
| 204 | mb(); /* ensure unlock take effect before we configure */ \ |
| 205 | } while (0) |
| 206 | |
| 207 | struct etm_ctx { |
| 208 | uint8_t arch; |
| 209 | uint8_t nr_pe; |
| 210 | uint8_t nr_pe_cmp; |
| 211 | uint8_t nr_addr_cmp; |
| 212 | uint8_t nr_data_cmp; |
| 213 | uint8_t nr_cntr; |
| 214 | uint8_t nr_ext_inp; |
| 215 | uint8_t nr_ext_inp_sel; |
| 216 | uint8_t nr_ext_out; |
| 217 | uint8_t nr_ctxid_cmp; |
| 218 | uint8_t nr_vmid_cmp; |
| 219 | uint8_t nr_seq_state; |
| 220 | uint8_t nr_event; |
| 221 | uint8_t nr_resource; |
| 222 | uint8_t nr_ss_cmp; |
| 223 | bool si_enable; |
| 224 | bool save_restore_disabled; |
| 225 | bool save_restore_enabled; |
| 226 | bool os_lock_present; |
| 227 | bool init; |
| 228 | bool enable; |
| 229 | void __iomem *base; |
| 230 | struct device *dev; |
| 231 | uint64_t *state; |
| 232 | spinlock_t spinlock; |
| 233 | struct mutex mutex; |
| 234 | }; |
| 235 | |
| 236 | static struct etm_ctx *etm[NR_CPUS]; |
| 237 | static int cnt; |
| 238 | |
| 239 | static struct clk *clock[NR_CPUS]; |
| 240 | |
| 241 | static ATOMIC_NOTIFIER_HEAD(etm_save_notifier_list); |
| 242 | static ATOMIC_NOTIFIER_HEAD(etm_restore_notifier_list); |
| 243 | |
| 244 | int msm_jtag_save_register(struct notifier_block *nb) |
| 245 | { |
| 246 | return atomic_notifier_chain_register(&etm_save_notifier_list, nb); |
| 247 | } |
| 248 | EXPORT_SYMBOL(msm_jtag_save_register); |
| 249 | |
| 250 | int msm_jtag_save_unregister(struct notifier_block *nb) |
| 251 | { |
| 252 | return atomic_notifier_chain_unregister(&etm_save_notifier_list, nb); |
| 253 | } |
| 254 | EXPORT_SYMBOL(msm_jtag_save_unregister); |
| 255 | |
| 256 | int msm_jtag_restore_register(struct notifier_block *nb) |
| 257 | { |
| 258 | return atomic_notifier_chain_register(&etm_restore_notifier_list, nb); |
| 259 | } |
| 260 | EXPORT_SYMBOL(msm_jtag_restore_register); |
| 261 | |
| 262 | int msm_jtag_restore_unregister(struct notifier_block *nb) |
| 263 | { |
| 264 | return atomic_notifier_chain_unregister(&etm_restore_notifier_list, nb); |
| 265 | } |
| 266 | EXPORT_SYMBOL(msm_jtag_restore_unregister); |
| 267 | |
| 268 | static void etm_os_lock(struct etm_ctx *etmdata) |
| 269 | { |
| 270 | if (etmdata->os_lock_present) { |
| 271 | etm_writel(etmdata, 0x1, TRCOSLAR); |
| 272 | /* Ensure OS lock is set before proceeding */ |
| 273 | mb(); |
| 274 | } |
| 275 | } |
| 276 | |
| 277 | static void etm_os_unlock(struct etm_ctx *etmdata) |
| 278 | { |
| 279 | if (etmdata->os_lock_present) { |
| 280 | /* Ensure all writes are complete before clearing OS lock */ |
| 281 | mb(); |
| 282 | etm_writel(etmdata, 0x0, TRCOSLAR); |
| 283 | } |
| 284 | } |
| 285 | |
| 286 | static inline void etm_mm_save_state(struct etm_ctx *etmdata) |
| 287 | { |
| 288 | int i, j, count; |
| 289 | |
| 290 | i = 0; |
| 291 | mb(); /* ensure all register writes complete before saving them */ |
| 292 | isb(); |
| 293 | ETM_UNLOCK(etmdata); |
| 294 | |
| 295 | switch (etmdata->arch) { |
| 296 | case ETM_ARCH_V4_2: |
| 297 | case ETM_ARCH_V4: |
| 298 | etm_os_lock(etmdata); |
| 299 | |
| 300 | /* poll until programmers' model becomes stable */ |
| 301 | for (count = TIMEOUT_US; (BVAL(etm_readl(etmdata, TRCSTATR), 1) |
| 302 | != 1) && count > 0; count--) |
| 303 | udelay(1); |
| 304 | if (count == 0) |
| 305 | pr_err_ratelimited("programmers model is not stable\n" |
| 306 | ); |
| 307 | |
| 308 | /* main control and configuration registers */ |
| 309 | etmdata->state[i++] = etm_readl(etmdata, TRCPROCSELR); |
| 310 | etmdata->state[i++] = etm_readl(etmdata, TRCCONFIGR); |
| 311 | etmdata->state[i++] = etm_readl(etmdata, TRCAUXCTLR); |
| 312 | etmdata->state[i++] = etm_readl(etmdata, TRCEVENTCTL0R); |
| 313 | etmdata->state[i++] = etm_readl(etmdata, TRCEVENTCTL1R); |
| 314 | etmdata->state[i++] = etm_readl(etmdata, TRCSTALLCTLR); |
| 315 | etmdata->state[i++] = etm_readl(etmdata, TRCTSCTLR); |
| 316 | etmdata->state[i++] = etm_readl(etmdata, TRCSYNCPR); |
| 317 | etmdata->state[i++] = etm_readl(etmdata, TRCCCCTLR); |
| 318 | etmdata->state[i++] = etm_readl(etmdata, TRCBBCTLR); |
| 319 | etmdata->state[i++] = etm_readl(etmdata, TRCTRACEIDR); |
| 320 | etmdata->state[i++] = etm_readl(etmdata, TRCQCTLR); |
| 321 | /* filtering control registers */ |
| 322 | etmdata->state[i++] = etm_readl(etmdata, TRCVICTLR); |
| 323 | etmdata->state[i++] = etm_readl(etmdata, TRCVIIECTLR); |
| 324 | etmdata->state[i++] = etm_readl(etmdata, TRCVISSCTLR); |
| 325 | etmdata->state[i++] = etm_readl(etmdata, TRCVIPCSSCTLR); |
| 326 | etmdata->state[i++] = etm_readl(etmdata, TRCVDCTLR); |
| 327 | etmdata->state[i++] = etm_readl(etmdata, TRCVDSACCTLR); |
| 328 | etmdata->state[i++] = etm_readl(etmdata, TRCVDARCCTLR); |
| 329 | /* derived resource registers */ |
| 330 | for (j = 0; j < etmdata->nr_seq_state-1; j++) |
| 331 | etmdata->state[i++] = etm_readl(etmdata, TRCSEQEVRn(j)); |
| 332 | etmdata->state[i++] = etm_readl(etmdata, TRCSEQRSTEVR); |
| 333 | etmdata->state[i++] = etm_readl(etmdata, TRCSEQSTR); |
| 334 | etmdata->state[i++] = etm_readl(etmdata, TRCEXTINSELR); |
| 335 | for (j = 0; j < etmdata->nr_cntr; j++) { |
| 336 | etmdata->state[i++] = etm_readl(etmdata, |
| 337 | TRCCNTRLDVRn(j)); |
| 338 | etmdata->state[i++] = etm_readl(etmdata, |
| 339 | TRCCNTCTLRn(j)); |
| 340 | etmdata->state[i++] = etm_readl(etmdata, |
| 341 | TRCCNTVRn(j)); |
| 342 | } |
| 343 | /* resource selection registers */ |
| 344 | for (j = 0; j < etmdata->nr_resource; j++) |
| 345 | etmdata->state[i++] = etm_readl(etmdata, TRCRSCTLRn(j)); |
| 346 | /* comparator registers */ |
| 347 | for (j = 0; j < etmdata->nr_addr_cmp * 2; j++) { |
| 348 | etmdata->state[i++] = etm_readq(etmdata, TRCACVRn(j)); |
| 349 | etmdata->state[i++] = etm_readq(etmdata, TRCACATRn(j)); |
| 350 | } |
| 351 | for (j = 0; j < etmdata->nr_data_cmp; j++) { |
| 352 | etmdata->state[i++] = etm_readq(etmdata, TRCDVCVRn(j)); |
| 353 | etmdata->state[i++] = etm_readq(etmdata, TRCDVCMRn(i)); |
| 354 | } |
| 355 | for (j = 0; j < etmdata->nr_ctxid_cmp; j++) |
| 356 | etmdata->state[i++] = etm_readq(etmdata, TRCCIDCVRn(j)); |
| 357 | etmdata->state[i++] = etm_readl(etmdata, TRCCIDCCTLR0); |
| 358 | etmdata->state[i++] = etm_readl(etmdata, TRCCIDCCTLR1); |
| 359 | for (j = 0; j < etmdata->nr_vmid_cmp; j++) |
| 360 | etmdata->state[i++] = etm_readq(etmdata, |
| 361 | TRCVMIDCVRn(j)); |
| 362 | etmdata->state[i++] = etm_readl(etmdata, TRCVMIDCCTLR0); |
| 363 | etmdata->state[i++] = etm_readl(etmdata, TRCVMIDCCTLR1); |
| 364 | /* single-shot comparator registers */ |
| 365 | for (j = 0; j < etmdata->nr_ss_cmp; j++) { |
| 366 | etmdata->state[i++] = etm_readl(etmdata, TRCSSCCRn(j)); |
| 367 | etmdata->state[i++] = etm_readl(etmdata, TRCSSCSRn(j)); |
| 368 | etmdata->state[i++] = etm_readl(etmdata, |
| 369 | TRCSSPCICRn(j)); |
| 370 | } |
| 371 | /* claim tag registers */ |
| 372 | etmdata->state[i++] = etm_readl(etmdata, TRCCLAIMCLR); |
| 373 | /* program ctrl register */ |
| 374 | etmdata->state[i++] = etm_readl(etmdata, TRCPRGCTLR); |
| 375 | |
| 376 | /* ensure trace unit is idle to be powered down */ |
| 377 | for (count = TIMEOUT_US; (BVAL(etm_readl(etmdata, TRCSTATR), 0) |
| 378 | != 1) && count > 0; count--) |
| 379 | udelay(1); |
| 380 | if (count == 0) |
| 381 | pr_err_ratelimited("timeout waiting for idle state\n"); |
| 382 | |
| 383 | atomic_notifier_call_chain(&etm_save_notifier_list, 0, NULL); |
| 384 | |
| 385 | break; |
| 386 | default: |
| 387 | pr_err_ratelimited("unsupported etm arch %d in %s\n", |
| 388 | etmdata->arch, __func__); |
| 389 | } |
| 390 | |
| 391 | ETM_LOCK(etmdata); |
| 392 | } |
| 393 | |
| 394 | static inline void etm_mm_restore_state(struct etm_ctx *etmdata) |
| 395 | { |
| 396 | int i, j; |
| 397 | |
| 398 | i = 0; |
| 399 | ETM_UNLOCK(etmdata); |
| 400 | |
| 401 | switch (etmdata->arch) { |
| 402 | case ETM_ARCH_V4_2: |
| 403 | case ETM_ARCH_V4: |
| 404 | atomic_notifier_call_chain(&etm_restore_notifier_list, 0, NULL); |
| 405 | |
| 406 | /* check OS lock is locked */ |
| 407 | if (BVAL(etm_readl(etmdata, TRCOSLSR), 1) != 1) { |
| 408 | pr_err_ratelimited("OS lock is unlocked\n"); |
| 409 | etm_os_lock(etmdata); |
| 410 | } |
| 411 | |
| 412 | /* main control and configuration registers */ |
| 413 | etm_writel(etmdata, etmdata->state[i++], TRCPROCSELR); |
| 414 | etm_writel(etmdata, etmdata->state[i++], TRCCONFIGR); |
| 415 | etm_writel(etmdata, etmdata->state[i++], TRCAUXCTLR); |
| 416 | etm_writel(etmdata, etmdata->state[i++], TRCEVENTCTL0R); |
| 417 | etm_writel(etmdata, etmdata->state[i++], TRCEVENTCTL1R); |
| 418 | etm_writel(etmdata, etmdata->state[i++], TRCSTALLCTLR); |
| 419 | etm_writel(etmdata, etmdata->state[i++], TRCTSCTLR); |
| 420 | etm_writel(etmdata, etmdata->state[i++], TRCSYNCPR); |
| 421 | etm_writel(etmdata, etmdata->state[i++], TRCCCCTLR); |
| 422 | etm_writel(etmdata, etmdata->state[i++], TRCBBCTLR); |
| 423 | etm_writel(etmdata, etmdata->state[i++], TRCTRACEIDR); |
| 424 | etm_writel(etmdata, etmdata->state[i++], TRCQCTLR); |
| 425 | /* filtering control registers */ |
| 426 | etm_writel(etmdata, etmdata->state[i++], TRCVICTLR); |
| 427 | etm_writel(etmdata, etmdata->state[i++], TRCVIIECTLR); |
| 428 | etm_writel(etmdata, etmdata->state[i++], TRCVISSCTLR); |
| 429 | etm_writel(etmdata, etmdata->state[i++], TRCVIPCSSCTLR); |
| 430 | etm_writel(etmdata, etmdata->state[i++], TRCVDCTLR); |
| 431 | etm_writel(etmdata, etmdata->state[i++], TRCVDSACCTLR); |
| 432 | etm_writel(etmdata, etmdata->state[i++], TRCVDARCCTLR); |
| 433 | /* derived resources registers */ |
| 434 | for (j = 0; j < etmdata->nr_seq_state-1; j++) |
| 435 | etm_writel(etmdata, etmdata->state[i++], TRCSEQEVRn(j)); |
| 436 | etm_writel(etmdata, etmdata->state[i++], TRCSEQRSTEVR); |
| 437 | etm_writel(etmdata, etmdata->state[i++], TRCSEQSTR); |
| 438 | etm_writel(etmdata, etmdata->state[i++], TRCEXTINSELR); |
| 439 | for (j = 0; j < etmdata->nr_cntr; j++) { |
| 440 | etm_writel(etmdata, etmdata->state[i++], |
| 441 | TRCCNTRLDVRn(j)); |
| 442 | etm_writel(etmdata, etmdata->state[i++], |
| 443 | TRCCNTCTLRn(j)); |
| 444 | etm_writel(etmdata, etmdata->state[i++], TRCCNTVRn(j)); |
| 445 | } |
| 446 | /* resource selection registers */ |
| 447 | for (j = 0; j < etmdata->nr_resource; j++) |
| 448 | etm_writel(etmdata, etmdata->state[i++], TRCRSCTLRn(j)); |
| 449 | /* comparator registers */ |
| 450 | for (j = 0; j < etmdata->nr_addr_cmp * 2; j++) { |
| 451 | etm_writeq(etmdata, etmdata->state[i++], TRCACVRn(j)); |
| 452 | etm_writeq(etmdata, etmdata->state[i++], TRCACATRn(j)); |
| 453 | } |
| 454 | for (j = 0; j < etmdata->nr_data_cmp; j++) { |
| 455 | etm_writeq(etmdata, etmdata->state[i++], TRCDVCVRn(j)); |
| 456 | etm_writeq(etmdata, etmdata->state[i++], TRCDVCMRn(j)); |
| 457 | } |
| 458 | for (j = 0; j < etmdata->nr_ctxid_cmp; j++) |
| 459 | etm_writeq(etmdata, etmdata->state[i++], TRCCIDCVRn(j)); |
| 460 | etm_writel(etmdata, etmdata->state[i++], TRCCIDCCTLR0); |
| 461 | etm_writel(etmdata, etmdata->state[i++], TRCCIDCCTLR1); |
| 462 | for (j = 0; j < etmdata->nr_vmid_cmp; j++) |
| 463 | etm_writeq(etmdata, etmdata->state[i++], |
| 464 | TRCVMIDCVRn(j)); |
| 465 | etm_writel(etmdata, etmdata->state[i++], TRCVMIDCCTLR0); |
| 466 | etm_writel(etmdata, etmdata->state[i++], TRCVMIDCCTLR1); |
| 467 | /* e-shot comparator registers */ |
| 468 | for (j = 0; j < etmdata->nr_ss_cmp; j++) { |
| 469 | etm_writel(etmdata, etmdata->state[i++], TRCSSCCRn(j)); |
| 470 | etm_writel(etmdata, etmdata->state[i++], TRCSSCSRn(j)); |
| 471 | etm_writel(etmdata, etmdata->state[i++], |
| 472 | TRCSSPCICRn(j)); |
| 473 | } |
| 474 | /* claim tag registers */ |
| 475 | etm_writel(etmdata, etmdata->state[i++], TRCCLAIMSET); |
| 476 | /* program ctrl register */ |
| 477 | etm_writel(etmdata, etmdata->state[i++], TRCPRGCTLR); |
| 478 | |
| 479 | etm_os_unlock(etmdata); |
| 480 | break; |
| 481 | default: |
| 482 | pr_err_ratelimited("unsupported etm arch %d in %s\n", |
| 483 | etmdata->arch, __func__); |
| 484 | } |
| 485 | |
| 486 | ETM_LOCK(etmdata); |
| 487 | } |
| 488 | |
| 489 | static inline void etm_clk_disable(void) |
| 490 | { |
| 491 | uint32_t cpmr; |
| 492 | |
| 493 | isb(); |
| 494 | cpmr = trc_readl(CPMR_EL1); |
| 495 | cpmr &= ~ETM_CPMR_CLKEN; |
| 496 | trc_write(cpmr, CPMR_EL1); |
| 497 | } |
| 498 | |
| 499 | static inline void etm_clk_enable(void) |
| 500 | { |
| 501 | uint32_t cpmr; |
| 502 | |
| 503 | cpmr = trc_readl(CPMR_EL1); |
| 504 | cpmr |= ETM_CPMR_CLKEN; |
| 505 | trc_write(cpmr, CPMR_EL1); |
| 506 | isb(); |
| 507 | } |
| 508 | |
| 509 | static int etm_read_ssxr(uint64_t *state, int i, int j) |
| 510 | { |
| 511 | switch (j) { |
| 512 | case 0: |
| 513 | state[i++] = trc_readl(ETMSEQEVR0); |
| 514 | break; |
| 515 | case 1: |
| 516 | state[i++] = trc_readl(ETMSEQEVR1); |
| 517 | break; |
| 518 | case 2: |
| 519 | state[i++] = trc_readl(ETMSEQEVR2); |
| 520 | break; |
| 521 | default: |
| 522 | pr_err_ratelimited("idx %d out of bounds in %s\n", j, __func__); |
| 523 | } |
| 524 | return i; |
| 525 | } |
| 526 | |
| 527 | static int etm_read_crxr(uint64_t *state, int i, int j) |
| 528 | { |
| 529 | switch (j) { |
| 530 | case 0: |
| 531 | state[i++] = trc_readl(ETMCNTRLDVR0); |
| 532 | state[i++] = trc_readl(ETMCNTCTLR0); |
| 533 | state[i++] = trc_readl(ETMCNTVR0); |
| 534 | break; |
| 535 | case 1: |
| 536 | state[i++] = trc_readl(ETMCNTRLDVR1); |
| 537 | state[i++] = trc_readl(ETMCNTCTLR1); |
| 538 | state[i++] = trc_readl(ETMCNTVR1); |
| 539 | break; |
| 540 | case 2: |
| 541 | state[i++] = trc_readl(ETMCNTRLDVR2); |
| 542 | state[i++] = trc_readl(ETMCNTCTLR2); |
| 543 | state[i++] = trc_readl(ETMCNTVR2); |
| 544 | break; |
| 545 | case 3: |
| 546 | state[i++] = trc_readl(ETMCNTRLDVR3); |
| 547 | state[i++] = trc_readl(ETMCNTCTLR3); |
| 548 | state[i++] = trc_readl(ETMCNTVR3); |
| 549 | break; |
| 550 | default: |
| 551 | pr_err_ratelimited("idx %d out of bounds in %s\n", j, __func__); |
| 552 | } |
| 553 | return i; |
| 554 | } |
| 555 | |
| 556 | static int etm_read_rsxr(uint64_t *state, int i, int j) |
| 557 | { |
| 558 | switch (j) { |
| 559 | case 2: |
| 560 | state[i++] = trc_readl(ETMRSCTLR2); |
| 561 | break; |
| 562 | case 3: |
| 563 | state[i++] = trc_readl(ETMRSCTLR3); |
| 564 | break; |
| 565 | case 4: |
| 566 | state[i++] = trc_readl(ETMRSCTLR4); |
| 567 | break; |
| 568 | case 5: |
| 569 | state[i++] = trc_readl(ETMRSCTLR5); |
| 570 | break; |
| 571 | case 6: |
| 572 | state[i++] = trc_readl(ETMRSCTLR6); |
| 573 | break; |
| 574 | case 7: |
| 575 | state[i++] = trc_readl(ETMRSCTLR7); |
| 576 | break; |
| 577 | case 8: |
| 578 | state[i++] = trc_readl(ETMRSCTLR8); |
| 579 | break; |
| 580 | case 9: |
| 581 | state[i++] = trc_readl(ETMRSCTLR9); |
| 582 | break; |
| 583 | case 10: |
| 584 | state[i++] = trc_readl(ETMRSCTLR10); |
| 585 | break; |
| 586 | case 11: |
| 587 | state[i++] = trc_readl(ETMRSCTLR11); |
| 588 | break; |
| 589 | case 12: |
| 590 | state[i++] = trc_readl(ETMRSCTLR12); |
| 591 | break; |
| 592 | case 13: |
| 593 | state[i++] = trc_readl(ETMRSCTLR13); |
| 594 | break; |
| 595 | case 14: |
| 596 | state[i++] = trc_readl(ETMRSCTLR14); |
| 597 | break; |
| 598 | case 15: |
| 599 | state[i++] = trc_readl(ETMRSCTLR15); |
| 600 | break; |
| 601 | case 16: |
| 602 | state[i++] = trc_readl(ETMRSCTLR16); |
| 603 | break; |
| 604 | case 17: |
| 605 | state[i++] = trc_readl(ETMRSCTLR17); |
| 606 | break; |
| 607 | case 18: |
| 608 | state[i++] = trc_readl(ETMRSCTLR18); |
| 609 | break; |
| 610 | case 19: |
| 611 | state[i++] = trc_readl(ETMRSCTLR19); |
| 612 | break; |
| 613 | case 20: |
| 614 | state[i++] = trc_readl(ETMRSCTLR20); |
| 615 | break; |
| 616 | case 21: |
| 617 | state[i++] = trc_readl(ETMRSCTLR21); |
| 618 | break; |
| 619 | case 22: |
| 620 | state[i++] = trc_readl(ETMRSCTLR22); |
| 621 | break; |
| 622 | case 23: |
| 623 | state[i++] = trc_readl(ETMRSCTLR23); |
| 624 | break; |
| 625 | case 24: |
| 626 | state[i++] = trc_readl(ETMRSCTLR24); |
| 627 | break; |
| 628 | case 25: |
| 629 | state[i++] = trc_readl(ETMRSCTLR25); |
| 630 | break; |
| 631 | case 26: |
| 632 | state[i++] = trc_readl(ETMRSCTLR26); |
| 633 | break; |
| 634 | case 27: |
| 635 | state[i++] = trc_readl(ETMRSCTLR27); |
| 636 | break; |
| 637 | case 28: |
| 638 | state[i++] = trc_readl(ETMRSCTLR28); |
| 639 | break; |
| 640 | case 29: |
| 641 | state[i++] = trc_readl(ETMRSCTLR29); |
| 642 | break; |
| 643 | case 30: |
| 644 | state[i++] = trc_readl(ETMRSCTLR30); |
| 645 | break; |
| 646 | case 31: |
| 647 | state[i++] = trc_readl(ETMRSCTLR31); |
| 648 | break; |
| 649 | default: |
| 650 | pr_err_ratelimited("idx %d out of bounds in %s\n", j, __func__); |
| 651 | } |
| 652 | return i; |
| 653 | } |
| 654 | |
| 655 | static int etm_read_acr(uint64_t *state, int i, int j) |
| 656 | { |
| 657 | switch (j) { |
| 658 | case 0: |
| 659 | state[i++] = trc_readq(ETMACVR0); |
| 660 | state[i++] = trc_readq(ETMACATR0); |
| 661 | break; |
| 662 | case 1: |
| 663 | state[i++] = trc_readq(ETMACVR1); |
| 664 | state[i++] = trc_readq(ETMACATR1); |
| 665 | break; |
| 666 | case 2: |
| 667 | state[i++] = trc_readq(ETMACVR2); |
| 668 | state[i++] = trc_readq(ETMACATR2); |
| 669 | break; |
| 670 | case 3: |
| 671 | state[i++] = trc_readq(ETMACVR3); |
| 672 | state[i++] = trc_readq(ETMACATR3); |
| 673 | break; |
| 674 | case 4: |
| 675 | state[i++] = trc_readq(ETMACVR4); |
| 676 | state[i++] = trc_readq(ETMACATR4); |
| 677 | break; |
| 678 | case 5: |
| 679 | state[i++] = trc_readq(ETMACVR5); |
| 680 | state[i++] = trc_readq(ETMACATR5); |
| 681 | break; |
| 682 | case 6: |
| 683 | state[i++] = trc_readq(ETMACVR6); |
| 684 | state[i++] = trc_readq(ETMACATR6); |
| 685 | break; |
| 686 | case 7: |
| 687 | state[i++] = trc_readq(ETMACVR7); |
| 688 | state[i++] = trc_readq(ETMACATR7); |
| 689 | break; |
| 690 | case 8: |
| 691 | state[i++] = trc_readq(ETMACVR8); |
| 692 | state[i++] = trc_readq(ETMACATR8); |
| 693 | break; |
| 694 | case 9: |
| 695 | state[i++] = trc_readq(ETMACVR9); |
| 696 | state[i++] = trc_readq(ETMACATR9); |
| 697 | break; |
| 698 | case 10: |
| 699 | state[i++] = trc_readq(ETMACVR10); |
| 700 | state[i++] = trc_readq(ETMACATR10); |
| 701 | break; |
| 702 | case 11: |
| 703 | state[i++] = trc_readq(ETMACVR11); |
| 704 | state[i++] = trc_readq(ETMACATR11); |
| 705 | break; |
| 706 | case 12: |
| 707 | state[i++] = trc_readq(ETMACVR12); |
| 708 | state[i++] = trc_readq(ETMACATR12); |
| 709 | break; |
| 710 | case 13: |
| 711 | state[i++] = trc_readq(ETMACVR13); |
| 712 | state[i++] = trc_readq(ETMACATR13); |
| 713 | break; |
| 714 | case 14: |
| 715 | state[i++] = trc_readq(ETMACVR14); |
| 716 | state[i++] = trc_readq(ETMACATR14); |
| 717 | break; |
| 718 | case 15: |
| 719 | state[i++] = trc_readq(ETMACVR15); |
| 720 | state[i++] = trc_readq(ETMACATR15); |
| 721 | break; |
| 722 | default: |
| 723 | pr_err_ratelimited("idx %d out of bounds in %s\n", j, __func__); |
| 724 | } |
| 725 | return i; |
| 726 | } |
| 727 | |
| 728 | static int etm_read_dvcr(uint64_t *state, int i, int j) |
| 729 | { |
| 730 | switch (j) { |
| 731 | case 0: |
| 732 | state[i++] = trc_readq(ETMDVCVR0); |
| 733 | state[i++] = trc_readq(ETMDVCMR0); |
| 734 | break; |
| 735 | case 1: |
| 736 | state[i++] = trc_readq(ETMDVCVR1); |
| 737 | state[i++] = trc_readq(ETMDVCMR1); |
| 738 | break; |
| 739 | case 2: |
| 740 | state[i++] = trc_readq(ETMDVCVR2); |
| 741 | state[i++] = trc_readq(ETMDVCMR2); |
| 742 | break; |
| 743 | case 3: |
| 744 | state[i++] = trc_readq(ETMDVCVR3); |
| 745 | state[i++] = trc_readq(ETMDVCMR3); |
| 746 | break; |
| 747 | case 4: |
| 748 | state[i++] = trc_readq(ETMDVCVR4); |
| 749 | state[i++] = trc_readq(ETMDVCMR4); |
| 750 | break; |
| 751 | case 5: |
| 752 | state[i++] = trc_readq(ETMDVCVR5); |
| 753 | state[i++] = trc_readq(ETMDVCMR5); |
| 754 | break; |
| 755 | case 6: |
| 756 | state[i++] = trc_readq(ETMDVCVR6); |
| 757 | state[i++] = trc_readq(ETMDVCMR6); |
| 758 | break; |
| 759 | case 7: |
| 760 | state[i++] = trc_readq(ETMDVCVR7); |
| 761 | state[i++] = trc_readq(ETMDVCMR7); |
| 762 | break; |
| 763 | default: |
| 764 | pr_err_ratelimited("idx %d out of bounds in %s\n", j, __func__); |
| 765 | } |
| 766 | return i; |
| 767 | } |
| 768 | |
| 769 | static int etm_read_ccvr(uint64_t *state, int i, int j) |
| 770 | { |
| 771 | switch (j) { |
| 772 | case 0: |
| 773 | state[i++] = trc_readq(ETMCIDCVR0); |
| 774 | break; |
| 775 | case 1: |
| 776 | state[i++] = trc_readq(ETMCIDCVR1); |
| 777 | break; |
| 778 | case 2: |
| 779 | state[i++] = trc_readq(ETMCIDCVR2); |
| 780 | break; |
| 781 | case 3: |
| 782 | state[i++] = trc_readq(ETMCIDCVR3); |
| 783 | break; |
| 784 | case 4: |
| 785 | state[i++] = trc_readq(ETMCIDCVR4); |
| 786 | break; |
| 787 | case 5: |
| 788 | state[i++] = trc_readq(ETMCIDCVR5); |
| 789 | break; |
| 790 | case 6: |
| 791 | state[i++] = trc_readq(ETMCIDCVR6); |
| 792 | break; |
| 793 | case 7: |
| 794 | state[i++] = trc_readq(ETMCIDCVR7); |
| 795 | break; |
| 796 | default: |
| 797 | pr_err_ratelimited("idx %d out of bounds in %s\n", j, __func__); |
| 798 | } |
| 799 | return i; |
| 800 | } |
| 801 | |
| 802 | static int etm_read_vcvr(uint64_t *state, int i, int j) |
| 803 | { |
| 804 | switch (j) { |
| 805 | case 0: |
| 806 | state[i++] = trc_readq(ETMVMIDCVR0); |
| 807 | break; |
| 808 | case 1: |
| 809 | state[i++] = trc_readq(ETMVMIDCVR1); |
| 810 | break; |
| 811 | case 2: |
| 812 | state[i++] = trc_readq(ETMVMIDCVR2); |
| 813 | break; |
| 814 | case 3: |
| 815 | state[i++] = trc_readq(ETMVMIDCVR3); |
| 816 | break; |
| 817 | case 4: |
| 818 | state[i++] = trc_readq(ETMVMIDCVR4); |
| 819 | break; |
| 820 | case 5: |
| 821 | state[i++] = trc_readq(ETMVMIDCVR5); |
| 822 | break; |
| 823 | case 6: |
| 824 | state[i++] = trc_readq(ETMVMIDCVR6); |
| 825 | break; |
| 826 | case 7: |
| 827 | state[i++] = trc_readq(ETMVMIDCVR7); |
| 828 | break; |
| 829 | default: |
| 830 | pr_err_ratelimited("idx %d out of bounds in %s\n", j, __func__); |
| 831 | } |
| 832 | return i; |
| 833 | } |
| 834 | |
| 835 | static int etm_read_sscr(uint64_t *state, int i, int j) |
| 836 | { |
| 837 | switch (j) { |
| 838 | case 0: |
| 839 | state[i++] = trc_readl(ETMSSCCR0); |
| 840 | state[i++] = trc_readl(ETMSSCSR0); |
| 841 | state[i++] = trc_readl(ETMSSPCICR0); |
| 842 | break; |
| 843 | case 1: |
| 844 | state[i++] = trc_readl(ETMSSCCR1); |
| 845 | state[i++] = trc_readl(ETMSSCSR1); |
| 846 | state[i++] = trc_readl(ETMSSPCICR1); |
| 847 | break; |
| 848 | case 2: |
| 849 | state[i++] = trc_readl(ETMSSCCR2); |
| 850 | state[i++] = trc_readl(ETMSSCSR2); |
| 851 | state[i++] = trc_readl(ETMSSPCICR2); |
| 852 | break; |
| 853 | case 3: |
| 854 | state[i++] = trc_readl(ETMSSCCR3); |
| 855 | state[i++] = trc_readl(ETMSSCSR3); |
| 856 | state[i++] = trc_readl(ETMSSPCICR3); |
| 857 | break; |
| 858 | case 4: |
| 859 | state[i++] = trc_readl(ETMSSCCR4); |
| 860 | state[i++] = trc_readl(ETMSSCSR4); |
| 861 | state[i++] = trc_readl(ETMSSPCICR4); |
| 862 | break; |
| 863 | case 5: |
| 864 | state[i++] = trc_readl(ETMSSCCR5); |
| 865 | state[i++] = trc_readl(ETMSSCSR5); |
| 866 | state[i++] = trc_readl(ETMSSPCICR5); |
| 867 | break; |
| 868 | case 6: |
| 869 | state[i++] = trc_readl(ETMSSCCR6); |
| 870 | state[i++] = trc_readl(ETMSSCSR6); |
| 871 | state[i++] = trc_readl(ETMSSPCICR6); |
| 872 | break; |
| 873 | case 7: |
| 874 | state[i++] = trc_readl(ETMSSCCR7); |
| 875 | state[i++] = trc_readl(ETMSSCSR7); |
| 876 | state[i++] = trc_readl(ETMSSPCICR7); |
| 877 | break; |
| 878 | default: |
| 879 | pr_err_ratelimited("idx %d out of bounds in %s\n", j, __func__); |
| 880 | } |
| 881 | return i; |
| 882 | } |
| 883 | |
| 884 | static inline void etm_si_save_state(struct etm_ctx *etmdata) |
| 885 | { |
| 886 | int i, j, count; |
| 887 | |
| 888 | i = 0; |
| 889 | /* Ensure all writes are complete before saving ETM registers */ |
| 890 | mb(); |
| 891 | isb(); |
| 892 | |
| 893 | /* Vote for ETM power/clock enable */ |
| 894 | etm_clk_enable(); |
| 895 | |
| 896 | switch (etmdata->arch) { |
| 897 | case ETM_ARCH_V4_2: |
| 898 | case ETM_ARCH_V4: |
| 899 | trc_write(0x1, ETMOSLAR); |
| 900 | isb(); |
| 901 | |
| 902 | /* poll until programmers' model becomes stable */ |
| 903 | for (count = TIMEOUT_US; (BVAL(trc_readl(ETMSTATR), 1) |
| 904 | != 1) && count > 0; count--) |
| 905 | udelay(1); |
| 906 | if (count == 0) |
| 907 | pr_err_ratelimited("programmers model is not stable\n"); |
| 908 | |
| 909 | /* main control and configuration registers */ |
| 910 | etmdata->state[i++] = trc_readl(ETMCONFIGR); |
| 911 | etmdata->state[i++] = trc_readl(ETMEVENTCTL0R); |
| 912 | etmdata->state[i++] = trc_readl(ETMEVENTCTL1R); |
| 913 | etmdata->state[i++] = trc_readl(ETMSTALLCTLR); |
| 914 | etmdata->state[i++] = trc_readl(ETMTSCTLR); |
| 915 | etmdata->state[i++] = trc_readl(ETMSYNCPR); |
| 916 | etmdata->state[i++] = trc_readl(ETMCCCTLR); |
| 917 | etmdata->state[i++] = trc_readl(ETMTRACEIDR); |
| 918 | /* filtering control registers */ |
| 919 | etmdata->state[i++] = trc_readl(ETMVICTLR); |
| 920 | etmdata->state[i++] = trc_readl(ETMVIIECTLR); |
| 921 | etmdata->state[i++] = trc_readl(ETMVISSCTLR); |
| 922 | /* derived resource registers */ |
| 923 | for (j = 0; j < etmdata->nr_seq_state-1; j++) |
| 924 | i = etm_read_ssxr(etmdata->state, i, j); |
| 925 | etmdata->state[i++] = trc_readl(ETMSEQRSTEVR); |
| 926 | etmdata->state[i++] = trc_readl(ETMSEQSTR); |
| 927 | etmdata->state[i++] = trc_readl(ETMEXTINSELR); |
| 928 | for (j = 0; j < etmdata->nr_cntr; j++) |
| 929 | i = etm_read_crxr(etmdata->state, i, j); |
| 930 | /* resource selection registers */ |
| 931 | for (j = 0; j < etmdata->nr_resource; j++) |
| 932 | i = etm_read_rsxr(etmdata->state, i, j + 2); |
| 933 | /* comparator registers */ |
| 934 | for (j = 0; j < etmdata->nr_addr_cmp * 2; j++) |
| 935 | i = etm_read_acr(etmdata->state, i, j); |
| 936 | for (j = 0; j < etmdata->nr_data_cmp; j++) |
| 937 | i = etm_read_dvcr(etmdata->state, i, j); |
| 938 | for (j = 0; j < etmdata->nr_ctxid_cmp; j++) |
| 939 | i = etm_read_ccvr(etmdata->state, i, j); |
| 940 | etmdata->state[i++] = trc_readl(ETMCIDCCTLR0); |
| 941 | for (j = 0; j < etmdata->nr_vmid_cmp; j++) |
| 942 | i = etm_read_vcvr(etmdata->state, i, j); |
| 943 | /* single-shot comparator registers */ |
| 944 | for (j = 0; j < etmdata->nr_ss_cmp; j++) |
| 945 | i = etm_read_sscr(etmdata->state, i, j); |
| 946 | /* program ctrl register */ |
| 947 | etmdata->state[i++] = trc_readl(ETMPRGCTLR); |
| 948 | |
| 949 | /* ensure trace unit is idle to be powered down */ |
| 950 | for (count = TIMEOUT_US; (BVAL(trc_readl(ETMSTATR), 0) |
| 951 | != 1) && count > 0; count--) |
| 952 | udelay(1); |
| 953 | if (count == 0) |
| 954 | pr_err_ratelimited("timeout waiting for idle state\n"); |
| 955 | |
| 956 | atomic_notifier_call_chain(&etm_save_notifier_list, 0, NULL); |
| 957 | |
| 958 | break; |
| 959 | default: |
| 960 | pr_err_ratelimited("unsupported etm arch %d in %s\n", |
| 961 | etmdata->arch, __func__); |
| 962 | } |
| 963 | |
| 964 | /* Vote for ETM power/clock disable */ |
| 965 | etm_clk_disable(); |
| 966 | } |
| 967 | |
| 968 | static int etm_write_ssxr(uint64_t *state, int i, int j) |
| 969 | { |
| 970 | switch (j) { |
| 971 | case 0: |
| 972 | trc_write(state[i++], ETMSEQEVR0); |
| 973 | break; |
| 974 | case 1: |
| 975 | trc_write(state[i++], ETMSEQEVR1); |
| 976 | break; |
| 977 | case 2: |
| 978 | trc_write(state[i++], ETMSEQEVR2); |
| 979 | break; |
| 980 | default: |
| 981 | pr_err_ratelimited("idx %d out of bounds in %s\n", j, __func__); |
| 982 | } |
| 983 | return i; |
| 984 | } |
| 985 | |
| 986 | static int etm_write_crxr(uint64_t *state, int i, int j) |
| 987 | { |
| 988 | switch (j) { |
| 989 | case 0: |
| 990 | trc_write(state[i++], ETMCNTRLDVR0); |
| 991 | trc_write(state[i++], ETMCNTCTLR0); |
| 992 | trc_write(state[i++], ETMCNTVR0); |
| 993 | break; |
| 994 | case 1: |
| 995 | trc_write(state[i++], ETMCNTRLDVR1); |
| 996 | trc_write(state[i++], ETMCNTCTLR1); |
| 997 | trc_write(state[i++], ETMCNTVR1); |
| 998 | break; |
| 999 | case 2: |
| 1000 | trc_write(state[i++], ETMCNTRLDVR2); |
| 1001 | trc_write(state[i++], ETMCNTCTLR2); |
| 1002 | trc_write(state[i++], ETMCNTVR2); |
| 1003 | break; |
| 1004 | case 3: |
| 1005 | trc_write(state[i++], ETMCNTRLDVR3); |
| 1006 | trc_write(state[i++], ETMCNTCTLR3); |
| 1007 | trc_write(state[i++], ETMCNTVR3); |
| 1008 | break; |
| 1009 | default: |
| 1010 | pr_err_ratelimited("idx %d out of bounds in %s\n", j, __func__); |
| 1011 | } |
| 1012 | return i; |
| 1013 | } |
| 1014 | |
| 1015 | static int etm_write_rsxr(uint64_t *state, int i, int j) |
| 1016 | { |
| 1017 | switch (j) { |
| 1018 | case 2: |
| 1019 | trc_write(state[i++], ETMRSCTLR2); |
| 1020 | break; |
| 1021 | case 3: |
| 1022 | trc_write(state[i++], ETMRSCTLR3); |
| 1023 | break; |
| 1024 | case 4: |
| 1025 | trc_write(state[i++], ETMRSCTLR4); |
| 1026 | break; |
| 1027 | case 5: |
| 1028 | trc_write(state[i++], ETMRSCTLR5); |
| 1029 | break; |
| 1030 | case 6: |
| 1031 | trc_write(state[i++], ETMRSCTLR6); |
| 1032 | break; |
| 1033 | case 7: |
| 1034 | trc_write(state[i++], ETMRSCTLR7); |
| 1035 | break; |
| 1036 | case 8: |
| 1037 | trc_write(state[i++], ETMRSCTLR8); |
| 1038 | break; |
| 1039 | case 9: |
| 1040 | trc_write(state[i++], ETMRSCTLR9); |
| 1041 | break; |
| 1042 | case 10: |
| 1043 | trc_write(state[i++], ETMRSCTLR10); |
| 1044 | break; |
| 1045 | case 11: |
| 1046 | trc_write(state[i++], ETMRSCTLR11); |
| 1047 | break; |
| 1048 | case 12: |
| 1049 | trc_write(state[i++], ETMRSCTLR12); |
| 1050 | break; |
| 1051 | case 13: |
| 1052 | trc_write(state[i++], ETMRSCTLR13); |
| 1053 | break; |
| 1054 | case 14: |
| 1055 | trc_write(state[i++], ETMRSCTLR14); |
| 1056 | break; |
| 1057 | case 15: |
| 1058 | trc_write(state[i++], ETMRSCTLR15); |
| 1059 | break; |
| 1060 | case 16: |
| 1061 | trc_write(state[i++], ETMRSCTLR16); |
| 1062 | break; |
| 1063 | case 17: |
| 1064 | trc_write(state[i++], ETMRSCTLR17); |
| 1065 | break; |
| 1066 | case 18: |
| 1067 | trc_write(state[i++], ETMRSCTLR18); |
| 1068 | break; |
| 1069 | case 19: |
| 1070 | trc_write(state[i++], ETMRSCTLR19); |
| 1071 | break; |
| 1072 | case 20: |
| 1073 | trc_write(state[i++], ETMRSCTLR20); |
| 1074 | break; |
| 1075 | case 21: |
| 1076 | trc_write(state[i++], ETMRSCTLR21); |
| 1077 | break; |
| 1078 | case 22: |
| 1079 | trc_write(state[i++], ETMRSCTLR22); |
| 1080 | break; |
| 1081 | case 23: |
| 1082 | trc_write(state[i++], ETMRSCTLR23); |
| 1083 | break; |
| 1084 | case 24: |
| 1085 | trc_write(state[i++], ETMRSCTLR24); |
| 1086 | break; |
| 1087 | case 25: |
| 1088 | trc_write(state[i++], ETMRSCTLR25); |
| 1089 | break; |
| 1090 | case 26: |
| 1091 | trc_write(state[i++], ETMRSCTLR26); |
| 1092 | break; |
| 1093 | case 27: |
| 1094 | trc_write(state[i++], ETMRSCTLR27); |
| 1095 | break; |
| 1096 | case 28: |
| 1097 | trc_write(state[i++], ETMRSCTLR28); |
| 1098 | break; |
| 1099 | case 29: |
| 1100 | trc_write(state[i++], ETMRSCTLR29); |
| 1101 | break; |
| 1102 | case 30: |
| 1103 | trc_write(state[i++], ETMRSCTLR30); |
| 1104 | break; |
| 1105 | case 31: |
| 1106 | trc_write(state[i++], ETMRSCTLR31); |
| 1107 | break; |
| 1108 | default: |
| 1109 | pr_err_ratelimited("idx %d out of bounds in %s\n", j, __func__); |
| 1110 | } |
| 1111 | return i; |
| 1112 | } |
| 1113 | |
| 1114 | static int etm_write_acr(uint64_t *state, int i, int j) |
| 1115 | { |
| 1116 | switch (j) { |
| 1117 | case 0: |
| 1118 | trc_write(state[i++], ETMACVR0); |
| 1119 | trc_write(state[i++], ETMACATR0); |
| 1120 | break; |
| 1121 | case 1: |
| 1122 | trc_write(state[i++], ETMACVR1); |
| 1123 | trc_write(state[i++], ETMACATR1); |
| 1124 | break; |
| 1125 | case 2: |
| 1126 | trc_write(state[i++], ETMACVR2); |
| 1127 | trc_write(state[i++], ETMACATR2); |
| 1128 | break; |
| 1129 | case 3: |
| 1130 | trc_write(state[i++], ETMACVR3); |
| 1131 | trc_write(state[i++], ETMACATR3); |
| 1132 | break; |
| 1133 | case 4: |
| 1134 | trc_write(state[i++], ETMACVR4); |
| 1135 | trc_write(state[i++], ETMACATR4); |
| 1136 | break; |
| 1137 | case 5: |
| 1138 | trc_write(state[i++], ETMACVR5); |
| 1139 | trc_write(state[i++], ETMACATR5); |
| 1140 | break; |
| 1141 | case 6: |
| 1142 | trc_write(state[i++], ETMACVR6); |
| 1143 | trc_write(state[i++], ETMACATR6); |
| 1144 | break; |
| 1145 | case 7: |
| 1146 | trc_write(state[i++], ETMACVR7); |
| 1147 | trc_write(state[i++], ETMACATR7); |
| 1148 | break; |
| 1149 | case 8: |
| 1150 | trc_write(state[i++], ETMACVR8); |
| 1151 | trc_write(state[i++], ETMACATR8); |
| 1152 | break; |
| 1153 | case 9: |
| 1154 | trc_write(state[i++], ETMACVR9); |
| 1155 | trc_write(state[i++], ETMACATR9); |
| 1156 | break; |
| 1157 | case 10: |
| 1158 | trc_write(state[i++], ETMACVR10); |
| 1159 | trc_write(state[i++], ETMACATR10); |
| 1160 | break; |
| 1161 | case 11: |
| 1162 | trc_write(state[i++], ETMACVR11); |
| 1163 | trc_write(state[i++], ETMACATR11); |
| 1164 | break; |
| 1165 | case 12: |
| 1166 | trc_write(state[i++], ETMACVR12); |
| 1167 | trc_write(state[i++], ETMACATR12); |
| 1168 | break; |
| 1169 | case 13: |
| 1170 | trc_write(state[i++], ETMACVR13); |
| 1171 | trc_write(state[i++], ETMACATR13); |
| 1172 | break; |
| 1173 | case 14: |
| 1174 | trc_write(state[i++], ETMACVR14); |
| 1175 | trc_write(state[i++], ETMACATR14); |
| 1176 | break; |
| 1177 | case 15: |
| 1178 | trc_write(state[i++], ETMACVR15); |
| 1179 | trc_write(state[i++], ETMACATR15); |
| 1180 | break; |
| 1181 | default: |
| 1182 | pr_err_ratelimited("idx %d out of bounds in %s\n", j, __func__); |
| 1183 | } |
| 1184 | return i; |
| 1185 | } |
| 1186 | |
| 1187 | static int etm_write_dvcr(uint64_t *state, int i, int j) |
| 1188 | { |
| 1189 | switch (j) { |
| 1190 | case 0: |
| 1191 | trc_write(state[i++], ETMDVCVR0); |
| 1192 | trc_write(state[i++], ETMDVCMR0); |
| 1193 | break; |
| 1194 | case 1: |
| 1195 | trc_write(state[i++], ETMDVCVR1); |
| 1196 | trc_write(state[i++], ETMDVCMR1); |
| 1197 | break; |
| 1198 | case 2: |
| 1199 | trc_write(state[i++], ETMDVCVR2); |
| 1200 | trc_write(state[i++], ETMDVCMR2); |
| 1201 | break; |
| 1202 | case 3: |
| 1203 | trc_write(state[i++], ETMDVCVR3); |
| 1204 | trc_write(state[i++], ETMDVCMR3); |
| 1205 | break; |
| 1206 | case 4: |
| 1207 | trc_write(state[i++], ETMDVCVR4); |
| 1208 | trc_write(state[i++], ETMDVCMR4); |
| 1209 | break; |
| 1210 | case 5: |
| 1211 | trc_write(state[i++], ETMDVCVR5); |
| 1212 | trc_write(state[i++], ETMDVCMR5); |
| 1213 | break; |
| 1214 | case 6: |
| 1215 | trc_write(state[i++], ETMDVCVR6); |
| 1216 | trc_write(state[i++], ETMDVCMR6); |
| 1217 | break; |
| 1218 | case 7: |
| 1219 | trc_write(state[i++], ETMDVCVR7); |
| 1220 | trc_write(state[i++], ETMDVCMR7); |
| 1221 | break; |
| 1222 | default: |
| 1223 | pr_err_ratelimited("idx %d out of bounds in %s\n", j, __func__); |
| 1224 | } |
| 1225 | return i; |
| 1226 | } |
| 1227 | |
| 1228 | static int etm_write_ccvr(uint64_t *state, int i, int j) |
| 1229 | { |
| 1230 | switch (j) { |
| 1231 | case 0: |
| 1232 | trc_write(state[i++], ETMCIDCVR0); |
| 1233 | break; |
| 1234 | case 1: |
| 1235 | trc_write(state[i++], ETMCIDCVR1); |
| 1236 | break; |
| 1237 | case 2: |
| 1238 | trc_write(state[i++], ETMCIDCVR2); |
| 1239 | break; |
| 1240 | case 3: |
| 1241 | trc_write(state[i++], ETMCIDCVR3); |
| 1242 | break; |
| 1243 | case 4: |
| 1244 | trc_write(state[i++], ETMCIDCVR4); |
| 1245 | break; |
| 1246 | case 5: |
| 1247 | trc_write(state[i++], ETMCIDCVR5); |
| 1248 | break; |
| 1249 | case 6: |
| 1250 | trc_write(state[i++], ETMCIDCVR6); |
| 1251 | break; |
| 1252 | case 7: |
| 1253 | trc_write(state[i++], ETMCIDCVR7); |
| 1254 | break; |
| 1255 | default: |
| 1256 | pr_err_ratelimited("idx %d out of bounds in %s\n", j, __func__); |
| 1257 | } |
| 1258 | return i; |
| 1259 | } |
| 1260 | |
| 1261 | static int etm_write_vcvr(uint64_t *state, int i, int j) |
| 1262 | { |
| 1263 | switch (j) { |
| 1264 | case 0: |
| 1265 | trc_write(state[i++], ETMVMIDCVR0); |
| 1266 | break; |
| 1267 | case 1: |
| 1268 | trc_write(state[i++], ETMVMIDCVR1); |
| 1269 | break; |
| 1270 | case 2: |
| 1271 | trc_write(state[i++], ETMVMIDCVR2); |
| 1272 | break; |
| 1273 | case 3: |
| 1274 | trc_write(state[i++], ETMVMIDCVR3); |
| 1275 | break; |
| 1276 | case 4: |
| 1277 | trc_write(state[i++], ETMVMIDCVR4); |
| 1278 | break; |
| 1279 | case 5: |
| 1280 | trc_write(state[i++], ETMVMIDCVR5); |
| 1281 | break; |
| 1282 | case 6: |
| 1283 | trc_write(state[i++], ETMVMIDCVR6); |
| 1284 | break; |
| 1285 | case 7: |
| 1286 | trc_write(state[i++], ETMVMIDCVR7); |
| 1287 | break; |
| 1288 | default: |
| 1289 | pr_err_ratelimited("idx %d out of bounds in %s\n", j, __func__); |
| 1290 | } |
| 1291 | return i; |
| 1292 | } |
| 1293 | |
| 1294 | static int etm_write_sscr(uint64_t *state, int i, int j) |
| 1295 | { |
| 1296 | switch (j) { |
| 1297 | case 0: |
| 1298 | trc_write(state[i++], ETMSSCCR0); |
| 1299 | trc_write(state[i++], ETMSSCSR0); |
| 1300 | trc_write(state[i++], ETMSSPCICR0); |
| 1301 | break; |
| 1302 | case 1: |
| 1303 | trc_write(state[i++], ETMSSCCR1); |
| 1304 | trc_write(state[i++], ETMSSCSR1); |
| 1305 | trc_write(state[i++], ETMSSPCICR1); |
| 1306 | break; |
| 1307 | case 2: |
| 1308 | trc_write(state[i++], ETMSSCCR2); |
| 1309 | trc_write(state[i++], ETMSSCSR2); |
| 1310 | trc_write(state[i++], ETMSSPCICR2); |
| 1311 | break; |
| 1312 | case 3: |
| 1313 | trc_write(state[i++], ETMSSCCR3); |
| 1314 | trc_write(state[i++], ETMSSCSR3); |
| 1315 | trc_write(state[i++], ETMSSPCICR3); |
| 1316 | break; |
| 1317 | case 4: |
| 1318 | trc_write(state[i++], ETMSSCCR4); |
| 1319 | trc_write(state[i++], ETMSSCSR4); |
| 1320 | trc_write(state[i++], ETMSSPCICR4); |
| 1321 | break; |
| 1322 | case 5: |
| 1323 | trc_write(state[i++], ETMSSCCR5); |
| 1324 | trc_write(state[i++], ETMSSCSR5); |
| 1325 | trc_write(state[i++], ETMSSPCICR5); |
| 1326 | break; |
| 1327 | case 6: |
| 1328 | trc_write(state[i++], ETMSSCCR6); |
| 1329 | trc_write(state[i++], ETMSSCSR6); |
| 1330 | trc_write(state[i++], ETMSSPCICR6); |
| 1331 | break; |
| 1332 | case 7: |
| 1333 | trc_write(state[i++], ETMSSCCR7); |
| 1334 | trc_write(state[i++], ETMSSCSR7); |
| 1335 | trc_write(state[i++], ETMSSPCICR7); |
| 1336 | break; |
| 1337 | default: |
| 1338 | pr_err_ratelimited("idx %d out of bounds in %s\n", j, __func__); |
| 1339 | } |
| 1340 | return i; |
| 1341 | } |
| 1342 | |
| 1343 | static inline void etm_si_restore_state(struct etm_ctx *etmdata) |
| 1344 | { |
| 1345 | int i, j; |
| 1346 | |
| 1347 | i = 0; |
| 1348 | |
| 1349 | /* Vote for ETM power/clock enable */ |
| 1350 | etm_clk_enable(); |
| 1351 | |
| 1352 | switch (etmdata->arch) { |
| 1353 | case ETM_ARCH_V4_2: |
| 1354 | case ETM_ARCH_V4: |
| 1355 | atomic_notifier_call_chain(&etm_restore_notifier_list, 0, NULL); |
| 1356 | |
| 1357 | /* check OS lock is locked */ |
| 1358 | if (BVAL(trc_readl(ETMOSLSR), 1) != 1) { |
| 1359 | pr_err_ratelimited("OS lock is unlocked\n"); |
| 1360 | trc_write(0x1, ETMOSLAR); |
| 1361 | isb(); |
| 1362 | } |
| 1363 | |
| 1364 | /* main control and configuration registers */ |
| 1365 | trc_write(etmdata->state[i++], ETMCONFIGR); |
| 1366 | trc_write(etmdata->state[i++], ETMEVENTCTL0R); |
| 1367 | trc_write(etmdata->state[i++], ETMEVENTCTL1R); |
| 1368 | trc_write(etmdata->state[i++], ETMSTALLCTLR); |
| 1369 | trc_write(etmdata->state[i++], ETMTSCTLR); |
| 1370 | trc_write(etmdata->state[i++], ETMSYNCPR); |
| 1371 | trc_write(etmdata->state[i++], ETMCCCTLR); |
| 1372 | trc_write(etmdata->state[i++], ETMTRACEIDR); |
| 1373 | /* filtering control registers */ |
| 1374 | trc_write(etmdata->state[i++], ETMVICTLR); |
| 1375 | trc_write(etmdata->state[i++], ETMVIIECTLR); |
| 1376 | trc_write(etmdata->state[i++], ETMVISSCTLR); |
| 1377 | /* derived resources registers */ |
| 1378 | for (j = 0; j < etmdata->nr_seq_state-1; j++) |
| 1379 | i = etm_write_ssxr(etmdata->state, i, j); |
| 1380 | trc_write(etmdata->state[i++], ETMSEQRSTEVR); |
| 1381 | trc_write(etmdata->state[i++], ETMSEQSTR); |
| 1382 | trc_write(etmdata->state[i++], ETMEXTINSELR); |
| 1383 | for (j = 0; j < etmdata->nr_cntr; j++) |
| 1384 | i = etm_write_crxr(etmdata->state, i, j); |
| 1385 | /* resource selection registers */ |
| 1386 | for (j = 0; j < etmdata->nr_resource; j++) |
| 1387 | i = etm_write_rsxr(etmdata->state, i, j + 2); |
| 1388 | /* comparator registers */ |
| 1389 | for (j = 0; j < etmdata->nr_addr_cmp * 2; j++) |
| 1390 | i = etm_write_acr(etmdata->state, i, j); |
| 1391 | for (j = 0; j < etmdata->nr_data_cmp; j++) |
| 1392 | i = etm_write_dvcr(etmdata->state, i, j); |
| 1393 | for (j = 0; j < etmdata->nr_ctxid_cmp; j++) |
| 1394 | i = etm_write_ccvr(etmdata->state, i, j); |
| 1395 | trc_write(etmdata->state[i++], ETMCIDCCTLR0); |
| 1396 | for (j = 0; j < etmdata->nr_vmid_cmp; j++) |
| 1397 | i = etm_write_vcvr(etmdata->state, i, j); |
| 1398 | /* single-shot comparator registers */ |
| 1399 | for (j = 0; j < etmdata->nr_ss_cmp; j++) |
| 1400 | i = etm_write_sscr(etmdata->state, i, j); |
| 1401 | /* program ctrl register */ |
| 1402 | trc_write(etmdata->state[i++], ETMPRGCTLR); |
| 1403 | |
| 1404 | isb(); |
| 1405 | trc_write(0x0, ETMOSLAR); |
| 1406 | break; |
| 1407 | default: |
| 1408 | pr_err_ratelimited("unsupported etm arch %d in %s\n", |
| 1409 | etmdata->arch, __func__); |
| 1410 | } |
| 1411 | |
| 1412 | /* Vote for ETM power/clock disable */ |
| 1413 | etm_clk_disable(); |
| 1414 | } |
| 1415 | |
| 1416 | void msm_jtag_etm_save_state(void) |
| 1417 | { |
| 1418 | int cpu; |
| 1419 | |
| 1420 | cpu = raw_smp_processor_id(); |
| 1421 | |
| 1422 | if (!etm[cpu] || etm[cpu]->save_restore_disabled) |
| 1423 | return; |
| 1424 | |
| 1425 | if (etm[cpu]->save_restore_enabled) { |
| 1426 | if (etm[cpu]->si_enable) |
| 1427 | etm_si_save_state(etm[cpu]); |
| 1428 | else |
| 1429 | etm_mm_save_state(etm[cpu]); |
| 1430 | } |
| 1431 | } |
| 1432 | EXPORT_SYMBOL(msm_jtag_etm_save_state); |
| 1433 | |
| 1434 | void msm_jtag_etm_restore_state(void) |
| 1435 | { |
| 1436 | int cpu; |
| 1437 | |
| 1438 | cpu = raw_smp_processor_id(); |
| 1439 | |
| 1440 | if (!etm[cpu] || etm[cpu]->save_restore_disabled) |
| 1441 | return; |
| 1442 | |
| 1443 | /* |
| 1444 | * Check to ensure we attempt to restore only when save |
| 1445 | * has been done is accomplished by callee function. |
| 1446 | */ |
| 1447 | if (etm[cpu]->save_restore_enabled) { |
| 1448 | if (etm[cpu]->si_enable) |
| 1449 | etm_si_restore_state(etm[cpu]); |
| 1450 | else |
| 1451 | etm_mm_restore_state(etm[cpu]); |
| 1452 | } |
| 1453 | } |
| 1454 | EXPORT_SYMBOL(msm_jtag_etm_restore_state); |
| 1455 | |
| 1456 | static inline bool etm_arch_supported(uint8_t arch) |
| 1457 | { |
| 1458 | switch (arch) { |
| 1459 | case ETM_ARCH_V4_2: |
| 1460 | case ETM_ARCH_V4: |
| 1461 | break; |
| 1462 | default: |
| 1463 | return false; |
| 1464 | } |
| 1465 | return true; |
| 1466 | } |
| 1467 | |
| 1468 | static void etm_os_lock_init(struct etm_ctx *etmdata) |
| 1469 | { |
| 1470 | uint32_t etmoslsr; |
| 1471 | |
| 1472 | etmoslsr = etm_readl(etmdata, TRCOSLSR); |
| 1473 | if ((BVAL(etmoslsr, 0) == 0) && BVAL(etmoslsr, 3)) |
| 1474 | etmdata->os_lock_present = true; |
| 1475 | else |
| 1476 | etmdata->os_lock_present = false; |
| 1477 | } |
| 1478 | |
| 1479 | static void etm_init_arch_data(void *info) |
| 1480 | { |
| 1481 | uint32_t val; |
| 1482 | struct etm_ctx *etmdata = info; |
| 1483 | |
| 1484 | ETM_UNLOCK(etmdata); |
| 1485 | |
| 1486 | etm_os_lock_init(etmdata); |
| 1487 | |
| 1488 | val = etm_readl(etmdata, TRCIDR1); |
| 1489 | etmdata->arch = BMVAL(val, 4, 11); |
| 1490 | |
| 1491 | /* number of resources trace unit supports */ |
| 1492 | val = etm_readl(etmdata, TRCIDR4); |
| 1493 | etmdata->nr_addr_cmp = BMVAL(val, 0, 3); |
| 1494 | etmdata->nr_data_cmp = BMVAL(val, 4, 7); |
| 1495 | etmdata->nr_resource = BMVAL(val, 16, 19); |
| 1496 | etmdata->nr_ss_cmp = BMVAL(val, 20, 23); |
| 1497 | etmdata->nr_ctxid_cmp = BMVAL(val, 24, 27); |
| 1498 | etmdata->nr_vmid_cmp = BMVAL(val, 28, 31); |
| 1499 | |
| 1500 | val = etm_readl(etmdata, TRCIDR5); |
| 1501 | etmdata->nr_seq_state = BMVAL(val, 25, 27); |
| 1502 | etmdata->nr_cntr = BMVAL(val, 28, 30); |
| 1503 | |
| 1504 | ETM_LOCK(etmdata); |
| 1505 | } |
| 1506 | |
| 1507 | static int jtag_mm_etm_starting(unsigned int cpu) |
| 1508 | { |
| 1509 | if (!etm[cpu]) |
| 1510 | return 0; |
| 1511 | |
| 1512 | spin_lock(&etm[cpu]->spinlock); |
| 1513 | if (!etm[cpu]->init) { |
| 1514 | etm_init_arch_data(etm[cpu]); |
| 1515 | etm[cpu]->init = true; |
| 1516 | } |
| 1517 | spin_unlock(&etm[cpu]->spinlock); |
| 1518 | |
| 1519 | return 0; |
| 1520 | } |
| 1521 | |
| 1522 | static int jtag_mm_etm_online(unsigned int cpu) |
| 1523 | { |
| 1524 | if (!etm[cpu]) |
| 1525 | return 0; |
| 1526 | |
| 1527 | mutex_lock(&etm[cpu]->mutex); |
| 1528 | if (etm[cpu]->enable) { |
| 1529 | mutex_unlock(&etm[cpu]->mutex); |
| 1530 | return 0; |
| 1531 | } |
| 1532 | if (etm_arch_supported(etm[cpu]->arch)) { |
| 1533 | if (scm_get_feat_version(TZ_DBG_ETM_FEAT_ID) < |
| 1534 | TZ_DBG_ETM_VER) |
| 1535 | etm[cpu]->save_restore_enabled = true; |
| 1536 | else |
| 1537 | pr_info("etm save-restore supported by TZ\n"); |
| 1538 | } else |
| 1539 | pr_info("etm arch %u not supported\n", etm[cpu]->arch); |
| 1540 | etm[cpu]->enable = true; |
| 1541 | mutex_unlock(&etm[cpu]->mutex); |
| 1542 | |
| 1543 | return 0; |
| 1544 | } |
| 1545 | |
| 1546 | static bool skip_etm_save_restore(void) |
| 1547 | { |
| 1548 | uint32_t id; |
| 1549 | uint32_t version; |
| 1550 | |
| 1551 | id = socinfo_get_id(); |
| 1552 | version = socinfo_get_version(); |
| 1553 | |
| 1554 | if (id == HW_SOC_ID_M8953 && SOCINFO_VERSION_MAJOR(version) == 1 && |
| 1555 | SOCINFO_VERSION_MINOR(version) == 0) |
| 1556 | return true; |
| 1557 | |
| 1558 | return false; |
| 1559 | } |
| 1560 | |
| 1561 | static int jtag_mm_etm_probe(struct platform_device *pdev, uint32_t cpu) |
| 1562 | { |
| 1563 | struct etm_ctx *etmdata; |
| 1564 | struct resource *res; |
| 1565 | struct device *dev = &pdev->dev; |
| 1566 | int ret; |
| 1567 | |
| 1568 | /* Allocate memory per cpu */ |
| 1569 | etmdata = devm_kzalloc(dev, sizeof(struct etm_ctx), GFP_KERNEL); |
| 1570 | if (!etmdata) |
| 1571 | return -ENOMEM; |
| 1572 | |
| 1573 | |
| 1574 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "etm-base"); |
| 1575 | if (!res) |
| 1576 | return -ENODEV; |
| 1577 | |
| 1578 | etmdata->base = devm_ioremap(dev, res->start, resource_size(res)); |
| 1579 | if (!etmdata->base) |
| 1580 | return -EINVAL; |
| 1581 | |
| 1582 | etmdata->si_enable = of_property_read_bool(pdev->dev.of_node, |
| 1583 | "qcom,si-enable"); |
| 1584 | etmdata->save_restore_disabled = of_property_read_bool( |
| 1585 | pdev->dev.of_node, |
| 1586 | "qcom,save-restore-disable"); |
| 1587 | |
| 1588 | if (skip_etm_save_restore()) |
| 1589 | etmdata->save_restore_disabled = 1; |
| 1590 | |
| 1591 | /* Allocate etm state save space per core */ |
| 1592 | etmdata->state = devm_kzalloc(dev, |
| 1593 | MAX_ETM_STATE_SIZE * sizeof(uint64_t), |
| 1594 | GFP_KERNEL); |
| 1595 | if (!etmdata->state) |
| 1596 | return -ENOMEM; |
| 1597 | |
| 1598 | spin_lock_init(&etmdata->spinlock); |
| 1599 | mutex_init(&etmdata->mutex); |
| 1600 | |
| 1601 | if (cnt++ == 0) { |
| 1602 | cpuhp_setup_state_nocalls(CPUHP_AP_ARM_MM_CORESIGHT4_STARTING, |
| 1603 | "AP_ARM_CORESIGHT4_STARTING", |
| 1604 | jtag_mm_etm_starting, NULL); |
| 1605 | ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, |
| 1606 | "AP_ARM_CORESIGHT4_ONLINE", |
| 1607 | jtag_mm_etm_online, NULL); |
| 1608 | } |
| 1609 | |
| 1610 | get_online_cpus(); |
| 1611 | |
| 1612 | if (!smp_call_function_single(cpu, etm_init_arch_data, etmdata, |
| 1613 | 1)) |
| 1614 | etmdata->init = true; |
| 1615 | |
| 1616 | etm[cpu] = etmdata; |
| 1617 | |
| 1618 | put_online_cpus(); |
| 1619 | |
| 1620 | mutex_lock(&etmdata->mutex); |
| 1621 | if (etmdata->init && !etmdata->enable) { |
| 1622 | if (etm_arch_supported(etmdata->arch)) { |
| 1623 | if (scm_get_feat_version(TZ_DBG_ETM_FEAT_ID) < |
| 1624 | TZ_DBG_ETM_VER) |
| 1625 | etmdata->save_restore_enabled = true; |
| 1626 | else |
| 1627 | pr_info("etm save-restore supported by TZ\n"); |
| 1628 | } else |
| 1629 | pr_info("etm arch %u not supported\n", etmdata->arch); |
| 1630 | etmdata->enable = true; |
| 1631 | } |
| 1632 | mutex_unlock(&etmdata->mutex); |
| 1633 | return 0; |
| 1634 | } |
| 1635 | |
| 1636 | static int jtag_mm_probe(struct platform_device *pdev) |
| 1637 | { |
| 1638 | int ret, i, cpu = -1; |
| 1639 | struct device *dev = &pdev->dev; |
| 1640 | struct device_node *cpu_node; |
| 1641 | |
| 1642 | cpu_node = of_parse_phandle(pdev->dev.of_node, |
| 1643 | "qcom,coresight-jtagmm-cpu", 0); |
| 1644 | if (!cpu_node) { |
| 1645 | dev_err(dev, "Jtag-mm cpu handle not specified\n"); |
| 1646 | return -ENODEV; |
| 1647 | } |
| 1648 | for_each_possible_cpu(i) { |
| 1649 | if (cpu_node == of_get_cpu_node(i, NULL)) { |
| 1650 | cpu = i; |
| 1651 | break; |
| 1652 | } |
| 1653 | } |
| 1654 | |
| 1655 | if (cpu == -1) { |
| 1656 | dev_err(dev, "invalid Jtag-mm cpu handle\n"); |
| 1657 | return -EINVAL; |
| 1658 | } |
| 1659 | |
| 1660 | clock[cpu] = devm_clk_get(dev, "core_clk"); |
| 1661 | if (IS_ERR(clock[cpu])) { |
| 1662 | ret = PTR_ERR(clock[cpu]); |
| 1663 | return ret; |
| 1664 | } |
| 1665 | |
| 1666 | ret = clk_prepare_enable(clock[cpu]); |
| 1667 | if (ret) |
| 1668 | return ret; |
| 1669 | |
| 1670 | platform_set_drvdata(pdev, clock[cpu]); |
| 1671 | |
| 1672 | ret = jtag_mm_etm_probe(pdev, cpu); |
| 1673 | if (ret) |
| 1674 | clk_disable_unprepare(clock[cpu]); |
| 1675 | |
| 1676 | return ret; |
| 1677 | } |
| 1678 | |
| 1679 | static void jtag_mm_etm_remove(void) |
| 1680 | { |
| 1681 | cpuhp_remove_state_nocalls(CPUHP_AP_ARM_MM_CORESIGHT4_STARTING); |
| 1682 | } |
| 1683 | |
| 1684 | static int jtag_mm_remove(struct platform_device *pdev) |
| 1685 | { |
| 1686 | struct clk *clock = platform_get_drvdata(pdev); |
| 1687 | |
| 1688 | if (--cnt == 0) |
| 1689 | jtag_mm_etm_remove(); |
| 1690 | clk_disable_unprepare(clock); |
| 1691 | return 0; |
| 1692 | } |
| 1693 | |
| 1694 | static const struct of_device_id msm_qdss_mm_match[] = { |
| 1695 | { .compatible = "qcom,jtagv8-mm"}, |
| 1696 | {} |
| 1697 | }; |
| 1698 | |
| 1699 | static struct platform_driver jtag_mm_driver = { |
| 1700 | .probe = jtag_mm_probe, |
| 1701 | .remove = jtag_mm_remove, |
| 1702 | .driver = { |
| 1703 | .name = "msm-jtagv8-mm", |
| 1704 | .owner = THIS_MODULE, |
| 1705 | .of_match_table = msm_qdss_mm_match, |
| 1706 | }, |
| 1707 | }; |
| 1708 | |
| 1709 | static int __init jtag_mm_init(void) |
| 1710 | { |
| 1711 | return platform_driver_register(&jtag_mm_driver); |
| 1712 | } |
| 1713 | module_init(jtag_mm_init); |
| 1714 | |
| 1715 | static void __exit jtag_mm_exit(void) |
| 1716 | { |
| 1717 | platform_driver_unregister(&jtag_mm_driver); |
| 1718 | } |
| 1719 | module_exit(jtag_mm_exit); |
| 1720 | |
| 1721 | MODULE_LICENSE("GPL v2"); |
| 1722 | MODULE_DESCRIPTION("CoreSight DEBUGv8 and ETMv4 save-restore driver"); |