Satyajit Desai | 66b6c45 | 2017-06-27 17:10:46 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2014-2017, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/module.h> |
| 15 | #include <linux/clk.h> |
| 16 | #include <linux/delay.h> |
| 17 | #include <linux/init.h> |
| 18 | #include <linux/types.h> |
| 19 | #include <linux/err.h> |
| 20 | #include <linux/slab.h> |
| 21 | #include <linux/smp.h> |
| 22 | #include <linux/cpu.h> |
| 23 | #include <linux/cpu_pm.h> |
| 24 | #include <linux/export.h> |
| 25 | #include <linux/printk.h> |
| 26 | #include <linux/ratelimit.h> |
| 27 | #include <linux/coresight.h> |
| 28 | #include <linux/io.h> |
| 29 | #include <linux/platform_device.h> |
| 30 | #include <linux/bitops.h> |
| 31 | #include <soc/qcom/scm.h> |
| 32 | #include <soc/qcom/jtag.h> |
| 33 | #ifdef CONFIG_ARM64 |
| 34 | #include <asm/debugv8.h> |
| 35 | #else |
| 36 | #include <asm/hardware/debugv8.h> |
| 37 | #endif |
| 38 | |
| 39 | #define TIMEOUT_US (100) |
| 40 | |
| 41 | #define BM(lsb, msb) ((BIT(msb) - BIT(lsb)) + BIT(msb)) |
| 42 | #define BMVAL(val, lsb, msb) ((val & BM(lsb, msb)) >> lsb) |
| 43 | #define BVAL(val, n) ((val & BIT(n)) >> n) |
| 44 | |
| 45 | #ifdef CONFIG_ARM64 |
| 46 | #define ARM_DEBUG_ARCH_V8_8 (0x8) |
| 47 | #define ARM_DEBUG_ARCH_V8 (0x6) |
| 48 | #endif |
| 49 | |
| 50 | #define MAX_DBG_REGS (66) |
| 51 | #define MAX_DBG_STATE_SIZE (MAX_DBG_REGS * num_possible_cpus()) |
| 52 | |
| 53 | #define OSLOCK_MAGIC (0xC5ACCE55) |
| 54 | #define TZ_DBG_ETM_FEAT_ID (0x8) |
| 55 | #define TZ_DBG_ETM_VER (0x400000) |
| 56 | |
| 57 | static uint32_t msm_jtag_save_cntr[NR_CPUS]; |
| 58 | static uint32_t msm_jtag_restore_cntr[NR_CPUS]; |
| 59 | |
| 60 | /* access debug registers using system instructions */ |
| 61 | struct dbg_cpu_ctx { |
| 62 | uint32_t *state; |
| 63 | }; |
| 64 | |
| 65 | struct dbg_ctx { |
| 66 | uint8_t arch; |
| 67 | bool save_restore_enabled; |
| 68 | uint8_t nr_wp; |
| 69 | uint8_t nr_bp; |
| 70 | uint8_t nr_ctx_cmp; |
| 71 | #ifdef CONFIG_ARM64 |
| 72 | uint64_t *state; |
| 73 | #else |
| 74 | uint32_t *state; |
| 75 | #endif |
| 76 | }; |
| 77 | |
| 78 | static struct dbg_ctx dbg; |
| 79 | static struct notifier_block jtag_cpu_pm_notifier; |
| 80 | |
| 81 | #ifdef CONFIG_ARM64 |
| 82 | static int dbg_read_arch64_bxr(uint64_t *state, int i, int j) |
| 83 | { |
| 84 | switch (j) { |
| 85 | case 0: |
| 86 | state[i++] = dbg_readq(DBGBVR0_EL1); |
| 87 | state[i++] = (uint64_t)dbg_readl(DBGBCR0_EL1); |
| 88 | break; |
| 89 | case 1: |
| 90 | state[i++] = dbg_readq(DBGBVR1_EL1); |
| 91 | state[i++] = (uint64_t)dbg_readl(DBGBCR1_EL1); |
| 92 | break; |
| 93 | case 2: |
| 94 | state[i++] = dbg_readq(DBGBVR2_EL1); |
| 95 | state[i++] = (uint64_t)dbg_readl(DBGBCR2_EL1); |
| 96 | break; |
| 97 | case 3: |
| 98 | state[i++] = dbg_readq(DBGBVR3_EL1); |
| 99 | state[i++] = (uint64_t)dbg_readl(DBGBCR3_EL1); |
| 100 | break; |
| 101 | case 4: |
| 102 | state[i++] = dbg_readq(DBGBVR4_EL1); |
| 103 | state[i++] = (uint64_t)dbg_readl(DBGBCR4_EL1); |
| 104 | break; |
| 105 | case 5: |
| 106 | state[i++] = dbg_readq(DBGBVR5_EL1); |
| 107 | state[i++] = (uint64_t)dbg_readl(DBGBCR5_EL1); |
| 108 | break; |
| 109 | case 6: |
| 110 | state[i++] = dbg_readq(DBGBVR6_EL1); |
| 111 | state[i++] = (uint64_t)dbg_readl(DBGBCR6_EL1); |
| 112 | break; |
| 113 | case 7: |
| 114 | state[i++] = dbg_readq(DBGBVR7_EL1); |
| 115 | state[i++] = (uint64_t)dbg_readl(DBGBCR7_EL1); |
| 116 | break; |
| 117 | case 8: |
| 118 | state[i++] = dbg_readq(DBGBVR8_EL1); |
| 119 | state[i++] = (uint64_t)dbg_readl(DBGBCR8_EL1); |
| 120 | break; |
| 121 | case 9: |
| 122 | state[i++] = dbg_readq(DBGBVR9_EL1); |
| 123 | state[i++] = (uint64_t)dbg_readl(DBGBCR9_EL1); |
| 124 | break; |
| 125 | case 10: |
| 126 | state[i++] = dbg_readq(DBGBVR10_EL1); |
| 127 | state[i++] = (uint64_t)dbg_readl(DBGBCR10_EL1); |
| 128 | break; |
| 129 | case 11: |
| 130 | state[i++] = dbg_readq(DBGBVR11_EL1); |
| 131 | state[i++] = (uint64_t)dbg_readl(DBGBCR11_EL1); |
| 132 | break; |
| 133 | case 12: |
| 134 | state[i++] = dbg_readq(DBGBVR12_EL1); |
| 135 | state[i++] = (uint64_t)dbg_readl(DBGBCR12_EL1); |
| 136 | break; |
| 137 | case 13: |
| 138 | state[i++] = dbg_readq(DBGBVR13_EL1); |
| 139 | state[i++] = (uint64_t)dbg_readl(DBGBCR13_EL1); |
| 140 | break; |
| 141 | case 14: |
| 142 | state[i++] = dbg_readq(DBGBVR14_EL1); |
| 143 | state[i++] = (uint64_t)dbg_readl(DBGBCR14_EL1); |
| 144 | break; |
| 145 | case 15: |
| 146 | state[i++] = dbg_readq(DBGBVR15_EL1); |
| 147 | state[i++] = (uint64_t)dbg_readl(DBGBCR15_EL1); |
| 148 | break; |
| 149 | default: |
| 150 | pr_err_ratelimited("idx %d out of bounds in %s\n", j, __func__); |
| 151 | } |
| 152 | return i; |
| 153 | } |
| 154 | |
| 155 | static int dbg_write_arch64_bxr(uint64_t *state, int i, int j) |
| 156 | { |
| 157 | switch (j) { |
| 158 | case 0: |
| 159 | dbg_write(state[i++], DBGBVR0_EL1); |
| 160 | dbg_write(state[i++], DBGBCR0_EL1); |
| 161 | break; |
| 162 | case 1: |
| 163 | dbg_write(state[i++], DBGBVR1_EL1); |
| 164 | dbg_write(state[i++], DBGBCR1_EL1); |
| 165 | break; |
| 166 | case 2: |
| 167 | dbg_write(state[i++], DBGBVR2_EL1); |
| 168 | dbg_write(state[i++], DBGBCR2_EL1); |
| 169 | break; |
| 170 | case 3: |
| 171 | dbg_write(state[i++], DBGBVR3_EL1); |
| 172 | dbg_write(state[i++], DBGBCR3_EL1); |
| 173 | break; |
| 174 | case 4: |
| 175 | dbg_write(state[i++], DBGBVR4_EL1); |
| 176 | dbg_write(state[i++], DBGBCR4_EL1); |
| 177 | break; |
| 178 | case 5: |
| 179 | dbg_write(state[i++], DBGBVR5_EL1); |
| 180 | dbg_write(state[i++], DBGBCR5_EL1); |
| 181 | break; |
| 182 | case 6: |
| 183 | dbg_write(state[i++], DBGBVR6_EL1); |
| 184 | dbg_write(state[i++], DBGBCR6_EL1); |
| 185 | break; |
| 186 | case 7: |
| 187 | dbg_write(state[i++], DBGBVR7_EL1); |
| 188 | dbg_write(state[i++], DBGBCR7_EL1); |
| 189 | break; |
| 190 | case 8: |
| 191 | dbg_write(state[i++], DBGBVR8_EL1); |
| 192 | dbg_write(state[i++], DBGBCR8_EL1); |
| 193 | break; |
| 194 | case 9: |
| 195 | dbg_write(state[i++], DBGBVR9_EL1); |
| 196 | dbg_write(state[i++], DBGBCR9_EL1); |
| 197 | break; |
| 198 | case 10: |
| 199 | dbg_write(state[i++], DBGBVR10_EL1); |
| 200 | dbg_write(state[i++], DBGBCR10_EL1); |
| 201 | break; |
| 202 | case 11: |
| 203 | dbg_write(state[i++], DBGBVR11_EL1); |
| 204 | dbg_write(state[i++], DBGBCR11_EL1); |
| 205 | break; |
| 206 | case 12: |
| 207 | dbg_write(state[i++], DBGBVR12_EL1); |
| 208 | dbg_write(state[i++], DBGBCR12_EL1); |
| 209 | break; |
| 210 | case 13: |
| 211 | dbg_write(state[i++], DBGBVR13_EL1); |
| 212 | dbg_write(state[i++], DBGBCR13_EL1); |
| 213 | break; |
| 214 | case 14: |
| 215 | dbg_write(state[i++], DBGBVR14_EL1); |
| 216 | dbg_write(state[i++], DBGBCR14_EL1); |
| 217 | break; |
| 218 | case 15: |
| 219 | dbg_write(state[i++], DBGBVR15_EL1); |
| 220 | dbg_write(state[i++], DBGBCR15_EL1); |
| 221 | break; |
| 222 | default: |
| 223 | pr_err_ratelimited("idx %d out of bounds in %s\n", j, __func__); |
| 224 | } |
| 225 | return i; |
| 226 | } |
| 227 | |
| 228 | static int dbg_read_arch64_wxr(uint64_t *state, int i, int j) |
| 229 | { |
| 230 | switch (j) { |
| 231 | case 0: |
| 232 | state[i++] = dbg_readq(DBGWVR0_EL1); |
| 233 | state[i++] = (uint64_t)dbg_readl(DBGWCR0_EL1); |
| 234 | break; |
| 235 | case 1: |
| 236 | state[i++] = dbg_readq(DBGWVR1_EL1); |
| 237 | state[i++] = (uint64_t)dbg_readl(DBGWCR1_EL1); |
| 238 | break; |
| 239 | case 2: |
| 240 | state[i++] = dbg_readq(DBGWVR2_EL1); |
| 241 | state[i++] = (uint64_t)dbg_readl(DBGWCR2_EL1); |
| 242 | break; |
| 243 | case 3: |
| 244 | state[i++] = dbg_readq(DBGWVR3_EL1); |
| 245 | state[i++] = (uint64_t)dbg_readl(DBGWCR3_EL1); |
| 246 | break; |
| 247 | case 4: |
| 248 | state[i++] = dbg_readq(DBGWVR4_EL1); |
| 249 | state[i++] = (uint64_t)dbg_readl(DBGWCR4_EL1); |
| 250 | break; |
| 251 | case 5: |
| 252 | state[i++] = dbg_readq(DBGWVR5_EL1); |
| 253 | state[i++] = (uint64_t)dbg_readl(DBGWCR5_EL1); |
| 254 | break; |
| 255 | case 6: |
| 256 | state[i++] = dbg_readq(DBGWVR6_EL1); |
| 257 | state[i++] = (uint64_t)dbg_readl(DBGWCR6_EL1); |
| 258 | break; |
| 259 | case 7: |
| 260 | state[i++] = dbg_readq(DBGWVR7_EL1); |
| 261 | state[i++] = (uint64_t)dbg_readl(DBGWCR7_EL1); |
| 262 | break; |
| 263 | case 8: |
| 264 | state[i++] = dbg_readq(DBGWVR8_EL1); |
| 265 | state[i++] = (uint64_t)dbg_readl(DBGWCR8_EL1); |
| 266 | break; |
| 267 | case 9: |
| 268 | state[i++] = dbg_readq(DBGWVR9_EL1); |
| 269 | state[i++] = (uint64_t)dbg_readl(DBGWCR9_EL1); |
| 270 | break; |
| 271 | case 10: |
| 272 | state[i++] = dbg_readq(DBGWVR10_EL1); |
| 273 | state[i++] = (uint64_t)dbg_readl(DBGWCR10_EL1); |
| 274 | break; |
| 275 | case 11: |
| 276 | state[i++] = dbg_readq(DBGWVR11_EL1); |
| 277 | state[i++] = (uint64_t)dbg_readl(DBGWCR11_EL1); |
| 278 | break; |
| 279 | case 12: |
| 280 | state[i++] = dbg_readq(DBGWVR12_EL1); |
| 281 | state[i++] = (uint64_t)dbg_readl(DBGWCR12_EL1); |
| 282 | break; |
| 283 | case 13: |
| 284 | state[i++] = dbg_readq(DBGWVR13_EL1); |
| 285 | state[i++] = (uint64_t)dbg_readl(DBGWCR13_EL1); |
| 286 | break; |
| 287 | case 14: |
| 288 | state[i++] = dbg_readq(DBGWVR14_EL1); |
| 289 | state[i++] = (uint64_t)dbg_readl(DBGWCR14_EL1); |
| 290 | break; |
| 291 | case 15: |
| 292 | state[i++] = dbg_readq(DBGWVR15_EL1); |
| 293 | state[i++] = (uint64_t)dbg_readl(DBGWCR15_EL1); |
| 294 | break; |
| 295 | default: |
| 296 | pr_err_ratelimited("idx %d out of bounds in %s\n", j, __func__); |
| 297 | } |
| 298 | return i; |
| 299 | } |
| 300 | |
| 301 | static int dbg_write_arch64_wxr(uint64_t *state, int i, int j) |
| 302 | { |
| 303 | switch (j) { |
| 304 | case 0: |
| 305 | dbg_write(state[i++], DBGWVR0_EL1); |
| 306 | dbg_write(state[i++], DBGWCR0_EL1); |
| 307 | break; |
| 308 | case 1: |
| 309 | dbg_write(state[i++], DBGWVR1_EL1); |
| 310 | dbg_write(state[i++], DBGWCR1_EL1); |
| 311 | break; |
| 312 | case 2: |
| 313 | dbg_write(state[i++], DBGWVR2_EL1); |
| 314 | dbg_write(state[i++], DBGWCR2_EL1); |
| 315 | break; |
| 316 | case 3: |
| 317 | dbg_write(state[i++], DBGWVR3_EL1); |
| 318 | dbg_write(state[i++], DBGWCR3_EL1); |
| 319 | break; |
| 320 | case 4: |
| 321 | dbg_write(state[i++], DBGWVR4_EL1); |
| 322 | dbg_write(state[i++], DBGWCR4_EL1); |
| 323 | break; |
| 324 | case 5: |
| 325 | dbg_write(state[i++], DBGWVR5_EL1); |
| 326 | dbg_write(state[i++], DBGWCR5_EL1); |
| 327 | break; |
| 328 | case 6: |
| 329 | dbg_write(state[i++], DBGWVR0_EL1); |
| 330 | dbg_write(state[i++], DBGWCR6_EL1); |
| 331 | break; |
| 332 | case 7: |
| 333 | dbg_write(state[i++], DBGWVR7_EL1); |
| 334 | dbg_write(state[i++], DBGWCR7_EL1); |
| 335 | break; |
| 336 | case 8: |
| 337 | dbg_write(state[i++], DBGWVR8_EL1); |
| 338 | dbg_write(state[i++], DBGWCR8_EL1); |
| 339 | break; |
| 340 | case 9: |
| 341 | dbg_write(state[i++], DBGWVR9_EL1); |
| 342 | dbg_write(state[i++], DBGWCR9_EL1); |
| 343 | break; |
| 344 | case 10: |
| 345 | dbg_write(state[i++], DBGWVR10_EL1); |
| 346 | dbg_write(state[i++], DBGWCR10_EL1); |
| 347 | break; |
| 348 | case 11: |
| 349 | dbg_write(state[i++], DBGWVR11_EL1); |
| 350 | dbg_write(state[i++], DBGWCR11_EL1); |
| 351 | break; |
| 352 | case 12: |
| 353 | dbg_write(state[i++], DBGWVR12_EL1); |
| 354 | dbg_write(state[i++], DBGWCR12_EL1); |
| 355 | break; |
| 356 | case 13: |
| 357 | dbg_write(state[i++], DBGWVR13_EL1); |
| 358 | dbg_write(state[i++], DBGWCR13_EL1); |
| 359 | break; |
| 360 | case 14: |
| 361 | dbg_write(state[i++], DBGWVR14_EL1); |
| 362 | dbg_write(state[i++], DBGWCR14_EL1); |
| 363 | break; |
| 364 | case 15: |
| 365 | dbg_write(state[i++], DBGWVR15_EL1); |
| 366 | dbg_write(state[i++], DBGWCR15_EL1); |
| 367 | break; |
| 368 | default: |
| 369 | pr_err_ratelimited("idx %d out of bounds in %s\n", j, __func__); |
| 370 | } |
| 371 | return i; |
| 372 | } |
| 373 | |
| 374 | static inline void dbg_save_state(int cpu) |
| 375 | { |
| 376 | int i, j; |
| 377 | |
| 378 | i = cpu * MAX_DBG_REGS; |
| 379 | |
| 380 | switch (dbg.arch) { |
| 381 | case ARM_DEBUG_ARCH_V8_8: |
| 382 | case ARM_DEBUG_ARCH_V8: |
| 383 | /* Set OS Lock to inform the debugger that the OS is in the |
| 384 | * process of saving debug registers. It prevents accidental |
| 385 | * modification of the debug regs by the external debugger. |
| 386 | */ |
| 387 | dbg_write(0x1, OSLAR_EL1); |
| 388 | /* Ensure OS lock is set before proceeding */ |
| 389 | isb(); |
| 390 | |
| 391 | dbg.state[i++] = (uint32_t)dbg_readl(MDSCR_EL1); |
| 392 | for (j = 0; j < dbg.nr_bp; j++) |
| 393 | i = dbg_read_arch64_bxr((uint64_t *)dbg.state, i, j); |
| 394 | for (j = 0; j < dbg.nr_wp; j++) |
| 395 | i = dbg_read_arch64_wxr((uint64_t *)dbg.state, i, j); |
| 396 | dbg.state[i++] = (uint32_t)dbg_readl(MDCCINT_EL1); |
| 397 | dbg.state[i++] = (uint32_t)dbg_readl(DBGCLAIMCLR_EL1); |
| 398 | dbg.state[i++] = (uint32_t)dbg_readl(OSECCR_EL1); |
| 399 | dbg.state[i++] = (uint32_t)dbg_readl(OSDTRRX_EL1); |
| 400 | dbg.state[i++] = (uint32_t)dbg_readl(OSDTRTX_EL1); |
| 401 | |
| 402 | /* Set the OS double lock */ |
| 403 | isb(); |
| 404 | dbg_write(0x1, OSDLR_EL1); |
| 405 | isb(); |
| 406 | break; |
| 407 | default: |
| 408 | pr_err_ratelimited("unsupported dbg arch %d in %s\n", dbg.arch, |
| 409 | __func__); |
| 410 | } |
| 411 | } |
| 412 | |
| 413 | static inline void dbg_restore_state(int cpu) |
| 414 | { |
| 415 | int i, j; |
| 416 | |
| 417 | i = cpu * MAX_DBG_REGS; |
| 418 | |
| 419 | switch (dbg.arch) { |
| 420 | case ARM_DEBUG_ARCH_V8_8: |
| 421 | case ARM_DEBUG_ARCH_V8: |
| 422 | /* Clear the OS double lock */ |
| 423 | isb(); |
| 424 | dbg_write(0x0, OSDLR_EL1); |
| 425 | isb(); |
| 426 | |
| 427 | /* Set OS lock. Lock will already be set after power collapse |
| 428 | * but this write is included to ensure it is set. |
| 429 | */ |
| 430 | dbg_write(0x1, OSLAR_EL1); |
| 431 | isb(); |
| 432 | |
| 433 | dbg_write(dbg.state[i++], MDSCR_EL1); |
| 434 | for (j = 0; j < dbg.nr_bp; j++) |
| 435 | i = dbg_write_arch64_bxr((uint64_t *)dbg.state, i, j); |
| 436 | for (j = 0; j < dbg.nr_wp; j++) |
| 437 | i = dbg_write_arch64_wxr((uint64_t *)dbg.state, i, j); |
| 438 | dbg_write(dbg.state[i++], MDCCINT_EL1); |
| 439 | dbg_write(dbg.state[i++], DBGCLAIMSET_EL1); |
| 440 | dbg_write(dbg.state[i++], OSECCR_EL1); |
| 441 | dbg_write(dbg.state[i++], OSDTRRX_EL1); |
| 442 | dbg_write(dbg.state[i++], OSDTRTX_EL1); |
| 443 | |
| 444 | isb(); |
| 445 | dbg_write(0x0, OSLAR_EL1); |
| 446 | isb(); |
| 447 | break; |
| 448 | default: |
| 449 | pr_err_ratelimited("unsupported dbg arch %d in %s\n", dbg.arch, |
| 450 | __func__); |
| 451 | } |
| 452 | } |
| 453 | |
| 454 | static void dbg_init_arch_data(void) |
| 455 | { |
| 456 | uint64_t dbgfr; |
| 457 | |
| 458 | /* This will run on core0 so use it to populate parameters */ |
| 459 | dbgfr = dbg_readq(ID_AA64DFR0_EL1); |
| 460 | dbg.arch = BMVAL(dbgfr, 0, 3); |
| 461 | dbg.nr_bp = BMVAL(dbgfr, 12, 15) + 1; |
| 462 | dbg.nr_wp = BMVAL(dbgfr, 20, 23) + 1; |
| 463 | dbg.nr_ctx_cmp = BMVAL(dbgfr, 28, 31) + 1; |
| 464 | } |
| 465 | #else |
| 466 | |
| 467 | static int dbg_read_arch32_bxr(uint32_t *state, int i, int j) |
| 468 | { |
| 469 | switch (j) { |
| 470 | case 0: |
| 471 | state[i++] = dbg_read(DBGBVR0); |
| 472 | state[i++] = dbg_read(DBGBCR0); |
| 473 | break; |
| 474 | case 1: |
| 475 | state[i++] = dbg_read(DBGBVR1); |
| 476 | state[i++] = dbg_read(DBGBCR1); |
| 477 | break; |
| 478 | case 2: |
| 479 | state[i++] = dbg_read(DBGBVR2); |
| 480 | state[i++] = dbg_read(DBGBCR2); |
| 481 | break; |
| 482 | case 3: |
| 483 | state[i++] = dbg_read(DBGBVR3); |
| 484 | state[i++] = dbg_read(DBGBCR3); |
| 485 | break; |
| 486 | case 4: |
| 487 | state[i++] = dbg_read(DBGBVR4); |
| 488 | state[i++] = dbg_read(DBGBCR4); |
| 489 | break; |
| 490 | case 5: |
| 491 | state[i++] = dbg_read(DBGBVR5); |
| 492 | state[i++] = dbg_read(DBGBCR5); |
| 493 | break; |
| 494 | case 6: |
| 495 | state[i++] = dbg_read(DBGBVR6); |
| 496 | state[i++] = dbg_read(DBGBCR6); |
| 497 | break; |
| 498 | case 7: |
| 499 | state[i++] = dbg_read(DBGBVR7); |
| 500 | state[i++] = dbg_read(DBGBCR7); |
| 501 | break; |
| 502 | case 8: |
| 503 | state[i++] = dbg_read(DBGBVR8); |
| 504 | state[i++] = dbg_read(DBGBCR8); |
| 505 | break; |
| 506 | case 9: |
| 507 | state[i++] = dbg_read(DBGBVR9); |
| 508 | state[i++] = dbg_read(DBGBCR9); |
| 509 | break; |
| 510 | case 10: |
| 511 | state[i++] = dbg_read(DBGBVR10); |
| 512 | state[i++] = dbg_read(DBGBCR10); |
| 513 | break; |
| 514 | case 11: |
| 515 | state[i++] = dbg_read(DBGBVR11); |
| 516 | state[i++] = dbg_read(DBGBCR11); |
| 517 | break; |
| 518 | case 12: |
| 519 | state[i++] = dbg_read(DBGBVR12); |
| 520 | state[i++] = dbg_read(DBGBCR12); |
| 521 | break; |
| 522 | case 13: |
| 523 | state[i++] = dbg_read(DBGBVR13); |
| 524 | state[i++] = dbg_read(DBGBCR13); |
| 525 | break; |
| 526 | case 14: |
| 527 | state[i++] = dbg_read(DBGBVR14); |
| 528 | state[i++] = dbg_read(DBGBCR14); |
| 529 | break; |
| 530 | case 15: |
| 531 | state[i++] = dbg_read(DBGBVR15); |
| 532 | state[i++] = dbg_read(DBGBCR15); |
| 533 | break; |
| 534 | default: |
| 535 | pr_err_ratelimited("idx %d out of bounds in %s\n", j, __func__); |
| 536 | } |
| 537 | return i; |
| 538 | } |
| 539 | |
| 540 | static int dbg_write_arch32_bxr(uint32_t *state, int i, int j) |
| 541 | { |
| 542 | switch (j) { |
| 543 | case 0: |
| 544 | dbg_write(state[i++], DBGBVR0); |
| 545 | dbg_write(state[i++], DBGBCR0); |
| 546 | break; |
| 547 | case 1: |
| 548 | dbg_write(state[i++], DBGBVR1); |
| 549 | dbg_write(state[i++], DBGBCR1); |
| 550 | break; |
| 551 | case 2: |
| 552 | dbg_write(state[i++], DBGBVR2); |
| 553 | dbg_write(state[i++], DBGBCR2); |
| 554 | break; |
| 555 | case 3: |
| 556 | dbg_write(state[i++], DBGBVR3); |
| 557 | dbg_write(state[i++], DBGBCR3); |
| 558 | break; |
| 559 | case 4: |
| 560 | dbg_write(state[i++], DBGBVR4); |
| 561 | dbg_write(state[i++], DBGBCR4); |
| 562 | break; |
| 563 | case 5: |
| 564 | dbg_write(state[i++], DBGBVR5); |
| 565 | dbg_write(state[i++], DBGBCR5); |
| 566 | break; |
| 567 | case 6: |
| 568 | dbg_write(state[i++], DBGBVR6); |
| 569 | dbg_write(state[i++], DBGBCR6); |
| 570 | break; |
| 571 | case 7: |
| 572 | dbg_write(state[i++], DBGBVR7); |
| 573 | dbg_write(state[i++], DBGBCR7); |
| 574 | break; |
| 575 | case 8: |
| 576 | dbg_write(state[i++], DBGBVR8); |
| 577 | dbg_write(state[i++], DBGBCR8); |
| 578 | break; |
| 579 | case 9: |
| 580 | dbg_write(state[i++], DBGBVR9); |
| 581 | dbg_write(state[i++], DBGBCR9); |
| 582 | break; |
| 583 | case 10: |
| 584 | dbg_write(state[i++], DBGBVR10); |
| 585 | dbg_write(state[i++], DBGBCR10); |
| 586 | break; |
| 587 | case 11: |
| 588 | dbg_write(state[i++], DBGBVR11); |
| 589 | dbg_write(state[i++], DBGBCR11); |
| 590 | break; |
| 591 | case 12: |
| 592 | dbg_write(state[i++], DBGBVR12); |
| 593 | dbg_write(state[i++], DBGBCR12); |
| 594 | break; |
| 595 | case 13: |
| 596 | dbg_write(state[i++], DBGBVR13); |
| 597 | dbg_write(state[i++], DBGBCR13); |
| 598 | break; |
| 599 | case 14: |
| 600 | dbg_write(state[i++], DBGBVR14); |
| 601 | dbg_write(state[i++], DBGBCR14); |
| 602 | break; |
| 603 | case 15: |
| 604 | dbg_write(state[i++], DBGBVR15); |
| 605 | dbg_write(state[i++], DBGBCR15); |
| 606 | break; |
| 607 | default: |
| 608 | pr_err_ratelimited("idx %d out of bounds in %s\n", j, __func__); |
| 609 | } |
| 610 | return i; |
| 611 | } |
| 612 | |
| 613 | static int dbg_read_arch32_wxr(uint32_t *state, int i, int j) |
| 614 | { |
| 615 | switch (j) { |
| 616 | case 0: |
| 617 | state[i++] = dbg_read(DBGWVR0); |
| 618 | state[i++] = dbg_read(DBGWCR0); |
| 619 | break; |
| 620 | case 1: |
| 621 | state[i++] = dbg_read(DBGWVR1); |
| 622 | state[i++] = dbg_read(DBGWCR1); |
| 623 | break; |
| 624 | case 2: |
| 625 | state[i++] = dbg_read(DBGWVR2); |
| 626 | state[i++] = dbg_read(DBGWCR2); |
| 627 | break; |
| 628 | case 3: |
| 629 | state[i++] = dbg_read(DBGWVR3); |
| 630 | state[i++] = dbg_read(DBGWCR3); |
| 631 | break; |
| 632 | case 4: |
| 633 | state[i++] = dbg_read(DBGWVR4); |
| 634 | state[i++] = dbg_read(DBGWCR4); |
| 635 | break; |
| 636 | case 5: |
| 637 | state[i++] = dbg_read(DBGWVR5); |
| 638 | state[i++] = dbg_read(DBGWCR5); |
| 639 | break; |
| 640 | case 6: |
| 641 | state[i++] = dbg_read(DBGWVR6); |
| 642 | state[i++] = dbg_read(DBGWCR6); |
| 643 | break; |
| 644 | case 7: |
| 645 | state[i++] = dbg_read(DBGWVR7); |
| 646 | state[i++] = dbg_read(DBGWCR7); |
| 647 | break; |
| 648 | case 8: |
| 649 | state[i++] = dbg_read(DBGWVR8); |
| 650 | state[i++] = dbg_read(DBGWCR8); |
| 651 | break; |
| 652 | case 9: |
| 653 | state[i++] = dbg_read(DBGWVR9); |
| 654 | state[i++] = dbg_read(DBGWCR9); |
| 655 | break; |
| 656 | case 10: |
| 657 | state[i++] = dbg_read(DBGWVR10); |
| 658 | state[i++] = dbg_read(DBGWCR10); |
| 659 | break; |
| 660 | case 11: |
| 661 | state[i++] = dbg_read(DBGWVR11); |
| 662 | state[i++] = dbg_read(DBGWCR11); |
| 663 | break; |
| 664 | case 12: |
| 665 | state[i++] = dbg_read(DBGWVR12); |
| 666 | state[i++] = dbg_read(DBGWCR12); |
| 667 | break; |
| 668 | case 13: |
| 669 | state[i++] = dbg_read(DBGWVR13); |
| 670 | state[i++] = dbg_read(DBGWCR13); |
| 671 | break; |
| 672 | case 14: |
| 673 | state[i++] = dbg_read(DBGWVR14); |
| 674 | state[i++] = dbg_read(DBGWCR14); |
| 675 | break; |
| 676 | case 15: |
| 677 | state[i++] = dbg_read(DBGWVR15); |
| 678 | state[i++] = dbg_read(DBGWCR15); |
| 679 | break; |
| 680 | default: |
| 681 | pr_err_ratelimited("idx %d out of bounds in %s\n", j, __func__); |
| 682 | } |
| 683 | return i; |
| 684 | } |
| 685 | |
| 686 | static int dbg_write_arch32_wxr(uint32_t *state, int i, int j) |
| 687 | { |
| 688 | switch (j) { |
| 689 | case 0: |
| 690 | dbg_write(state[i++], DBGWVR0); |
| 691 | dbg_write(state[i++], DBGWCR0); |
| 692 | break; |
| 693 | case 1: |
| 694 | dbg_write(state[i++], DBGWVR1); |
| 695 | dbg_write(state[i++], DBGWCR1); |
| 696 | break; |
| 697 | case 2: |
| 698 | dbg_write(state[i++], DBGWVR2); |
| 699 | dbg_write(state[i++], DBGWCR2); |
| 700 | break; |
| 701 | case 3: |
| 702 | dbg_write(state[i++], DBGWVR3); |
| 703 | dbg_write(state[i++], DBGWCR3); |
| 704 | break; |
| 705 | case 4: |
| 706 | dbg_write(state[i++], DBGWVR4); |
| 707 | dbg_write(state[i++], DBGWCR4); |
| 708 | break; |
| 709 | case 5: |
| 710 | dbg_write(state[i++], DBGWVR5); |
| 711 | dbg_write(state[i++], DBGWCR5); |
| 712 | break; |
| 713 | case 6: |
| 714 | dbg_write(state[i++], DBGWVR6); |
| 715 | dbg_write(state[i++], DBGWCR6); |
| 716 | break; |
| 717 | case 7: |
| 718 | dbg_write(state[i++], DBGWVR7); |
| 719 | dbg_write(state[i++], DBGWCR7); |
| 720 | break; |
| 721 | case 8: |
| 722 | dbg_write(state[i++], DBGWVR8); |
| 723 | dbg_write(state[i++], DBGWCR8); |
| 724 | break; |
| 725 | case 9: |
| 726 | dbg_write(state[i++], DBGWVR9); |
| 727 | dbg_write(state[i++], DBGWCR9); |
| 728 | break; |
| 729 | case 10: |
| 730 | dbg_write(state[i++], DBGWVR10); |
| 731 | dbg_write(state[i++], DBGWCR10); |
| 732 | break; |
| 733 | case 11: |
| 734 | dbg_write(state[i++], DBGWVR11); |
| 735 | dbg_write(state[i++], DBGWCR11); |
| 736 | break; |
| 737 | case 12: |
| 738 | dbg_write(state[i++], DBGWVR12); |
| 739 | dbg_write(state[i++], DBGWCR12); |
| 740 | break; |
| 741 | case 13: |
| 742 | dbg_write(state[i++], DBGWVR13); |
| 743 | dbg_write(state[i++], DBGWCR13); |
| 744 | break; |
| 745 | case 14: |
| 746 | dbg_write(state[i++], DBGWVR14); |
| 747 | dbg_write(state[i++], DBGWCR14); |
| 748 | break; |
| 749 | case 15: |
| 750 | dbg_write(state[i++], DBGWVR15); |
| 751 | dbg_write(state[i++], DBGWCR15); |
| 752 | break; |
| 753 | default: |
| 754 | pr_err_ratelimited("idx %d out of bounds in %s\n", j, __func__); |
| 755 | } |
| 756 | return i; |
| 757 | } |
| 758 | |
| 759 | static inline void dbg_save_state(int cpu) |
| 760 | { |
| 761 | int i, j; |
| 762 | |
| 763 | i = cpu * MAX_DBG_REGS; |
| 764 | |
| 765 | switch (dbg.arch) { |
| 766 | case ARM_DEBUG_ARCH_V8_8: |
| 767 | case ARM_DEBUG_ARCH_V8: |
| 768 | /* Set OS Lock to inform the debugger that the OS is in the |
| 769 | * process of saving debug registers. It prevents accidental |
| 770 | * modification of the debug regs by the external debugger. |
| 771 | */ |
| 772 | dbg_write(OSLOCK_MAGIC, DBGOSLAR); |
| 773 | /* Ensure OS lock is set before proceeding */ |
| 774 | isb(); |
| 775 | |
| 776 | dbg.state[i++] = dbg_read(DBGDSCRext); |
| 777 | for (j = 0; j < dbg.nr_bp; j++) |
| 778 | i = dbg_read_arch32_bxr(dbg.state, i, j); |
| 779 | for (j = 0; j < dbg.nr_wp; j++) |
| 780 | i = dbg_read_arch32_wxr(dbg.state, i, j); |
| 781 | dbg.state[i++] = dbg_read(DBGDCCINT); |
| 782 | dbg.state[i++] = dbg_read(DBGCLAIMCLR); |
| 783 | dbg.state[i++] = dbg_read(DBGOSECCR); |
| 784 | dbg.state[i++] = dbg_read(DBGDTRRXext); |
| 785 | dbg.state[i++] = dbg_read(DBGDTRTXext); |
| 786 | |
| 787 | /* Set the OS double lock */ |
| 788 | isb(); |
| 789 | dbg_write(0x1, DBGOSDLR); |
| 790 | isb(); |
| 791 | break; |
| 792 | default: |
| 793 | pr_err_ratelimited("unsupported dbg arch %d in %s\n", dbg.arch, |
| 794 | __func__); |
| 795 | } |
| 796 | } |
| 797 | |
| 798 | static inline void dbg_restore_state(int cpu) |
| 799 | { |
| 800 | int i, j; |
| 801 | |
| 802 | i = cpu * MAX_DBG_REGS; |
| 803 | |
| 804 | switch (dbg.arch) { |
| 805 | case ARM_DEBUG_ARCH_V8_8: |
| 806 | case ARM_DEBUG_ARCH_V8: |
| 807 | /* Clear the OS double lock */ |
| 808 | isb(); |
| 809 | dbg_write(0x0, DBGOSDLR); |
| 810 | isb(); |
| 811 | |
| 812 | /* Set OS lock. Lock will already be set after power collapse |
| 813 | * but this write is included to ensure it is set. |
| 814 | */ |
| 815 | dbg_write(OSLOCK_MAGIC, DBGOSLAR); |
| 816 | isb(); |
| 817 | |
| 818 | dbg_write(dbg.state[i++], DBGDSCRext); |
| 819 | for (j = 0; j < dbg.nr_bp; j++) |
| 820 | i = dbg_write_arch32_bxr((uint32_t *)dbg.state, i, j); |
| 821 | for (j = 0; j < dbg.nr_wp; j++) |
| 822 | i = dbg_write_arch32_wxr((uint32_t *)dbg.state, i, j); |
| 823 | dbg_write(dbg.state[i++], DBGDCCINT); |
| 824 | dbg_write(dbg.state[i++], DBGCLAIMSET); |
| 825 | dbg_write(dbg.state[i++], DBGOSECCR); |
| 826 | dbg_write(dbg.state[i++], DBGDTRRXext); |
| 827 | dbg_write(dbg.state[i++], DBGDTRTXext); |
| 828 | |
| 829 | isb(); |
| 830 | dbg_write(0x0, DBGOSLAR); |
| 831 | isb(); |
| 832 | break; |
| 833 | default: |
| 834 | pr_err_ratelimited("unsupported dbg arch %d in %s\n", dbg.arch, |
| 835 | __func__); |
| 836 | } |
| 837 | } |
| 838 | |
| 839 | static void dbg_init_arch_data(void) |
| 840 | { |
| 841 | uint32_t dbgdidr; |
| 842 | |
| 843 | /* This will run on core0 so use it to populate parameters */ |
| 844 | dbgdidr = dbg_read(DBGDIDR); |
| 845 | dbg.arch = BMVAL(dbgdidr, 16, 19); |
| 846 | dbg.nr_ctx_cmp = BMVAL(dbgdidr, 20, 23) + 1; |
| 847 | dbg.nr_bp = BMVAL(dbgdidr, 24, 27) + 1; |
| 848 | dbg.nr_wp = BMVAL(dbgdidr, 28, 31) + 1; |
| 849 | } |
| 850 | #endif |
| 851 | |
| 852 | /* |
| 853 | * msm_jtag_save_state - save debug registers |
| 854 | * |
| 855 | * Debug registers are saved before power collapse if debug |
| 856 | * architecture is supported respectively and TZ isn't supporting |
| 857 | * the save and restore of debug registers. |
| 858 | * |
| 859 | * CONTEXT: |
| 860 | * Called with preemption off and interrupts locked from: |
| 861 | * 1. per_cpu idle thread context for idle power collapses |
| 862 | * or |
| 863 | * 2. per_cpu idle thread context for hotplug/suspend power collapse |
| 864 | * for nonboot cpus |
| 865 | * or |
| 866 | * 3. suspend thread context for suspend power collapse for core0 |
| 867 | * |
| 868 | * In all cases we will run on the same cpu for the entire duration. |
| 869 | */ |
| 870 | void msm_jtag_save_state(void) |
| 871 | { |
| 872 | int cpu; |
| 873 | |
| 874 | cpu = raw_smp_processor_id(); |
| 875 | |
| 876 | msm_jtag_save_cntr[cpu]++; |
| 877 | /* ensure counter is updated before moving forward */ |
| 878 | mb(); |
| 879 | |
| 880 | msm_jtag_etm_save_state(); |
| 881 | if (dbg.save_restore_enabled) |
| 882 | dbg_save_state(cpu); |
| 883 | } |
| 884 | EXPORT_SYMBOL(msm_jtag_save_state); |
| 885 | |
| 886 | void msm_jtag_restore_state(void) |
| 887 | { |
| 888 | int cpu; |
| 889 | |
| 890 | cpu = raw_smp_processor_id(); |
| 891 | |
| 892 | /* Attempt restore only if save has been done. If power collapse |
| 893 | * is disabled, hotplug off of non-boot core will result in WFI |
| 894 | * and hence msm_jtag_save_state will not occur. Subsequently, |
| 895 | * during hotplug on of non-boot core when msm_jtag_restore_state |
| 896 | * is called via msm_platform_secondary_init, this check will help |
| 897 | * bail us out without restoring. |
| 898 | */ |
| 899 | if (msm_jtag_save_cntr[cpu] == msm_jtag_restore_cntr[cpu]) |
| 900 | return; |
| 901 | else if (msm_jtag_save_cntr[cpu] != msm_jtag_restore_cntr[cpu] + 1) |
| 902 | pr_err_ratelimited("jtag imbalance, save:%lu, restore:%lu\n", |
| 903 | (unsigned long)msm_jtag_save_cntr[cpu], |
| 904 | (unsigned long)msm_jtag_restore_cntr[cpu]); |
| 905 | |
| 906 | msm_jtag_restore_cntr[cpu]++; |
| 907 | /* ensure counter is updated before moving forward */ |
| 908 | mb(); |
| 909 | |
| 910 | if (dbg.save_restore_enabled) |
| 911 | dbg_restore_state(cpu); |
| 912 | msm_jtag_etm_restore_state(); |
| 913 | } |
| 914 | EXPORT_SYMBOL(msm_jtag_restore_state); |
| 915 | |
| 916 | static inline bool dbg_arch_supported(uint8_t arch) |
| 917 | { |
| 918 | switch (arch) { |
| 919 | case ARM_DEBUG_ARCH_V8_8: |
| 920 | case ARM_DEBUG_ARCH_V8: |
| 921 | break; |
| 922 | default: |
| 923 | return false; |
| 924 | } |
| 925 | return true; |
| 926 | } |
| 927 | |
| 928 | static int jtag_hotcpu_save_callback(unsigned int cpu) |
| 929 | { |
| 930 | msm_jtag_save_state(); |
| 931 | return 0; |
| 932 | } |
| 933 | |
| 934 | static int jtag_hotcpu_restore_callback(unsigned int cpu) |
| 935 | { |
| 936 | msm_jtag_restore_state(); |
| 937 | return 0; |
| 938 | } |
| 939 | |
| 940 | static int jtag_cpu_pm_callback(struct notifier_block *nfb, |
| 941 | unsigned long action, void *hcpu) |
| 942 | { |
| 943 | switch (action) { |
| 944 | case CPU_PM_ENTER: |
| 945 | msm_jtag_save_state(); |
| 946 | break; |
| 947 | case CPU_PM_ENTER_FAILED: |
| 948 | case CPU_PM_EXIT: |
| 949 | msm_jtag_restore_state(); |
| 950 | break; |
| 951 | } |
| 952 | return NOTIFY_OK; |
| 953 | } |
| 954 | |
| 955 | static struct notifier_block jtag_cpu_pm_notifier = { |
| 956 | .notifier_call = jtag_cpu_pm_callback, |
| 957 | }; |
| 958 | |
| 959 | static int __init msm_jtag_dbg_init(void) |
| 960 | { |
| 961 | int ret; |
| 962 | |
| 963 | /* This will run on core0 so use it to populate parameters */ |
| 964 | dbg_init_arch_data(); |
| 965 | |
| 966 | if (dbg_arch_supported(dbg.arch)) { |
| 967 | if (scm_get_feat_version(TZ_DBG_ETM_FEAT_ID) < TZ_DBG_ETM_VER) { |
| 968 | dbg.save_restore_enabled = true; |
| 969 | } else { |
| 970 | pr_info("dbg save-restore supported by TZ\n"); |
| 971 | goto dbg_out; |
| 972 | } |
| 973 | } else { |
| 974 | pr_info("dbg arch %u not supported\n", dbg.arch); |
| 975 | goto dbg_out; |
| 976 | } |
| 977 | |
| 978 | /* Allocate dbg state save space */ |
| 979 | #ifdef CONFIG_ARM64 |
| 980 | dbg.state = kcalloc(MAX_DBG_STATE_SIZE, sizeof(uint64_t), GFP_KERNEL); |
| 981 | #else |
| 982 | dbg.state = kcalloc(MAX_DBG_STATE_SIZE, sizeof(uint32_t), GFP_KERNEL); |
| 983 | #endif |
| 984 | if (!dbg.state) { |
| 985 | ret = -ENOMEM; |
| 986 | goto dbg_err; |
| 987 | } |
| 988 | |
| 989 | cpuhp_setup_state_nocalls(CPUHP_AP_ARM_SAVE_RESTORE_CORESIGHT4_STARTING, |
| 990 | "AP_ARM_SAVE_RESTORE_CORESIGHT4_STARTING", |
| 991 | jtag_hotcpu_restore_callback, |
| 992 | jtag_hotcpu_save_callback); |
| 993 | |
| 994 | cpu_pm_register_notifier(&jtag_cpu_pm_notifier); |
| 995 | dbg_out: |
| 996 | return 0; |
| 997 | dbg_err: |
| 998 | return ret; |
| 999 | } |
| 1000 | arch_initcall(msm_jtag_dbg_init); |