Anatol Pomozov | 34ca27f | 2015-10-02 09:49:14 -0700 | [diff] [blame] | 1 | /* |
| 2 | * NAU8825 ALSA SoC audio driver |
| 3 | * |
| 4 | * Copyright 2015 Google Inc. |
| 5 | * Author: Anatol Pomozov <anatol.pomozov@chrominium.org> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | */ |
| 11 | |
| 12 | #ifndef __NAU8825_H__ |
| 13 | #define __NAU8825_H__ |
| 14 | |
| 15 | #define NAU8825_REG_RESET 0x00 |
| 16 | #define NAU8825_REG_ENA_CTRL 0x01 |
John Hsu | 45d5eb3 | 2016-03-11 17:33:58 -0800 | [diff] [blame] | 17 | #define NAU8825_REG_IIC_ADDR_SET 0x02 |
Anatol Pomozov | 34ca27f | 2015-10-02 09:49:14 -0700 | [diff] [blame] | 18 | #define NAU8825_REG_CLK_DIVIDER 0x03 |
| 19 | #define NAU8825_REG_FLL1 0x04 |
| 20 | #define NAU8825_REG_FLL2 0x05 |
| 21 | #define NAU8825_REG_FLL3 0x06 |
| 22 | #define NAU8825_REG_FLL4 0x07 |
| 23 | #define NAU8825_REG_FLL5 0x08 |
| 24 | #define NAU8825_REG_FLL6 0x09 |
| 25 | #define NAU8825_REG_FLL_VCO_RSV 0x0a |
| 26 | #define NAU8825_REG_HSD_CTRL 0x0c |
| 27 | #define NAU8825_REG_JACK_DET_CTRL 0x0d |
| 28 | #define NAU8825_REG_INTERRUPT_MASK 0x0f |
| 29 | #define NAU8825_REG_IRQ_STATUS 0x10 |
| 30 | #define NAU8825_REG_INT_CLR_KEY_STATUS 0x11 |
| 31 | #define NAU8825_REG_INTERRUPT_DIS_CTRL 0x12 |
| 32 | #define NAU8825_REG_SAR_CTRL 0x13 |
| 33 | #define NAU8825_REG_KEYDET_CTRL 0x14 |
| 34 | #define NAU8825_REG_VDET_THRESHOLD_1 0x15 |
| 35 | #define NAU8825_REG_VDET_THRESHOLD_2 0x16 |
| 36 | #define NAU8825_REG_VDET_THRESHOLD_3 0x17 |
| 37 | #define NAU8825_REG_VDET_THRESHOLD_4 0x18 |
| 38 | #define NAU8825_REG_GPIO34_CTRL 0x19 |
| 39 | #define NAU8825_REG_GPIO12_CTRL 0x1a |
| 40 | #define NAU8825_REG_TDM_CTRL 0x1b |
| 41 | #define NAU8825_REG_I2S_PCM_CTRL1 0x1c |
| 42 | #define NAU8825_REG_I2S_PCM_CTRL2 0x1d |
| 43 | #define NAU8825_REG_LEFT_TIME_SLOT 0x1e |
| 44 | #define NAU8825_REG_RIGHT_TIME_SLOT 0x1f |
| 45 | #define NAU8825_REG_BIQ_CTRL 0x20 |
| 46 | #define NAU8825_REG_BIQ_COF1 0x21 |
| 47 | #define NAU8825_REG_BIQ_COF2 0x22 |
| 48 | #define NAU8825_REG_BIQ_COF3 0x23 |
| 49 | #define NAU8825_REG_BIQ_COF4 0x24 |
| 50 | #define NAU8825_REG_BIQ_COF5 0x25 |
| 51 | #define NAU8825_REG_BIQ_COF6 0x26 |
| 52 | #define NAU8825_REG_BIQ_COF7 0x27 |
| 53 | #define NAU8825_REG_BIQ_COF8 0x28 |
| 54 | #define NAU8825_REG_BIQ_COF9 0x29 |
| 55 | #define NAU8825_REG_BIQ_COF10 0x2a |
| 56 | #define NAU8825_REG_ADC_RATE 0x2b |
| 57 | #define NAU8825_REG_DAC_CTRL1 0x2c |
| 58 | #define NAU8825_REG_DAC_CTRL2 0x2d |
| 59 | #define NAU8825_REG_DAC_DGAIN_CTRL 0x2f |
| 60 | #define NAU8825_REG_ADC_DGAIN_CTRL 0x30 |
| 61 | #define NAU8825_REG_MUTE_CTRL 0x31 |
| 62 | #define NAU8825_REG_HSVOL_CTRL 0x32 |
| 63 | #define NAU8825_REG_DACL_CTRL 0x33 |
| 64 | #define NAU8825_REG_DACR_CTRL 0x34 |
| 65 | #define NAU8825_REG_ADC_DRC_KNEE_IP12 0x38 |
| 66 | #define NAU8825_REG_ADC_DRC_KNEE_IP34 0x39 |
| 67 | #define NAU8825_REG_ADC_DRC_SLOPES 0x3a |
| 68 | #define NAU8825_REG_ADC_DRC_ATKDCY 0x3b |
| 69 | #define NAU8825_REG_DAC_DRC_KNEE_IP12 0x45 |
| 70 | #define NAU8825_REG_DAC_DRC_KNEE_IP34 0x46 |
| 71 | #define NAU8825_REG_DAC_DRC_SLOPES 0x47 |
| 72 | #define NAU8825_REG_DAC_DRC_ATKDCY 0x48 |
| 73 | #define NAU8825_REG_IMM_MODE_CTRL 0x4c |
| 74 | #define NAU8825_REG_IMM_RMS_L 0x4d |
| 75 | #define NAU8825_REG_IMM_RMS_R 0x4e |
| 76 | #define NAU8825_REG_CLASSG_CTRL 0x50 |
| 77 | #define NAU8825_REG_OPT_EFUSE_CTRL 0x51 |
| 78 | #define NAU8825_REG_MISC_CTRL 0x55 |
| 79 | #define NAU8825_REG_I2C_DEVICE_ID 0x58 |
| 80 | #define NAU8825_REG_SARDOUT_RAM_STATUS 0x59 |
| 81 | #define NAU8825_REG_BIAS_ADJ 0x66 |
| 82 | #define NAU8825_REG_TRIM_SETTINGS 0x68 |
| 83 | #define NAU8825_REG_ANALOG_CONTROL_1 0x69 |
| 84 | #define NAU8825_REG_ANALOG_CONTROL_2 0x6a |
| 85 | #define NAU8825_REG_ANALOG_ADC_1 0x71 |
| 86 | #define NAU8825_REG_ANALOG_ADC_2 0x72 |
| 87 | #define NAU8825_REG_RDAC 0x73 |
| 88 | #define NAU8825_REG_MIC_BIAS 0x74 |
| 89 | #define NAU8825_REG_BOOST 0x76 |
| 90 | #define NAU8825_REG_FEPGA 0x77 |
| 91 | #define NAU8825_REG_POWER_UP_CONTROL 0x7f |
| 92 | #define NAU8825_REG_CHARGE_PUMP 0x80 |
| 93 | #define NAU8825_REG_CHARGE_PUMP_INPUT_READ 0x81 |
| 94 | #define NAU8825_REG_GENERAL_STATUS 0x82 |
| 95 | #define NAU8825_REG_MAX NAU8825_REG_GENERAL_STATUS |
John Hsu | 2ec30f6 | 2016-05-23 10:25:40 +0800 | [diff] [blame] | 96 | /* 16-bit control register address, and 16-bits control register data */ |
| 97 | #define NAU8825_REG_ADDR_LEN 16 |
| 98 | #define NAU8825_REG_DATA_LEN 16 |
Anatol Pomozov | 34ca27f | 2015-10-02 09:49:14 -0700 | [diff] [blame] | 99 | |
| 100 | /* ENA_CTRL (0x1) */ |
| 101 | #define NAU8825_ENABLE_DACR_SFT 10 |
| 102 | #define NAU8825_ENABLE_DACR (1 << NAU8825_ENABLE_DACR_SFT) |
| 103 | #define NAU8825_ENABLE_DACL_SFT 9 |
John Hsu | b50455f | 2016-06-07 10:29:27 +0800 | [diff] [blame] | 104 | #define NAU8825_ENABLE_DACL (1 << NAU8825_ENABLE_DACL_SFT) |
Anatol Pomozov | 34ca27f | 2015-10-02 09:49:14 -0700 | [diff] [blame] | 105 | #define NAU8825_ENABLE_ADC_SFT 8 |
John Hsu | eeef16a | 2016-03-22 11:57:20 +0800 | [diff] [blame] | 106 | #define NAU8825_ENABLE_ADC (1 << NAU8825_ENABLE_ADC_SFT) |
John Hsu | b50455f | 2016-06-07 10:29:27 +0800 | [diff] [blame] | 107 | #define NAU8825_ENABLE_ADC_CLK_SFT 7 |
| 108 | #define NAU8825_ENABLE_ADC_CLK (1 << NAU8825_ENABLE_ADC_CLK_SFT) |
| 109 | #define NAU8825_ENABLE_DAC_CLK_SFT 6 |
| 110 | #define NAU8825_ENABLE_DAC_CLK (1 << NAU8825_ENABLE_DAC_CLK_SFT) |
Anatol Pomozov | 34ca27f | 2015-10-02 09:49:14 -0700 | [diff] [blame] | 111 | #define NAU8825_ENABLE_SAR_SFT 1 |
| 112 | |
| 113 | /* CLK_DIVIDER (0x3) */ |
Ben Zhang | c86ba61 | 2015-10-19 16:49:05 -0700 | [diff] [blame] | 114 | #define NAU8825_CLK_SRC_SFT 15 |
| 115 | #define NAU8825_CLK_SRC_MASK (1 << NAU8825_CLK_SRC_SFT) |
| 116 | #define NAU8825_CLK_SRC_VCO (1 << NAU8825_CLK_SRC_SFT) |
| 117 | #define NAU8825_CLK_SRC_MCLK (0 << NAU8825_CLK_SRC_SFT) |
| 118 | #define NAU8825_CLK_MCLK_SRC_MASK (0xf << 0) |
| 119 | |
| 120 | /* FLL1 (0x04) */ |
| 121 | #define NAU8825_FLL_RATIO_MASK (0x7f << 0) |
| 122 | |
| 123 | /* FLL3 (0x06) */ |
| 124 | #define NAU8825_FLL_INTEGER_MASK (0x3ff << 0) |
John Hsu | 70543c3 | 2016-03-15 12:08:21 +0800 | [diff] [blame] | 125 | #define NAU8825_FLL_CLK_SRC_SFT 10 |
| 126 | #define NAU8825_FLL_CLK_SRC_MASK (0x3 << NAU8825_FLL_CLK_SRC_SFT) |
| 127 | #define NAU8825_FLL_CLK_SRC_MCLK (0 << NAU8825_FLL_CLK_SRC_SFT) |
| 128 | #define NAU8825_FLL_CLK_SRC_BLK (0x2 << NAU8825_FLL_CLK_SRC_SFT) |
| 129 | #define NAU8825_FLL_CLK_SRC_FS (0x3 << NAU8825_FLL_CLK_SRC_SFT) |
Ben Zhang | c86ba61 | 2015-10-19 16:49:05 -0700 | [diff] [blame] | 130 | |
| 131 | /* FLL4 (0x07) */ |
John Hsu | c612bba | 2016-12-20 12:03:09 +0800 | [diff] [blame] | 132 | #define NAU8825_FLL_REF_DIV_SFT 10 |
| 133 | #define NAU8825_FLL_REF_DIV_MASK (0x3 << NAU8825_FLL_REF_DIV_SFT) |
Ben Zhang | c86ba61 | 2015-10-19 16:49:05 -0700 | [diff] [blame] | 134 | |
| 135 | /* FLL5 (0x08) */ |
John Hsu | 407c71b | 2016-03-15 12:09:36 +0800 | [diff] [blame] | 136 | #define NAU8825_FLL_PDB_DAC_EN (0x1 << 15) |
| 137 | #define NAU8825_FLL_LOOP_FTR_EN (0x1 << 14) |
| 138 | #define NAU8825_FLL_CLK_SW_MASK (0x1 << 13) |
| 139 | #define NAU8825_FLL_CLK_SW_N2 (0x1 << 13) |
| 140 | #define NAU8825_FLL_CLK_SW_REF (0x0 << 13) |
| 141 | #define NAU8825_FLL_FTR_SW_MASK (0x1 << 12) |
| 142 | #define NAU8825_FLL_FTR_SW_ACCU (0x1 << 12) |
| 143 | #define NAU8825_FLL_FTR_SW_FILTER (0x0 << 12) |
Anatol Pomozov | 34ca27f | 2015-10-02 09:49:14 -0700 | [diff] [blame] | 144 | |
| 145 | /* FLL6 (0x9) */ |
Ben Zhang | c86ba61 | 2015-10-19 16:49:05 -0700 | [diff] [blame] | 146 | #define NAU8825_DCO_EN (0x1 << 15) |
Ben Zhang | c86ba61 | 2015-10-19 16:49:05 -0700 | [diff] [blame] | 147 | #define NAU8825_SDM_EN (0x1 << 14) |
Anatol Pomozov | 34ca27f | 2015-10-02 09:49:14 -0700 | [diff] [blame] | 148 | |
| 149 | /* HSD_CTRL (0xc) */ |
| 150 | #define NAU8825_HSD_AUTO_MODE (1 << 6) |
John Hsu | 45d5eb3 | 2016-03-11 17:33:58 -0800 | [diff] [blame] | 151 | /* 0 - open, 1 - short to GND */ |
Anatol Pomozov | 34ca27f | 2015-10-02 09:49:14 -0700 | [diff] [blame] | 152 | #define NAU8825_SPKR_DWN1R (1 << 1) |
| 153 | #define NAU8825_SPKR_DWN1L (1 << 0) |
| 154 | |
| 155 | /* JACK_DET_CTRL (0xd) */ |
| 156 | #define NAU8825_JACK_DET_RESTART (1 << 9) |
John Hsu | 2ec30f6 | 2016-05-23 10:25:40 +0800 | [diff] [blame] | 157 | #define NAU8825_JACK_DET_DB_BYPASS (1 << 8) |
Anatol Pomozov | 34ca27f | 2015-10-02 09:49:14 -0700 | [diff] [blame] | 158 | #define NAU8825_JACK_INSERT_DEBOUNCE_SFT 5 |
| 159 | #define NAU8825_JACK_INSERT_DEBOUNCE_MASK (0x7 << NAU8825_JACK_INSERT_DEBOUNCE_SFT) |
| 160 | #define NAU8825_JACK_EJECT_DEBOUNCE_SFT 2 |
| 161 | #define NAU8825_JACK_EJECT_DEBOUNCE_MASK (0x7 << NAU8825_JACK_EJECT_DEBOUNCE_SFT) |
| 162 | #define NAU8825_JACK_POLARITY (1 << 1) /* 0 - active low, 1 - active high */ |
| 163 | |
| 164 | /* INTERRUPT_MASK (0xf) */ |
| 165 | #define NAU8825_IRQ_OUTPUT_EN (1 << 11) |
| 166 | #define NAU8825_IRQ_HEADSET_COMPLETE_EN (1 << 10) |
John Hsu | b50455f | 2016-06-07 10:29:27 +0800 | [diff] [blame] | 167 | #define NAU8825_IRQ_RMS_EN (1 << 8) |
Anatol Pomozov | 34ca27f | 2015-10-02 09:49:14 -0700 | [diff] [blame] | 168 | #define NAU8825_IRQ_KEY_RELEASE_EN (1 << 7) |
| 169 | #define NAU8825_IRQ_KEY_SHORT_PRESS_EN (1 << 5) |
| 170 | #define NAU8825_IRQ_EJECT_EN (1 << 2) |
John Hsu | 2ec30f6 | 2016-05-23 10:25:40 +0800 | [diff] [blame] | 171 | #define NAU8825_IRQ_INSERT_EN (1 << 0) |
Anatol Pomozov | 34ca27f | 2015-10-02 09:49:14 -0700 | [diff] [blame] | 172 | |
| 173 | /* IRQ_STATUS (0x10) */ |
| 174 | #define NAU8825_HEADSET_COMPLETION_IRQ (1 << 10) |
| 175 | #define NAU8825_SHORT_CIRCUIT_IRQ (1 << 9) |
| 176 | #define NAU8825_IMPEDANCE_MEAS_IRQ (1 << 8) |
| 177 | #define NAU8825_KEY_IRQ_MASK (0x7 << 5) |
| 178 | #define NAU8825_KEY_RELEASE_IRQ (1 << 7) |
| 179 | #define NAU8825_KEY_LONG_PRESS_IRQ (1 << 6) |
| 180 | #define NAU8825_KEY_SHORT_PRESS_IRQ (1 << 5) |
| 181 | #define NAU8825_MIC_DETECTION_IRQ (1 << 4) |
| 182 | #define NAU8825_JACK_EJECTION_IRQ_MASK (3 << 2) |
| 183 | #define NAU8825_JACK_EJECTION_DETECTED (1 << 2) |
| 184 | #define NAU8825_JACK_INSERTION_IRQ_MASK (3 << 0) |
| 185 | #define NAU8825_JACK_INSERTION_DETECTED (1 << 0) |
| 186 | |
| 187 | /* INTERRUPT_DIS_CTRL (0x12) */ |
| 188 | #define NAU8825_IRQ_HEADSET_COMPLETE_DIS (1 << 10) |
| 189 | #define NAU8825_IRQ_KEY_RELEASE_DIS (1 << 7) |
| 190 | #define NAU8825_IRQ_KEY_SHORT_PRESS_DIS (1 << 5) |
| 191 | #define NAU8825_IRQ_EJECT_DIS (1 << 2) |
John Hsu | 2ec30f6 | 2016-05-23 10:25:40 +0800 | [diff] [blame] | 192 | #define NAU8825_IRQ_INSERT_DIS (1 << 0) |
Anatol Pomozov | 34ca27f | 2015-10-02 09:49:14 -0700 | [diff] [blame] | 193 | |
| 194 | /* SAR_CTRL (0x13) */ |
| 195 | #define NAU8825_SAR_ADC_EN_SFT 12 |
| 196 | #define NAU8825_SAR_ADC_EN (1 << NAU8825_SAR_ADC_EN_SFT) |
| 197 | #define NAU8825_SAR_INPUT_MASK (1 << 11) |
| 198 | #define NAU8825_SAR_INPUT_JKSLV (1 << 11) |
| 199 | #define NAU8825_SAR_INPUT_JKR2 (0 << 11) |
| 200 | #define NAU8825_SAR_TRACKING_GAIN_SFT 8 |
| 201 | #define NAU8825_SAR_TRACKING_GAIN_MASK (0x7 << NAU8825_SAR_TRACKING_GAIN_SFT) |
| 202 | #define NAU8825_SAR_COMPARE_TIME_SFT 2 |
| 203 | #define NAU8825_SAR_COMPARE_TIME_MASK (3 << 2) |
| 204 | #define NAU8825_SAR_SAMPLING_TIME_SFT 0 |
| 205 | #define NAU8825_SAR_SAMPLING_TIME_MASK (3 << 0) |
| 206 | |
| 207 | /* KEYDET_CTRL (0x14) */ |
| 208 | #define NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT 12 |
| 209 | #define NAU8825_KEYDET_SHORTKEY_DEBOUNCE_MASK (0x3 << NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT) |
| 210 | #define NAU8825_KEYDET_LEVELS_NR_SFT 8 |
| 211 | #define NAU8825_KEYDET_LEVELS_NR_MASK (0x7 << 8) |
| 212 | #define NAU8825_KEYDET_HYSTERESIS_SFT 0 |
| 213 | #define NAU8825_KEYDET_HYSTERESIS_MASK 0xf |
| 214 | |
| 215 | /* GPIO12_CTRL (0x1a) */ |
| 216 | #define NAU8825_JKDET_PULL_UP (1 << 11) /* 0 - pull down, 1 - pull up */ |
| 217 | #define NAU8825_JKDET_PULL_EN (1 << 9) /* 0 - enable pull, 1 - disable */ |
| 218 | #define NAU8825_JKDET_OUTPUT_EN (1 << 8) /* 0 - enable input, 1 - enable output */ |
| 219 | |
| 220 | /* I2S_PCM_CTRL1 (0x1c) */ |
| 221 | #define NAU8825_I2S_BP_SFT 7 |
| 222 | #define NAU8825_I2S_BP_MASK (1 << NAU8825_I2S_BP_SFT) |
| 223 | #define NAU8825_I2S_BP_INV (1 << NAU8825_I2S_BP_SFT) |
| 224 | #define NAU8825_I2S_PCMB_SFT 6 |
| 225 | #define NAU8825_I2S_PCMB_MASK (1 << NAU8825_I2S_PCMB_SFT) |
| 226 | #define NAU8825_I2S_PCMB_EN (1 << NAU8825_I2S_PCMB_SFT) |
| 227 | #define NAU8825_I2S_DL_SFT 2 |
| 228 | #define NAU8825_I2S_DL_MASK (0x3 << NAU8825_I2S_DL_SFT) |
| 229 | #define NAU8825_I2S_DL_16 (0 << NAU8825_I2S_DL_SFT) |
| 230 | #define NAU8825_I2S_DL_20 (1 << NAU8825_I2S_DL_SFT) |
| 231 | #define NAU8825_I2S_DL_24 (2 << NAU8825_I2S_DL_SFT) |
| 232 | #define NAU8825_I2S_DL_32 (3 << NAU8825_I2S_DL_SFT) |
| 233 | #define NAU8825_I2S_DF_SFT 0 |
| 234 | #define NAU8825_I2S_DF_MASK (0x3 << NAU8825_I2S_DF_SFT) |
| 235 | #define NAU8825_I2S_DF_RIGTH (0 << NAU8825_I2S_DF_SFT) |
| 236 | #define NAU8825_I2S_DF_LEFT (1 << NAU8825_I2S_DF_SFT) |
| 237 | #define NAU8825_I2S_DF_I2S (2 << NAU8825_I2S_DF_SFT) |
| 238 | #define NAU8825_I2S_DF_PCM_AB (3 << NAU8825_I2S_DF_SFT) |
| 239 | |
| 240 | /* I2S_PCM_CTRL2 (0x1d) */ |
| 241 | #define NAU8825_I2S_TRISTATE (1 << 15) /* 0 - normal mode, 1 - Hi-Z output */ |
John Hsu | b50455f | 2016-06-07 10:29:27 +0800 | [diff] [blame] | 242 | #define NAU8825_I2S_DRV_SFT 12 |
| 243 | #define NAU8825_I2S_DRV_MASK (0x3 << NAU8825_I2S_DRV_SFT) |
Anatol Pomozov | 34ca27f | 2015-10-02 09:49:14 -0700 | [diff] [blame] | 244 | #define NAU8825_I2S_MS_SFT 3 |
| 245 | #define NAU8825_I2S_MS_MASK (1 << NAU8825_I2S_MS_SFT) |
| 246 | #define NAU8825_I2S_MS_MASTER (1 << NAU8825_I2S_MS_SFT) |
| 247 | #define NAU8825_I2S_MS_SLAVE (0 << NAU8825_I2S_MS_SFT) |
John Hsu | b50455f | 2016-06-07 10:29:27 +0800 | [diff] [blame] | 248 | #define NAU8825_I2S_BLK_DIV_MASK 0x7 |
Anatol Pomozov | 34ca27f | 2015-10-02 09:49:14 -0700 | [diff] [blame] | 249 | |
John Hsu | 18d8306 | 2016-05-31 11:57:41 +0800 | [diff] [blame] | 250 | /* BIQ_CTRL (0x20) */ |
| 251 | #define NAU8825_BIQ_WRT_SFT 4 |
| 252 | #define NAU8825_BIQ_WRT_EN (1 << NAU8825_BIQ_WRT_SFT) |
| 253 | #define NAU8825_BIQ_PATH_SFT 0 |
| 254 | #define NAU8825_BIQ_PATH_MASK (1 << NAU8825_BIQ_PATH_SFT) |
| 255 | #define NAU8825_BIQ_PATH_ADC (0 << NAU8825_BIQ_PATH_SFT) |
| 256 | #define NAU8825_BIQ_PATH_DAC (1 << NAU8825_BIQ_PATH_SFT) |
| 257 | |
Anatol Pomozov | 34ca27f | 2015-10-02 09:49:14 -0700 | [diff] [blame] | 258 | /* ADC_RATE (0x2b) */ |
| 259 | #define NAU8825_ADC_SYNC_DOWN_SFT 0 |
| 260 | #define NAU8825_ADC_SYNC_DOWN_MASK 0x3 |
| 261 | #define NAU8825_ADC_SYNC_DOWN_32 0 |
| 262 | #define NAU8825_ADC_SYNC_DOWN_64 1 |
| 263 | #define NAU8825_ADC_SYNC_DOWN_128 2 |
| 264 | #define NAU8825_ADC_SYNC_DOWN_256 3 |
| 265 | |
| 266 | /* DAC_CTRL1 (0x2c) */ |
| 267 | #define NAU8825_DAC_CLIP_OFF (1 << 7) |
| 268 | #define NAU8825_DAC_OVERSAMPLE_SFT 0 |
| 269 | #define NAU8825_DAC_OVERSAMPLE_MASK 0x7 |
| 270 | #define NAU8825_DAC_OVERSAMPLE_64 0 |
| 271 | #define NAU8825_DAC_OVERSAMPLE_256 1 |
| 272 | #define NAU8825_DAC_OVERSAMPLE_128 2 |
| 273 | #define NAU8825_DAC_OVERSAMPLE_32 4 |
| 274 | |
John Hsu | b50455f | 2016-06-07 10:29:27 +0800 | [diff] [blame] | 275 | /* ADC_DGAIN_CTRL (0x30) */ |
| 276 | #define NAU8825_ADC_DIG_VOL_MASK 0xff |
| 277 | |
Anatol Pomozov | 34ca27f | 2015-10-02 09:49:14 -0700 | [diff] [blame] | 278 | /* MUTE_CTRL (0x31) */ |
| 279 | #define NAU8825_DAC_ZERO_CROSSING_EN (1 << 9) |
| 280 | #define NAU8825_DAC_SOFT_MUTE (1 << 9) |
| 281 | |
| 282 | /* HSVOL_CTRL (0x32) */ |
| 283 | #define NAU8825_HP_MUTE (1 << 15) |
John Hsu | b50455f | 2016-06-07 10:29:27 +0800 | [diff] [blame] | 284 | #define NAU8825_HP_MUTE_AUTO (1 << 14) |
| 285 | #define NAU8825_HPL_MUTE (1 << 13) |
| 286 | #define NAU8825_HPR_MUTE (1 << 12) |
| 287 | #define NAU8825_HPL_VOL_SFT 6 |
| 288 | #define NAU8825_HPL_VOL_MASK (0x3f << NAU8825_HPL_VOL_SFT) |
| 289 | #define NAU8825_HPR_VOL_SFT 0 |
| 290 | #define NAU8825_HPR_VOL_MASK (0x3f << NAU8825_HPR_VOL_SFT) |
| 291 | #define NAU8825_HP_VOL_MIN 0x36 |
Anatol Pomozov | 34ca27f | 2015-10-02 09:49:14 -0700 | [diff] [blame] | 292 | |
| 293 | /* DACL_CTRL (0x33) */ |
| 294 | #define NAU8825_DACL_CH_SEL_SFT 9 |
John Hsu | 3f03916 | 2016-03-30 14:57:11 +0800 | [diff] [blame] | 295 | #define NAU8825_DACL_CH_SEL_MASK (0x1 << NAU8825_DACL_CH_SEL_SFT) |
| 296 | #define NAU8825_DACL_CH_SEL_L (0x0 << NAU8825_DACL_CH_SEL_SFT) |
| 297 | #define NAU8825_DACL_CH_SEL_R (0x1 << NAU8825_DACL_CH_SEL_SFT) |
John Hsu | b50455f | 2016-06-07 10:29:27 +0800 | [diff] [blame] | 298 | #define NAU8825_DACL_CH_VOL_MASK 0xff |
Anatol Pomozov | 34ca27f | 2015-10-02 09:49:14 -0700 | [diff] [blame] | 299 | |
| 300 | /* DACR_CTRL (0x34) */ |
| 301 | #define NAU8825_DACR_CH_SEL_SFT 9 |
John Hsu | 3f03916 | 2016-03-30 14:57:11 +0800 | [diff] [blame] | 302 | #define NAU8825_DACR_CH_SEL_MASK (0x1 << NAU8825_DACR_CH_SEL_SFT) |
| 303 | #define NAU8825_DACR_CH_SEL_L (0x0 << NAU8825_DACR_CH_SEL_SFT) |
| 304 | #define NAU8825_DACR_CH_SEL_R (0x1 << NAU8825_DACR_CH_SEL_SFT) |
John Hsu | b50455f | 2016-06-07 10:29:27 +0800 | [diff] [blame] | 305 | #define NAU8825_DACR_CH_VOL_MASK 0xff |
| 306 | |
| 307 | /* IMM_MODE_CTRL (0x4C) */ |
| 308 | #define NAU8825_IMM_THD_SFT 8 |
| 309 | #define NAU8825_IMM_THD_MASK (0x3f << NAU8825_IMM_THD_SFT) |
| 310 | #define NAU8825_IMM_GEN_VOL_SFT 6 |
| 311 | #define NAU8825_IMM_GEN_VOL_MASK (0x3 << NAU8825_IMM_GEN_VOL_SFT) |
| 312 | #define NAU8825_IMM_GEN_VOL_1_2nd (0x0 << NAU8825_IMM_GEN_VOL_SFT) |
| 313 | #define NAU8825_IMM_GEN_VOL_1_4th (0x1 << NAU8825_IMM_GEN_VOL_SFT) |
| 314 | #define NAU8825_IMM_GEN_VOL_1_8th (0x2 << NAU8825_IMM_GEN_VOL_SFT) |
| 315 | #define NAU8825_IMM_GEN_VOL_1_16th (0x3 << NAU8825_IMM_GEN_VOL_SFT) |
| 316 | |
| 317 | #define NAU8825_IMM_CYC_SFT 4 |
| 318 | #define NAU8825_IMM_CYC_MASK (0x3 << NAU8825_IMM_CYC_SFT) |
| 319 | #define NAU8825_IMM_CYC_1024 (0x0 << NAU8825_IMM_CYC_SFT) |
| 320 | #define NAU8825_IMM_CYC_2048 (0x1 << NAU8825_IMM_CYC_SFT) |
| 321 | #define NAU8825_IMM_CYC_4096 (0x2 << NAU8825_IMM_CYC_SFT) |
| 322 | #define NAU8825_IMM_CYC_8192 (0x3 << NAU8825_IMM_CYC_SFT) |
| 323 | #define NAU8825_IMM_EN (1 << 3) |
| 324 | #define NAU8825_IMM_DAC_SRC_MASK 0x7 |
| 325 | #define NAU8825_IMM_DAC_SRC_BIQ 0x0 |
| 326 | #define NAU8825_IMM_DAC_SRC_DRC 0x1 |
| 327 | #define NAU8825_IMM_DAC_SRC_MIX 0x2 |
| 328 | #define NAU8825_IMM_DAC_SRC_SIN 0x3 |
Anatol Pomozov | 34ca27f | 2015-10-02 09:49:14 -0700 | [diff] [blame] | 329 | |
John Hsu | 45d5eb3 | 2016-03-11 17:33:58 -0800 | [diff] [blame] | 330 | /* CLASSG_CTRL (0x50) */ |
| 331 | #define NAU8825_CLASSG_TIMER_SFT 8 |
| 332 | #define NAU8825_CLASSG_TIMER_MASK (0x3f << NAU8825_CLASSG_TIMER_SFT) |
John Hsu | b50455f | 2016-06-07 10:29:27 +0800 | [diff] [blame] | 333 | #define NAU8825_CLASSG_TIMER_1ms (0x1 << NAU8825_CLASSG_TIMER_SFT) |
| 334 | #define NAU8825_CLASSG_TIMER_2ms (0x2 << NAU8825_CLASSG_TIMER_SFT) |
| 335 | #define NAU8825_CLASSG_TIMER_8ms (0x4 << NAU8825_CLASSG_TIMER_SFT) |
| 336 | #define NAU8825_CLASSG_TIMER_16ms (0x8 << NAU8825_CLASSG_TIMER_SFT) |
| 337 | #define NAU8825_CLASSG_TIMER_32ms (0x10 << NAU8825_CLASSG_TIMER_SFT) |
| 338 | #define NAU8825_CLASSG_TIMER_64ms (0x20 << NAU8825_CLASSG_TIMER_SFT) |
| 339 | #define NAU8825_CLASSG_LDAC_EN (0x1 << 2) |
| 340 | #define NAU8825_CLASSG_RDAC_EN (0x1 << 1) |
John Hsu | 45d5eb3 | 2016-03-11 17:33:58 -0800 | [diff] [blame] | 341 | #define NAU8825_CLASSG_EN (1 << 0) |
| 342 | |
Anatol Pomozov | 34ca27f | 2015-10-02 09:49:14 -0700 | [diff] [blame] | 343 | /* I2C_DEVICE_ID (0x58) */ |
| 344 | #define NAU8825_GPIO2JD1 (1 << 7) |
| 345 | #define NAU8825_SOFTWARE_ID_MASK 0x3 |
| 346 | #define NAU8825_SOFTWARE_ID_NAU8825 0x0 |
| 347 | |
| 348 | /* BIAS_ADJ (0x66) */ |
John Hsu | b50455f | 2016-06-07 10:29:27 +0800 | [diff] [blame] | 349 | #define NAU8825_BIAS_HPR_IMP (1 << 15) |
| 350 | #define NAU8825_BIAS_HPL_IMP (1 << 14) |
| 351 | #define NAU8825_BIAS_TESTDAC_SFT 8 |
| 352 | #define NAU8825_BIAS_TESTDAC_EN (0x3 << NAU8825_BIAS_TESTDAC_SFT) |
| 353 | #define NAU8825_BIAS_TESTDACR_EN (0x2 << NAU8825_BIAS_TESTDAC_SFT) |
| 354 | #define NAU8825_BIAS_TESTDACL_EN (0x1 << NAU8825_BIAS_TESTDAC_SFT) |
Anatol Pomozov | 34ca27f | 2015-10-02 09:49:14 -0700 | [diff] [blame] | 355 | #define NAU8825_BIAS_VMID (1 << 6) |
| 356 | #define NAU8825_BIAS_VMID_SEL_SFT 4 |
| 357 | #define NAU8825_BIAS_VMID_SEL_MASK (3 << NAU8825_BIAS_VMID_SEL_SFT) |
| 358 | |
| 359 | /* ANALOG_CONTROL_2 (0x6a) */ |
| 360 | #define NAU8825_HP_NON_CLASSG_CURRENT_2xADJ (1 << 12) |
| 361 | #define NAU8825_DAC_CAPACITOR_MSB (1 << 1) |
| 362 | #define NAU8825_DAC_CAPACITOR_LSB (1 << 0) |
| 363 | |
| 364 | /* ANALOG_ADC_2 (0x72) */ |
| 365 | #define NAU8825_ADC_VREFSEL_MASK (0x3 << 8) |
| 366 | #define NAU8825_ADC_VREFSEL_ANALOG (0 << 8) |
| 367 | #define NAU8825_ADC_VREFSEL_VMID (1 << 8) |
| 368 | #define NAU8825_ADC_VREFSEL_VMID_PLUS_0_5DB (2 << 8) |
| 369 | #define NAU8825_ADC_VREFSEL_VMID_PLUS_1DB (3 << 8) |
| 370 | #define NAU8825_POWERUP_ADCL (1 << 6) |
| 371 | |
John Hsu | 45d5eb3 | 2016-03-11 17:33:58 -0800 | [diff] [blame] | 372 | /* RDAC (0x73) */ |
John Hsu | b50455f | 2016-06-07 10:29:27 +0800 | [diff] [blame] | 373 | #define NAU8825_RDAC_FS_BCLK_ENB (1 << 15) |
| 374 | #define NAU8825_RDAC_EN_SFT 12 |
| 375 | #define NAU8825_RDAC_EN (0x3 << NAU8825_RDAC_EN_SFT) |
| 376 | #define NAU8825_RDAC_CLK_EN_SFT 8 |
| 377 | #define NAU8825_RDAC_CLK_EN (0x3 << NAU8825_RDAC_CLK_EN_SFT) |
John Hsu | 45d5eb3 | 2016-03-11 17:33:58 -0800 | [diff] [blame] | 378 | #define NAU8825_RDAC_CLK_DELAY_SFT 4 |
| 379 | #define NAU8825_RDAC_CLK_DELAY_MASK (0x7 << NAU8825_RDAC_CLK_DELAY_SFT) |
| 380 | #define NAU8825_RDAC_VREF_SFT 2 |
| 381 | #define NAU8825_RDAC_VREF_MASK (0x3 << NAU8825_RDAC_VREF_SFT) |
| 382 | |
Anatol Pomozov | 34ca27f | 2015-10-02 09:49:14 -0700 | [diff] [blame] | 383 | /* MIC_BIAS (0x74) */ |
| 384 | #define NAU8825_MICBIAS_JKSLV (1 << 14) |
| 385 | #define NAU8825_MICBIAS_JKR2 (1 << 12) |
| 386 | #define NAU8825_MICBIAS_POWERUP_SFT 8 |
| 387 | #define NAU8825_MICBIAS_VOLTAGE_SFT 0 |
| 388 | #define NAU8825_MICBIAS_VOLTAGE_MASK 0x7 |
| 389 | |
| 390 | /* BOOST (0x76) */ |
| 391 | #define NAU8825_PRECHARGE_DIS (1 << 13) |
| 392 | #define NAU8825_GLOBAL_BIAS_EN (1 << 12) |
John Hsu | 45d5eb3 | 2016-03-11 17:33:58 -0800 | [diff] [blame] | 393 | #define NAU8825_HP_BOOST_DIS (1 << 9) |
Anatol Pomozov | 34ca27f | 2015-10-02 09:49:14 -0700 | [diff] [blame] | 394 | #define NAU8825_HP_BOOST_G_DIS (1 << 8) |
| 395 | #define NAU8825_SHORT_SHUTDOWN_EN (1 << 6) |
| 396 | |
| 397 | /* POWER_UP_CONTROL (0x7f) */ |
| 398 | #define NAU8825_POWERUP_INTEGR_R (1 << 5) |
| 399 | #define NAU8825_POWERUP_INTEGR_L (1 << 4) |
| 400 | #define NAU8825_POWERUP_DRV_IN_R (1 << 3) |
| 401 | #define NAU8825_POWERUP_DRV_IN_L (1 << 2) |
| 402 | #define NAU8825_POWERUP_HP_DRV_R (1 << 1) |
| 403 | #define NAU8825_POWERUP_HP_DRV_L (1 << 0) |
| 404 | |
| 405 | /* CHARGE_PUMP (0x80) */ |
| 406 | #define NAU8825_JAMNODCLOW (1 << 10) |
| 407 | #define NAU8825_POWER_DOWN_DACR (1 << 9) |
| 408 | #define NAU8825_POWER_DOWN_DACL (1 << 8) |
| 409 | #define NAU8825_CHANRGE_PUMP_EN (1 << 5) |
| 410 | |
| 411 | |
| 412 | /* System Clock Source */ |
| 413 | enum { |
John Hsu | 2ec30f6 | 2016-05-23 10:25:40 +0800 | [diff] [blame] | 414 | NAU8825_CLK_DIS = 0, |
| 415 | NAU8825_CLK_MCLK, |
Anatol Pomozov | 34ca27f | 2015-10-02 09:49:14 -0700 | [diff] [blame] | 416 | NAU8825_CLK_INTERNAL, |
John Hsu | 70543c3 | 2016-03-15 12:08:21 +0800 | [diff] [blame] | 417 | NAU8825_CLK_FLL_MCLK, |
| 418 | NAU8825_CLK_FLL_BLK, |
| 419 | NAU8825_CLK_FLL_FS, |
Anatol Pomozov | 34ca27f | 2015-10-02 09:49:14 -0700 | [diff] [blame] | 420 | }; |
| 421 | |
John Hsu | b50455f | 2016-06-07 10:29:27 +0800 | [diff] [blame] | 422 | /* Cross talk detection state */ |
| 423 | enum { |
| 424 | NAU8825_XTALK_PREPARE = 0, |
| 425 | NAU8825_XTALK_HPR_R2L, |
| 426 | NAU8825_XTALK_HPL_R2L, |
| 427 | NAU8825_XTALK_IMM, |
| 428 | NAU8825_XTALK_DONE, |
| 429 | }; |
| 430 | |
Anatol Pomozov | 34ca27f | 2015-10-02 09:49:14 -0700 | [diff] [blame] | 431 | struct nau8825 { |
| 432 | struct device *dev; |
| 433 | struct regmap *regmap; |
| 434 | struct snd_soc_dapm_context *dapm; |
| 435 | struct snd_soc_jack *jack; |
| 436 | struct clk *mclk; |
John Hsu | b50455f | 2016-06-07 10:29:27 +0800 | [diff] [blame] | 437 | struct work_struct xtalk_work; |
| 438 | struct semaphore xtalk_sem; |
Anatol Pomozov | 34ca27f | 2015-10-02 09:49:14 -0700 | [diff] [blame] | 439 | int irq; |
| 440 | int mclk_freq; /* 0 - mclk is disabled */ |
| 441 | int button_pressed; |
| 442 | int micbias_voltage; |
| 443 | int vref_impedance; |
| 444 | bool jkdet_enable; |
| 445 | bool jkdet_pull_enable; |
| 446 | bool jkdet_pull_up; |
| 447 | int jkdet_polarity; |
| 448 | int sar_threshold_num; |
| 449 | int sar_threshold[8]; |
| 450 | int sar_hysteresis; |
| 451 | int sar_voltage; |
| 452 | int sar_compare_time; |
| 453 | int sar_sampling_time; |
| 454 | int key_debounce; |
| 455 | int jack_insert_debounce; |
| 456 | int jack_eject_debounce; |
John Hsu | b50455f | 2016-06-07 10:29:27 +0800 | [diff] [blame] | 457 | int high_imped; |
| 458 | int xtalk_state; |
| 459 | int xtalk_event; |
| 460 | int xtalk_event_mask; |
| 461 | bool xtalk_protect; |
| 462 | int imp_rms[NAU8825_XTALK_IMM]; |
Anatol Pomozov | 34ca27f | 2015-10-02 09:49:14 -0700 | [diff] [blame] | 463 | }; |
| 464 | |
| 465 | int nau8825_enable_jack_detect(struct snd_soc_codec *codec, |
| 466 | struct snd_soc_jack *jack); |
| 467 | |
| 468 | |
| 469 | #endif /* __NAU8825_H__ */ |