blob: fd918565f4e56d0deccf694438da08a1e5252b95 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Dave Airliebc54fd12005-06-23 22:46:46 +10004 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10007 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110028 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
33/* General customization:
34 */
35
36#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
37
38#define DRIVER_NAME "i915"
39#define DRIVER_DESC "Intel Graphics"
Dave Airliede227f52006-01-25 15:31:43 +110040#define DRIVER_DATE "20060119"
Linus Torvalds1da177e2005-04-16 15:20:36 -070041
42/* Interface history:
43 *
44 * 1.1: Original.
Dave Airlie0d6aa602006-01-02 20:14:23 +110045 * 1.2: Add Power Management
46 * 1.3: Add vblank support
Dave Airliede227f52006-01-25 15:31:43 +110047 * 1.4: Fix cmdbuffer path, add heap destroy
Dave Airlie702880f2006-06-24 17:07:34 +100048 * 1.5: Add vblank pipe configuration
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +100049 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
50 * - Support vertical blank on secondary display pipe
Linus Torvalds1da177e2005-04-16 15:20:36 -070051 */
52#define DRIVER_MAJOR 1
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +100053#define DRIVER_MINOR 6
Linus Torvalds1da177e2005-04-16 15:20:36 -070054#define DRIVER_PATCHLEVEL 0
55
Linus Torvalds1da177e2005-04-16 15:20:36 -070056typedef struct _drm_i915_ring_buffer {
57 int tail_mask;
58 unsigned long Start;
59 unsigned long End;
60 unsigned long Size;
61 u8 *virtual_start;
62 int head;
63 int tail;
64 int space;
65 drm_local_map_t map;
66} drm_i915_ring_buffer_t;
67
68struct mem_block {
69 struct mem_block *next;
70 struct mem_block *prev;
71 int start;
72 int size;
73 DRMFILE filp; /* 0: free, -1: heap, other: real files */
74};
75
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +100076typedef struct _drm_i915_vbl_swap {
77 struct list_head head;
78 drm_drawable_t drw_id;
79 unsigned int pipe;
80 unsigned int sequence;
81} drm_i915_vbl_swap_t;
82
Linus Torvalds1da177e2005-04-16 15:20:36 -070083typedef struct drm_i915_private {
84 drm_local_map_t *sarea;
85 drm_local_map_t *mmio_map;
86
87 drm_i915_sarea_t *sarea_priv;
88 drm_i915_ring_buffer_t ring;
89
Dave Airlie9c8da5e2005-07-10 15:38:56 +100090 drm_dma_handle_t *status_page_dmah;
Linus Torvalds1da177e2005-04-16 15:20:36 -070091 void *hw_status_page;
Linus Torvalds1da177e2005-04-16 15:20:36 -070092 dma_addr_t dma_status_page;
Dave Airlie9c8da5e2005-07-10 15:38:56 +100093 unsigned long counter;
Wang Zhenyudc7a9312007-06-10 15:58:19 +100094 unsigned int status_gfx_addr;
95 drm_local_map_t hws_map;
Linus Torvalds1da177e2005-04-16 15:20:36 -070096
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +100097 unsigned int cpp;
Linus Torvalds1da177e2005-04-16 15:20:36 -070098 int back_offset;
99 int front_offset;
100 int current_page;
101 int page_flipping;
102 int use_mi_batchbuffer_start;
103
104 wait_queue_head_t irq_queue;
105 atomic_t irq_received;
106 atomic_t irq_emitted;
107
108 int tex_lru_log_granularity;
109 int allow_batchbuffer;
110 struct mem_block *agp_heap;
Dave Airlie0d6aa602006-01-02 20:14:23 +1100111 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
Dave Airlie702880f2006-06-24 17:07:34 +1000112 int vblank_pipe;
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000113
114 spinlock_t swaps_lock;
115 drm_i915_vbl_swap_t vbl_swaps;
116 unsigned int swaps_pending;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700117} drm_i915_private_t;
118
Dave Airlieb3a83632005-09-30 18:37:36 +1000119extern drm_ioctl_desc_t i915_ioctls[];
120extern int i915_max_ioctl;
121
Linus Torvalds1da177e2005-04-16 15:20:36 -0700122 /* i915_dma.c */
Dave Airlie84b1fd12007-07-11 15:53:27 +1000123extern void i915_kernel_lost_context(struct drm_device * dev);
Dave Airlie22eae942005-11-10 22:16:34 +1100124extern int i915_driver_load(struct drm_device *, unsigned long flags);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000125extern void i915_driver_lastclose(struct drm_device * dev);
126extern void i915_driver_preclose(struct drm_device * dev, DRMFILE filp);
127extern int i915_driver_device_is_agp(struct drm_device * dev);
Dave Airlie0d6aa602006-01-02 20:14:23 +1100128extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
129 unsigned long arg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700130
131/* i915_irq.c */
132extern int i915_irq_emit(DRM_IOCTL_ARGS);
133extern int i915_irq_wait(DRM_IOCTL_ARGS);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700134
Dave Airlie84b1fd12007-07-11 15:53:27 +1000135extern int i915_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence);
136extern int i915_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700137extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000138extern void i915_driver_irq_preinstall(struct drm_device * dev);
139extern void i915_driver_irq_postinstall(struct drm_device * dev);
140extern void i915_driver_irq_uninstall(struct drm_device * dev);
Dave Airlie702880f2006-06-24 17:07:34 +1000141extern int i915_vblank_pipe_set(DRM_IOCTL_ARGS);
142extern int i915_vblank_pipe_get(DRM_IOCTL_ARGS);
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000143extern int i915_vblank_swap(DRM_IOCTL_ARGS);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700144
145/* i915_mem.c */
146extern int i915_mem_alloc(DRM_IOCTL_ARGS);
147extern int i915_mem_free(DRM_IOCTL_ARGS);
148extern int i915_mem_init_heap(DRM_IOCTL_ARGS);
Dave Airliede227f52006-01-25 15:31:43 +1100149extern int i915_mem_destroy_heap(DRM_IOCTL_ARGS);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700150extern void i915_mem_takedown(struct mem_block **heap);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000151extern void i915_mem_release(struct drm_device * dev,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700152 DRMFILE filp, struct mem_block *heap);
153
Dave Airlie0d6aa602006-01-02 20:14:23 +1100154#define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg))
155#define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
156#define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg))
157#define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700158
159#define I915_VERBOSE 0
160
161#define RING_LOCALS unsigned int outring, ringmask, outcount; \
162 volatile char *virt;
163
164#define BEGIN_LP_RING(n) do { \
165 if (I915_VERBOSE) \
166 DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n", \
Alan Hourihanec29b6692006-08-12 16:29:24 +1000167 (n), __FUNCTION__); \
168 if (dev_priv->ring.space < (n)*4) \
169 i915_wait_ring(dev, (n)*4, __FUNCTION__); \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700170 outcount = 0; \
171 outring = dev_priv->ring.tail; \
172 ringmask = dev_priv->ring.tail_mask; \
173 virt = dev_priv->ring.virtual_start; \
174} while (0)
175
176#define OUT_RING(n) do { \
177 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
Alan Hourihanec29b6692006-08-12 16:29:24 +1000178 *(volatile unsigned int *)(virt + outring) = (n); \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700179 outcount++; \
180 outring += 4; \
181 outring &= ringmask; \
182} while (0)
183
184#define ADVANCE_LP_RING() do { \
185 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
186 dev_priv->ring.tail = outring; \
187 dev_priv->ring.space -= outcount * 4; \
188 I915_WRITE(LP_RING + RING_TAIL, outring); \
189} while(0)
190
Dave Airlie84b1fd12007-07-11 15:53:27 +1000191extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700192
193#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
194#define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))
195#define CMD_REPORT_HEAD (7<<23)
196#define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1)
197#define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1)
198
199#define INST_PARSER_CLIENT 0x00000000
200#define INST_OP_FLUSH 0x02000000
201#define INST_FLUSH_MAP_CACHE 0x00000001
202
203#define BB1_START_ADDR_MASK (~0x7)
204#define BB1_PROTECTED (1<<0)
205#define BB1_UNPROTECTED (0<<0)
206#define BB2_END_ADDR_MASK (~0x7)
207
208#define I915REG_HWSTAM 0x02098
209#define I915REG_INT_IDENTITY_R 0x020a4
210#define I915REG_INT_MASK_R 0x020a8
211#define I915REG_INT_ENABLE_R 0x020a0
212
213#define SRX_INDEX 0x3c4
214#define SRX_DATA 0x3c5
215#define SR01 1
216#define SR01_SCREEN_OFF (1<<5)
217
218#define PPCR 0x61204
219#define PPCR_ON (1<<0)
220
Dave Airlie0d6aa602006-01-02 20:14:23 +1100221#define DVOB 0x61140
222#define DVOB_ON (1<<31)
223#define DVOC 0x61160
224#define DVOC_ON (1<<31)
225#define LVDS 0x61180
226#define LVDS_ON (1<<31)
227
Linus Torvalds1da177e2005-04-16 15:20:36 -0700228#define ADPA 0x61100
229#define ADPA_DPMS_MASK (~(3<<10))
230#define ADPA_DPMS_ON (0<<10)
231#define ADPA_DPMS_SUSPEND (1<<10)
232#define ADPA_DPMS_STANDBY (2<<10)
233#define ADPA_DPMS_OFF (3<<10)
234
235#define NOPID 0x2094
236#define LP_RING 0x2030
237#define HP_RING 0x2040
238#define RING_TAIL 0x00
239#define TAIL_ADDR 0x001FFFF8
240#define RING_HEAD 0x04
241#define HEAD_WRAP_COUNT 0xFFE00000
242#define HEAD_WRAP_ONE 0x00200000
243#define HEAD_ADDR 0x001FFFFC
244#define RING_START 0x08
245#define START_ADDR 0x0xFFFFF000
246#define RING_LEN 0x0C
247#define RING_NR_PAGES 0x001FF000
248#define RING_REPORT_MASK 0x00000006
249#define RING_REPORT_64K 0x00000002
250#define RING_REPORT_128K 0x00000004
251#define RING_NO_REPORT 0x00000000
252#define RING_VALID_MASK 0x00000001
253#define RING_VALID 0x00000001
254#define RING_INVALID 0x00000000
255
256#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
257#define SC_UPDATE_SCISSOR (0x1<<1)
258#define SC_ENABLE_MASK (0x1<<0)
259#define SC_ENABLE (0x1<<0)
260
261#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
262#define SCI_YMIN_MASK (0xffff<<16)
263#define SCI_XMIN_MASK (0xffff<<0)
264#define SCI_YMAX_MASK (0xffff<<16)
265#define SCI_XMAX_MASK (0xffff<<0)
266
267#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
268#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
269#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
270#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
271#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
272#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
273#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
274
Alan Hourihanec29b6692006-08-12 16:29:24 +1000275#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
276
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000277#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
278#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
279#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
280
Linus Torvalds1da177e2005-04-16 15:20:36 -0700281#define MI_BATCH_BUFFER ((0x30<<23)|1)
282#define MI_BATCH_BUFFER_START (0x31<<23)
283#define MI_BATCH_BUFFER_END (0xA<<23)
284#define MI_BATCH_NON_SECURE (1)
285
286#define MI_WAIT_FOR_EVENT ((0x3<<23))
287#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
288#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
289
290#define MI_LOAD_SCAN_LINES_INCL ((0x12<<23))
291
292#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
293#define ASYNC_FLIP (1<<22)
294
295#define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
296
Dave Airlie0d6aa602006-01-02 20:14:23 +1100297#define READ_BREADCRUMB(dev_priv) (((u32 *)(dev_priv->hw_status_page))[5])
298
Linus Torvalds1da177e2005-04-16 15:20:36 -0700299#endif