Hemant Kumar | 4f836c2 | 2020-01-14 17:35:10 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. |
Nitesh Gupta | 35b8ea6 | 2019-10-31 10:45:54 +0530 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/debugfs.h> |
| 14 | #include <linux/device.h> |
| 15 | #include <linux/dma-direction.h> |
| 16 | #include <linux/dma-mapping.h> |
| 17 | #include <linux/interrupt.h> |
| 18 | #include <linux/list.h> |
| 19 | #include <linux/of.h> |
| 20 | #include <linux/module.h> |
| 21 | #include <linux/skbuff.h> |
| 22 | #include <linux/slab.h> |
| 23 | #include <linux/mhi.h> |
Nitesh Gupta | f2b595d | 2019-10-31 11:22:01 +0530 | [diff] [blame] | 24 | #include <linux/types.h> |
Nitesh Gupta | 35b8ea6 | 2019-10-31 10:45:54 +0530 | [diff] [blame] | 25 | #include "mhi_internal.h" |
| 26 | |
| 27 | static void __mhi_unprepare_channel(struct mhi_controller *mhi_cntrl, |
| 28 | struct mhi_chan *mhi_chan); |
| 29 | |
| 30 | int __must_check mhi_read_reg(struct mhi_controller *mhi_cntrl, |
| 31 | void __iomem *base, |
| 32 | u32 offset, |
| 33 | u32 *out) |
| 34 | { |
| 35 | u32 tmp = readl_relaxed(base + offset); |
| 36 | |
| 37 | /* unexpected value, query the link status */ |
| 38 | if (PCI_INVALID_READ(tmp) && |
| 39 | mhi_cntrl->link_status(mhi_cntrl, mhi_cntrl->priv_data)) |
| 40 | return -EIO; |
| 41 | |
| 42 | *out = tmp; |
| 43 | |
| 44 | return 0; |
| 45 | } |
| 46 | |
| 47 | int __must_check mhi_read_reg_field(struct mhi_controller *mhi_cntrl, |
| 48 | void __iomem *base, |
| 49 | u32 offset, |
| 50 | u32 mask, |
| 51 | u32 shift, |
| 52 | u32 *out) |
| 53 | { |
| 54 | u32 tmp; |
| 55 | int ret; |
| 56 | |
| 57 | ret = mhi_read_reg(mhi_cntrl, base, offset, &tmp); |
| 58 | if (ret) |
| 59 | return ret; |
| 60 | |
| 61 | *out = (tmp & mask) >> shift; |
| 62 | |
| 63 | return 0; |
| 64 | } |
| 65 | |
| 66 | int mhi_get_capability_offset(struct mhi_controller *mhi_cntrl, |
| 67 | u32 capability, |
| 68 | u32 *offset) |
| 69 | { |
| 70 | u32 cur_cap, next_offset; |
| 71 | int ret; |
| 72 | |
| 73 | /* get the 1st supported capability offset */ |
| 74 | ret = mhi_read_reg_field(mhi_cntrl, mhi_cntrl->regs, MISC_OFFSET, |
| 75 | MISC_CAP_MASK, MISC_CAP_SHIFT, offset); |
| 76 | if (ret) |
| 77 | return ret; |
| 78 | do { |
| 79 | ret = mhi_read_reg_field(mhi_cntrl, mhi_cntrl->regs, *offset, |
| 80 | CAP_CAPID_MASK, CAP_CAPID_SHIFT, |
| 81 | &cur_cap); |
| 82 | if (ret) |
| 83 | return ret; |
| 84 | |
| 85 | if (cur_cap == capability) |
| 86 | return 0; |
| 87 | |
| 88 | ret = mhi_read_reg_field(mhi_cntrl, mhi_cntrl->regs, *offset, |
| 89 | CAP_NEXT_CAP_MASK, CAP_NEXT_CAP_SHIFT, |
| 90 | &next_offset); |
| 91 | if (ret) |
| 92 | return ret; |
| 93 | |
| 94 | *offset = next_offset; |
| 95 | if (*offset >= MHI_REG_SIZE) |
| 96 | return -ENXIO; |
| 97 | } while (next_offset); |
| 98 | |
| 99 | return -ENXIO; |
| 100 | } |
| 101 | |
| 102 | void mhi_write_reg(struct mhi_controller *mhi_cntrl, |
| 103 | void __iomem *base, |
| 104 | u32 offset, |
| 105 | u32 val) |
| 106 | { |
| 107 | writel_relaxed(val, base + offset); |
| 108 | } |
| 109 | |
| 110 | void mhi_write_reg_field(struct mhi_controller *mhi_cntrl, |
| 111 | void __iomem *base, |
| 112 | u32 offset, |
| 113 | u32 mask, |
| 114 | u32 shift, |
| 115 | u32 val) |
| 116 | { |
| 117 | int ret; |
| 118 | u32 tmp; |
| 119 | |
| 120 | ret = mhi_read_reg(mhi_cntrl, base, offset, &tmp); |
| 121 | if (ret) |
| 122 | return; |
| 123 | |
| 124 | tmp &= ~mask; |
| 125 | tmp |= (val << shift); |
| 126 | mhi_write_reg(mhi_cntrl, base, offset, tmp); |
| 127 | } |
| 128 | |
| 129 | void mhi_write_db(struct mhi_controller *mhi_cntrl, |
| 130 | void __iomem *db_addr, |
| 131 | dma_addr_t wp) |
| 132 | { |
| 133 | mhi_write_reg(mhi_cntrl, db_addr, 4, upper_32_bits(wp)); |
| 134 | mhi_write_reg(mhi_cntrl, db_addr, 0, lower_32_bits(wp)); |
| 135 | } |
| 136 | |
| 137 | void mhi_db_brstmode(struct mhi_controller *mhi_cntrl, |
| 138 | struct db_cfg *db_cfg, |
| 139 | void __iomem *db_addr, |
| 140 | dma_addr_t wp) |
| 141 | { |
| 142 | if (db_cfg->db_mode) { |
| 143 | db_cfg->db_val = wp; |
| 144 | mhi_write_db(mhi_cntrl, db_addr, wp); |
| 145 | db_cfg->db_mode = 0; |
| 146 | } |
| 147 | } |
| 148 | |
| 149 | void mhi_db_brstmode_disable(struct mhi_controller *mhi_cntrl, |
| 150 | struct db_cfg *db_cfg, |
| 151 | void __iomem *db_addr, |
| 152 | dma_addr_t wp) |
| 153 | { |
| 154 | db_cfg->db_val = wp; |
| 155 | mhi_write_db(mhi_cntrl, db_addr, wp); |
| 156 | } |
| 157 | |
| 158 | void mhi_ring_er_db(struct mhi_event *mhi_event) |
| 159 | { |
| 160 | struct mhi_ring *ring = &mhi_event->ring; |
| 161 | |
| 162 | mhi_event->db_cfg.process_db(mhi_event->mhi_cntrl, &mhi_event->db_cfg, |
| 163 | ring->db_addr, *ring->ctxt_wp); |
| 164 | } |
| 165 | |
| 166 | void mhi_ring_cmd_db(struct mhi_controller *mhi_cntrl, struct mhi_cmd *mhi_cmd) |
| 167 | { |
| 168 | dma_addr_t db; |
| 169 | struct mhi_ring *ring = &mhi_cmd->ring; |
| 170 | |
| 171 | db = ring->iommu_base + (ring->wp - ring->base); |
| 172 | *ring->ctxt_wp = db; |
| 173 | mhi_write_db(mhi_cntrl, ring->db_addr, db); |
| 174 | } |
| 175 | |
| 176 | void mhi_ring_chan_db(struct mhi_controller *mhi_cntrl, |
| 177 | struct mhi_chan *mhi_chan) |
| 178 | { |
| 179 | struct mhi_ring *ring = &mhi_chan->tre_ring; |
| 180 | dma_addr_t db; |
| 181 | |
| 182 | db = ring->iommu_base + (ring->wp - ring->base); |
| 183 | *ring->ctxt_wp = db; |
| 184 | mhi_chan->db_cfg.process_db(mhi_cntrl, &mhi_chan->db_cfg, ring->db_addr, |
| 185 | db); |
| 186 | } |
| 187 | |
| 188 | static enum mhi_ee mhi_translate_dev_ee(struct mhi_controller *mhi_cntrl, |
| 189 | u32 dev_ee) |
| 190 | { |
| 191 | enum mhi_ee i; |
| 192 | |
| 193 | for (i = MHI_EE_PBL; i < MHI_EE_MAX; i++) |
| 194 | if (mhi_cntrl->ee_table[i] == dev_ee) |
| 195 | return i; |
| 196 | |
| 197 | return MHI_EE_NOT_SUPPORTED; |
| 198 | } |
| 199 | |
| 200 | enum mhi_ee mhi_get_exec_env(struct mhi_controller *mhi_cntrl) |
| 201 | { |
| 202 | u32 exec; |
| 203 | int ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_EXECENV, &exec); |
| 204 | |
| 205 | return (ret) ? MHI_EE_MAX : mhi_translate_dev_ee(mhi_cntrl, exec); |
| 206 | } |
| 207 | |
| 208 | enum mhi_dev_state mhi_get_mhi_state(struct mhi_controller *mhi_cntrl) |
| 209 | { |
| 210 | u32 state; |
| 211 | int ret = mhi_read_reg_field(mhi_cntrl, mhi_cntrl->regs, MHISTATUS, |
| 212 | MHISTATUS_MHISTATE_MASK, |
| 213 | MHISTATUS_MHISTATE_SHIFT, &state); |
| 214 | return ret ? MHI_STATE_MAX : state; |
| 215 | } |
| 216 | |
| 217 | int mhi_queue_sclist(struct mhi_device *mhi_dev, |
| 218 | struct mhi_chan *mhi_chan, |
| 219 | void *buf, |
| 220 | size_t len, |
| 221 | enum MHI_FLAGS mflags) |
| 222 | { |
| 223 | return -EINVAL; |
| 224 | } |
| 225 | |
| 226 | int mhi_queue_nop(struct mhi_device *mhi_dev, |
| 227 | struct mhi_chan *mhi_chan, |
| 228 | void *buf, |
| 229 | size_t len, |
| 230 | enum MHI_FLAGS mflags) |
| 231 | { |
| 232 | return -EINVAL; |
| 233 | } |
| 234 | |
| 235 | static void mhi_add_ring_element(struct mhi_controller *mhi_cntrl, |
| 236 | struct mhi_ring *ring) |
| 237 | { |
| 238 | ring->wp += ring->el_size; |
| 239 | if (ring->wp >= (ring->base + ring->len)) |
| 240 | ring->wp = ring->base; |
| 241 | /* smp update */ |
| 242 | smp_wmb(); |
| 243 | } |
| 244 | |
| 245 | static void mhi_del_ring_element(struct mhi_controller *mhi_cntrl, |
| 246 | struct mhi_ring *ring) |
| 247 | { |
| 248 | ring->rp += ring->el_size; |
| 249 | if (ring->rp >= (ring->base + ring->len)) |
| 250 | ring->rp = ring->base; |
| 251 | /* smp update */ |
| 252 | smp_wmb(); |
| 253 | } |
| 254 | |
| 255 | static int get_nr_avail_ring_elements(struct mhi_controller *mhi_cntrl, |
| 256 | struct mhi_ring *ring) |
| 257 | { |
| 258 | int nr_el; |
| 259 | |
| 260 | if (ring->wp < ring->rp) |
| 261 | nr_el = ((ring->rp - ring->wp) / ring->el_size) - 1; |
| 262 | else { |
| 263 | nr_el = (ring->rp - ring->base) / ring->el_size; |
| 264 | nr_el += ((ring->base + ring->len - ring->wp) / |
| 265 | ring->el_size) - 1; |
| 266 | } |
| 267 | return nr_el; |
| 268 | } |
| 269 | |
| 270 | void *mhi_to_virtual(struct mhi_ring *ring, dma_addr_t addr) |
| 271 | { |
| 272 | return (addr - ring->iommu_base) + ring->base; |
| 273 | } |
| 274 | |
| 275 | dma_addr_t mhi_to_physical(struct mhi_ring *ring, void *addr) |
| 276 | { |
| 277 | return (addr - ring->base) + ring->iommu_base; |
| 278 | } |
| 279 | |
| 280 | static void mhi_recycle_ev_ring_element(struct mhi_controller *mhi_cntrl, |
| 281 | struct mhi_ring *ring) |
| 282 | { |
| 283 | dma_addr_t ctxt_wp; |
| 284 | |
| 285 | /* update the WP */ |
| 286 | ring->wp += ring->el_size; |
| 287 | ctxt_wp = *ring->ctxt_wp + ring->el_size; |
| 288 | |
| 289 | if (ring->wp >= (ring->base + ring->len)) { |
| 290 | ring->wp = ring->base; |
| 291 | ctxt_wp = ring->iommu_base; |
| 292 | } |
| 293 | |
| 294 | *ring->ctxt_wp = ctxt_wp; |
| 295 | |
| 296 | /* update the RP */ |
| 297 | ring->rp += ring->el_size; |
| 298 | if (ring->rp >= (ring->base + ring->len)) |
| 299 | ring->rp = ring->base; |
| 300 | |
| 301 | /* visible to other cores */ |
| 302 | smp_wmb(); |
| 303 | } |
| 304 | |
| 305 | static bool mhi_is_ring_full(struct mhi_controller *mhi_cntrl, |
| 306 | struct mhi_ring *ring) |
| 307 | { |
| 308 | void *tmp = ring->wp + ring->el_size; |
| 309 | |
| 310 | if (tmp >= (ring->base + ring->len)) |
| 311 | tmp = ring->base; |
| 312 | |
| 313 | return (tmp == ring->rp); |
| 314 | } |
| 315 | |
| 316 | int mhi_map_single_no_bb(struct mhi_controller *mhi_cntrl, |
| 317 | struct mhi_buf_info *buf_info) |
| 318 | { |
| 319 | buf_info->p_addr = dma_map_single(mhi_cntrl->dev, buf_info->v_addr, |
| 320 | buf_info->len, buf_info->dir); |
| 321 | if (dma_mapping_error(mhi_cntrl->dev, buf_info->p_addr)) |
| 322 | return -ENOMEM; |
| 323 | |
| 324 | return 0; |
| 325 | } |
| 326 | |
| 327 | int mhi_map_single_use_bb(struct mhi_controller *mhi_cntrl, |
| 328 | struct mhi_buf_info *buf_info) |
| 329 | { |
| 330 | void *buf = mhi_alloc_coherent(mhi_cntrl, buf_info->len, |
| 331 | &buf_info->p_addr, GFP_ATOMIC); |
| 332 | |
| 333 | if (!buf) |
| 334 | return -ENOMEM; |
| 335 | |
| 336 | if (buf_info->dir == DMA_TO_DEVICE) |
| 337 | memcpy(buf, buf_info->v_addr, buf_info->len); |
| 338 | |
| 339 | buf_info->bb_addr = buf; |
| 340 | |
| 341 | return 0; |
| 342 | } |
| 343 | |
| 344 | void mhi_unmap_single_no_bb(struct mhi_controller *mhi_cntrl, |
| 345 | struct mhi_buf_info *buf_info) |
| 346 | { |
| 347 | dma_unmap_single(mhi_cntrl->dev, buf_info->p_addr, buf_info->len, |
| 348 | buf_info->dir); |
| 349 | } |
| 350 | |
| 351 | void mhi_unmap_single_use_bb(struct mhi_controller *mhi_cntrl, |
| 352 | struct mhi_buf_info *buf_info) |
| 353 | { |
| 354 | if (buf_info->dir == DMA_FROM_DEVICE) |
| 355 | memcpy(buf_info->v_addr, buf_info->bb_addr, buf_info->len); |
| 356 | |
| 357 | mhi_free_coherent(mhi_cntrl, buf_info->len, buf_info->bb_addr, |
| 358 | buf_info->p_addr); |
| 359 | } |
| 360 | |
| 361 | int mhi_queue_skb(struct mhi_device *mhi_dev, |
| 362 | struct mhi_chan *mhi_chan, |
| 363 | void *buf, |
| 364 | size_t len, |
| 365 | enum MHI_FLAGS mflags) |
| 366 | { |
| 367 | struct sk_buff *skb = buf; |
| 368 | struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; |
| 369 | struct mhi_ring *tre_ring = &mhi_chan->tre_ring; |
| 370 | struct mhi_ring *buf_ring = &mhi_chan->buf_ring; |
| 371 | struct mhi_buf_info *buf_info; |
| 372 | struct mhi_tre *mhi_tre; |
| 373 | int ret; |
| 374 | |
| 375 | if (mhi_is_ring_full(mhi_cntrl, tre_ring)) |
| 376 | return -ENOMEM; |
| 377 | |
| 378 | read_lock_bh(&mhi_cntrl->pm_lock); |
| 379 | if (unlikely(MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state))) { |
| 380 | MHI_VERB("MHI is not in activate state, pm_state:%s\n", |
| 381 | to_mhi_pm_state_str(mhi_cntrl->pm_state)); |
| 382 | read_unlock_bh(&mhi_cntrl->pm_lock); |
| 383 | |
| 384 | return -EIO; |
| 385 | } |
| 386 | |
| 387 | /* we're in M3 or transitioning to M3 */ |
| 388 | if (MHI_PM_IN_SUSPEND_STATE(mhi_cntrl->pm_state)) { |
| 389 | mhi_cntrl->runtime_get(mhi_cntrl, mhi_cntrl->priv_data); |
| 390 | mhi_cntrl->runtime_put(mhi_cntrl, mhi_cntrl->priv_data); |
| 391 | } |
| 392 | |
| 393 | /* toggle wake to exit out of M2 */ |
| 394 | mhi_cntrl->wake_toggle(mhi_cntrl); |
| 395 | |
| 396 | /* generate the tre */ |
| 397 | buf_info = buf_ring->wp; |
| 398 | buf_info->v_addr = skb->data; |
| 399 | buf_info->cb_buf = skb; |
| 400 | buf_info->wp = tre_ring->wp; |
| 401 | buf_info->dir = mhi_chan->dir; |
| 402 | buf_info->len = len; |
| 403 | ret = mhi_cntrl->map_single(mhi_cntrl, buf_info); |
| 404 | if (ret) |
| 405 | goto map_error; |
| 406 | |
| 407 | mhi_tre = tre_ring->wp; |
| 408 | |
| 409 | mhi_tre->ptr = MHI_TRE_DATA_PTR(buf_info->p_addr); |
| 410 | mhi_tre->dword[0] = MHI_TRE_DATA_DWORD0(buf_info->len); |
| 411 | mhi_tre->dword[1] = MHI_TRE_DATA_DWORD1(1, 1, 0, 0); |
| 412 | |
| 413 | MHI_VERB("chan:%d WP:0x%llx TRE:0x%llx 0x%08x 0x%08x\n", mhi_chan->chan, |
| 414 | (u64)mhi_to_physical(tre_ring, mhi_tre), mhi_tre->ptr, |
| 415 | mhi_tre->dword[0], mhi_tre->dword[1]); |
| 416 | |
| 417 | /* increment WP */ |
| 418 | mhi_add_ring_element(mhi_cntrl, tre_ring); |
| 419 | mhi_add_ring_element(mhi_cntrl, buf_ring); |
| 420 | |
| 421 | if (mhi_chan->dir == DMA_TO_DEVICE) |
| 422 | atomic_inc(&mhi_cntrl->pending_pkts); |
| 423 | |
| 424 | if (likely(MHI_DB_ACCESS_VALID(mhi_cntrl))) { |
| 425 | read_lock_bh(&mhi_chan->lock); |
| 426 | mhi_ring_chan_db(mhi_cntrl, mhi_chan); |
| 427 | read_unlock_bh(&mhi_chan->lock); |
| 428 | } |
| 429 | |
| 430 | read_unlock_bh(&mhi_cntrl->pm_lock); |
| 431 | |
| 432 | return 0; |
| 433 | |
| 434 | map_error: |
| 435 | read_unlock_bh(&mhi_cntrl->pm_lock); |
| 436 | |
| 437 | return ret; |
| 438 | } |
| 439 | |
| 440 | int mhi_queue_dma(struct mhi_device *mhi_dev, |
| 441 | struct mhi_chan *mhi_chan, |
| 442 | void *buf, |
| 443 | size_t len, |
| 444 | enum MHI_FLAGS mflags) |
| 445 | { |
| 446 | struct mhi_buf *mhi_buf = buf; |
| 447 | struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; |
| 448 | struct mhi_ring *tre_ring = &mhi_chan->tre_ring; |
| 449 | struct mhi_ring *buf_ring = &mhi_chan->buf_ring; |
| 450 | struct mhi_buf_info *buf_info; |
| 451 | struct mhi_tre *mhi_tre; |
| 452 | |
| 453 | if (mhi_is_ring_full(mhi_cntrl, tre_ring)) |
| 454 | return -ENOMEM; |
| 455 | |
| 456 | read_lock_bh(&mhi_cntrl->pm_lock); |
| 457 | if (unlikely(MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state))) { |
| 458 | MHI_VERB("MHI is not in activate state, pm_state:%s\n", |
| 459 | to_mhi_pm_state_str(mhi_cntrl->pm_state)); |
| 460 | read_unlock_bh(&mhi_cntrl->pm_lock); |
| 461 | |
| 462 | return -EIO; |
| 463 | } |
| 464 | |
| 465 | /* we're in M3 or transitioning to M3 */ |
| 466 | if (MHI_PM_IN_SUSPEND_STATE(mhi_cntrl->pm_state)) { |
| 467 | mhi_cntrl->runtime_get(mhi_cntrl, mhi_cntrl->priv_data); |
| 468 | mhi_cntrl->runtime_put(mhi_cntrl, mhi_cntrl->priv_data); |
| 469 | } |
| 470 | |
| 471 | /* toggle wake to exit out of M2 */ |
| 472 | mhi_cntrl->wake_toggle(mhi_cntrl); |
| 473 | |
| 474 | /* generate the tre */ |
| 475 | buf_info = buf_ring->wp; |
| 476 | MHI_ASSERT(buf_info->used, "TRE Not Freed\n"); |
| 477 | buf_info->p_addr = mhi_buf->dma_addr; |
| 478 | buf_info->pre_mapped = true; |
| 479 | buf_info->cb_buf = mhi_buf; |
| 480 | buf_info->wp = tre_ring->wp; |
| 481 | buf_info->dir = mhi_chan->dir; |
| 482 | buf_info->len = len; |
| 483 | |
| 484 | mhi_tre = tre_ring->wp; |
| 485 | |
| 486 | if (mhi_chan->xfer_type == MHI_XFER_RSC_DMA) { |
| 487 | buf_info->used = true; |
| 488 | mhi_tre->ptr = |
| 489 | MHI_RSCTRE_DATA_PTR(buf_info->p_addr, buf_info->len); |
| 490 | mhi_tre->dword[0] = |
| 491 | MHI_RSCTRE_DATA_DWORD0(buf_ring->wp - buf_ring->base); |
| 492 | mhi_tre->dword[1] = MHI_RSCTRE_DATA_DWORD1; |
| 493 | } else { |
| 494 | mhi_tre->ptr = MHI_TRE_DATA_PTR(buf_info->p_addr); |
| 495 | mhi_tre->dword[0] = MHI_TRE_DATA_DWORD0(buf_info->len); |
| 496 | mhi_tre->dword[1] = MHI_TRE_DATA_DWORD1(1, 1, 0, 0); |
| 497 | } |
| 498 | |
| 499 | MHI_VERB("chan:%d WP:0x%llx TRE:0x%llx 0x%08x 0x%08x\n", mhi_chan->chan, |
| 500 | (u64)mhi_to_physical(tre_ring, mhi_tre), mhi_tre->ptr, |
| 501 | mhi_tre->dword[0], mhi_tre->dword[1]); |
| 502 | |
| 503 | /* increment WP */ |
| 504 | mhi_add_ring_element(mhi_cntrl, tre_ring); |
| 505 | mhi_add_ring_element(mhi_cntrl, buf_ring); |
| 506 | |
| 507 | if (mhi_chan->dir == DMA_TO_DEVICE) |
| 508 | atomic_inc(&mhi_cntrl->pending_pkts); |
| 509 | |
| 510 | if (likely(MHI_DB_ACCESS_VALID(mhi_cntrl))) { |
| 511 | read_lock_bh(&mhi_chan->lock); |
| 512 | mhi_ring_chan_db(mhi_cntrl, mhi_chan); |
| 513 | read_unlock_bh(&mhi_chan->lock); |
| 514 | } |
| 515 | |
| 516 | read_unlock_bh(&mhi_cntrl->pm_lock); |
| 517 | |
| 518 | return 0; |
| 519 | } |
| 520 | |
| 521 | int mhi_gen_tre(struct mhi_controller *mhi_cntrl, |
| 522 | struct mhi_chan *mhi_chan, |
| 523 | void *buf, |
| 524 | void *cb, |
| 525 | size_t buf_len, |
| 526 | enum MHI_FLAGS flags) |
| 527 | { |
| 528 | struct mhi_ring *buf_ring, *tre_ring; |
| 529 | struct mhi_tre *mhi_tre; |
| 530 | struct mhi_buf_info *buf_info; |
| 531 | int eot, eob, chain, bei; |
| 532 | int ret; |
| 533 | |
| 534 | buf_ring = &mhi_chan->buf_ring; |
| 535 | tre_ring = &mhi_chan->tre_ring; |
| 536 | |
| 537 | buf_info = buf_ring->wp; |
| 538 | buf_info->v_addr = buf; |
| 539 | buf_info->cb_buf = cb; |
| 540 | buf_info->wp = tre_ring->wp; |
| 541 | buf_info->dir = mhi_chan->dir; |
| 542 | buf_info->len = buf_len; |
| 543 | |
| 544 | ret = mhi_cntrl->map_single(mhi_cntrl, buf_info); |
| 545 | if (ret) |
| 546 | return ret; |
| 547 | |
| 548 | eob = !!(flags & MHI_EOB); |
| 549 | eot = !!(flags & MHI_EOT); |
| 550 | chain = !!(flags & MHI_CHAIN); |
| 551 | bei = !!(mhi_chan->intmod); |
| 552 | |
| 553 | mhi_tre = tre_ring->wp; |
| 554 | mhi_tre->ptr = MHI_TRE_DATA_PTR(buf_info->p_addr); |
| 555 | mhi_tre->dword[0] = MHI_TRE_DATA_DWORD0(buf_len); |
| 556 | mhi_tre->dword[1] = MHI_TRE_DATA_DWORD1(bei, eot, eob, chain); |
| 557 | |
| 558 | MHI_VERB("chan:%d WP:0x%llx TRE:0x%llx 0x%08x 0x%08x\n", mhi_chan->chan, |
| 559 | (u64)mhi_to_physical(tre_ring, mhi_tre), mhi_tre->ptr, |
| 560 | mhi_tre->dword[0], mhi_tre->dword[1]); |
| 561 | |
| 562 | /* increment WP */ |
| 563 | mhi_add_ring_element(mhi_cntrl, tre_ring); |
| 564 | mhi_add_ring_element(mhi_cntrl, buf_ring); |
| 565 | |
| 566 | return 0; |
| 567 | } |
| 568 | |
| 569 | int mhi_queue_buf(struct mhi_device *mhi_dev, |
| 570 | struct mhi_chan *mhi_chan, |
| 571 | void *buf, |
| 572 | size_t len, |
| 573 | enum MHI_FLAGS mflags) |
| 574 | { |
| 575 | struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; |
| 576 | struct mhi_ring *tre_ring; |
| 577 | unsigned long flags; |
| 578 | int ret; |
| 579 | |
| 580 | /* |
| 581 | * this check here only as a guard, it's always |
| 582 | * possible mhi can enter error while executing rest of function, |
| 583 | * which is not fatal so we do not need to hold pm_lock |
| 584 | */ |
| 585 | if (unlikely(MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state))) { |
| 586 | MHI_VERB("MHI is not in active state, pm_state:%s\n", |
| 587 | to_mhi_pm_state_str(mhi_cntrl->pm_state)); |
| 588 | |
| 589 | return -EIO; |
| 590 | } |
| 591 | |
| 592 | tre_ring = &mhi_chan->tre_ring; |
| 593 | if (mhi_is_ring_full(mhi_cntrl, tre_ring)) |
| 594 | return -ENOMEM; |
| 595 | |
| 596 | ret = mhi_chan->gen_tre(mhi_cntrl, mhi_chan, buf, buf, len, mflags); |
| 597 | if (unlikely(ret)) |
| 598 | return ret; |
| 599 | |
| 600 | read_lock_irqsave(&mhi_cntrl->pm_lock, flags); |
| 601 | |
| 602 | /* we're in M3 or transitioning to M3 */ |
| 603 | if (MHI_PM_IN_SUSPEND_STATE(mhi_cntrl->pm_state)) { |
| 604 | mhi_cntrl->runtime_get(mhi_cntrl, mhi_cntrl->priv_data); |
| 605 | mhi_cntrl->runtime_put(mhi_cntrl, mhi_cntrl->priv_data); |
| 606 | } |
| 607 | |
| 608 | /* toggle wake to exit out of M2 */ |
| 609 | mhi_cntrl->wake_toggle(mhi_cntrl); |
| 610 | |
| 611 | if (mhi_chan->dir == DMA_TO_DEVICE) |
| 612 | atomic_inc(&mhi_cntrl->pending_pkts); |
| 613 | |
| 614 | if (likely(MHI_DB_ACCESS_VALID(mhi_cntrl))) { |
| 615 | unsigned long flags; |
| 616 | |
| 617 | read_lock_irqsave(&mhi_chan->lock, flags); |
| 618 | mhi_ring_chan_db(mhi_cntrl, mhi_chan); |
| 619 | read_unlock_irqrestore(&mhi_chan->lock, flags); |
| 620 | } |
| 621 | |
| 622 | read_unlock_irqrestore(&mhi_cntrl->pm_lock, flags); |
| 623 | |
| 624 | return 0; |
| 625 | } |
| 626 | |
| 627 | /* destroy specific device */ |
| 628 | int mhi_destroy_device(struct device *dev, void *data) |
| 629 | { |
| 630 | struct mhi_device *mhi_dev; |
| 631 | struct mhi_controller *mhi_cntrl; |
| 632 | |
| 633 | if (dev->bus != &mhi_bus_type) |
| 634 | return 0; |
| 635 | |
| 636 | mhi_dev = to_mhi_device(dev); |
| 637 | mhi_cntrl = mhi_dev->mhi_cntrl; |
| 638 | |
| 639 | /* only destroying virtual devices thats attached to bus */ |
| 640 | if (mhi_dev->dev_type == MHI_CONTROLLER_TYPE) |
| 641 | return 0; |
| 642 | |
| 643 | MHI_LOG("destroy device for chan:%s\n", mhi_dev->chan_name); |
| 644 | |
| 645 | /* notify the client and remove the device from mhi bus */ |
| 646 | device_del(dev); |
| 647 | put_device(dev); |
| 648 | |
| 649 | return 0; |
| 650 | } |
| 651 | |
| 652 | int mhi_early_notify_device(struct device *dev, void *data) |
| 653 | { |
| 654 | struct mhi_device *mhi_dev = to_mhi_device(dev); |
| 655 | struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; |
| 656 | |
| 657 | /* skip early notification */ |
| 658 | if (!mhi_dev->early_notif) |
| 659 | return 0; |
| 660 | |
| 661 | MHI_LOG("Early notification for dev:%s\n", mhi_dev->chan_name); |
| 662 | |
| 663 | mhi_notify(mhi_dev, MHI_CB_FATAL_ERROR); |
| 664 | |
| 665 | return 0; |
| 666 | } |
| 667 | |
| 668 | void mhi_notify(struct mhi_device *mhi_dev, enum MHI_CB cb_reason) |
| 669 | { |
| 670 | struct mhi_driver *mhi_drv; |
| 671 | |
| 672 | if (!mhi_dev->dev.driver) |
| 673 | return; |
| 674 | |
| 675 | mhi_drv = to_mhi_driver(mhi_dev->dev.driver); |
| 676 | |
| 677 | if (mhi_drv->status_cb) |
| 678 | mhi_drv->status_cb(mhi_dev, cb_reason); |
| 679 | } |
| 680 | |
| 681 | static void mhi_assign_of_node(struct mhi_controller *mhi_cntrl, |
| 682 | struct mhi_device *mhi_dev) |
| 683 | { |
| 684 | struct device_node *controller, *node; |
| 685 | const char *dt_name; |
| 686 | int ret; |
| 687 | |
| 688 | controller = of_find_node_by_name(mhi_cntrl->of_node, "mhi_devices"); |
| 689 | if (!controller) |
| 690 | return; |
| 691 | |
| 692 | for_each_available_child_of_node(controller, node) { |
| 693 | ret = of_property_read_string(node, "mhi,chan", &dt_name); |
| 694 | if (ret) |
| 695 | continue; |
| 696 | if (!strcmp(mhi_dev->chan_name, dt_name)) { |
| 697 | mhi_dev->dev.of_node = node; |
| 698 | break; |
| 699 | } |
| 700 | } |
| 701 | } |
| 702 | |
| 703 | static ssize_t time_show(struct device *dev, |
| 704 | struct device_attribute *attr, |
| 705 | char *buf) |
| 706 | { |
| 707 | struct mhi_device *mhi_dev = to_mhi_device(dev); |
| 708 | struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; |
| 709 | u64 t_host, t_device; |
| 710 | int ret; |
| 711 | |
| 712 | ret = mhi_get_remote_time_sync(mhi_dev, &t_host, &t_device); |
| 713 | if (ret) { |
| 714 | MHI_ERR("Failed to obtain time, ret:%d\n", ret); |
| 715 | return ret; |
| 716 | } |
| 717 | |
| 718 | return scnprintf(buf, PAGE_SIZE, "local: %llu remote: %llu (ticks)\n", |
| 719 | t_host, t_device); |
| 720 | } |
| 721 | static DEVICE_ATTR_RO(time); |
| 722 | |
| 723 | static ssize_t time_us_show(struct device *dev, |
| 724 | struct device_attribute *attr, |
| 725 | char *buf) |
| 726 | { |
| 727 | struct mhi_device *mhi_dev = to_mhi_device(dev); |
| 728 | struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; |
| 729 | u64 t_host, t_device; |
| 730 | int ret; |
| 731 | |
| 732 | ret = mhi_get_remote_time_sync(mhi_dev, &t_host, &t_device); |
| 733 | if (ret) { |
| 734 | MHI_ERR("Failed to obtain time, ret:%d\n", ret); |
| 735 | return ret; |
| 736 | } |
| 737 | |
| 738 | return scnprintf(buf, PAGE_SIZE, "local: %llu remote: %llu (us)\n", |
| 739 | LOCAL_TICKS_TO_US(t_host), |
| 740 | REMOTE_TICKS_TO_US(t_device)); |
| 741 | } |
| 742 | static DEVICE_ATTR_RO(time_us); |
| 743 | |
| 744 | static struct attribute *mhi_tsync_attrs[] = { |
| 745 | &dev_attr_time.attr, |
| 746 | &dev_attr_time_us.attr, |
| 747 | NULL, |
| 748 | }; |
| 749 | |
| 750 | static const struct attribute_group mhi_tsync_group = { |
| 751 | .attrs = mhi_tsync_attrs, |
| 752 | }; |
| 753 | |
| 754 | void mhi_destroy_timesync(struct mhi_controller *mhi_cntrl) |
| 755 | { |
| 756 | if (mhi_cntrl->mhi_tsync) { |
| 757 | sysfs_remove_group(&mhi_cntrl->mhi_dev->dev.kobj, |
| 758 | &mhi_tsync_group); |
| 759 | kfree(mhi_cntrl->mhi_tsync); |
| 760 | mhi_cntrl->mhi_tsync = NULL; |
| 761 | } |
| 762 | } |
| 763 | |
| 764 | int mhi_create_timesync_sysfs(struct mhi_controller *mhi_cntrl) |
| 765 | { |
| 766 | return sysfs_create_group(&mhi_cntrl->mhi_dev->dev.kobj, |
| 767 | &mhi_tsync_group); |
| 768 | } |
| 769 | |
| 770 | static void mhi_create_time_sync_dev(struct mhi_controller *mhi_cntrl) |
| 771 | { |
| 772 | struct mhi_device *mhi_dev; |
| 773 | int ret; |
| 774 | |
| 775 | if (!MHI_IN_MISSION_MODE(mhi_cntrl->ee)) |
| 776 | return; |
| 777 | |
| 778 | mhi_dev = mhi_alloc_device(mhi_cntrl); |
| 779 | if (!mhi_dev) |
| 780 | return; |
| 781 | |
| 782 | mhi_dev->dev_type = MHI_TIMESYNC_TYPE; |
| 783 | mhi_dev->chan_name = "TIME_SYNC"; |
| 784 | dev_set_name(&mhi_dev->dev, "%04x_%02u.%02u.%02u_%s", mhi_dev->dev_id, |
| 785 | mhi_dev->domain, mhi_dev->bus, mhi_dev->slot, |
| 786 | mhi_dev->chan_name); |
| 787 | |
| 788 | /* add if there is a matching DT node */ |
| 789 | mhi_assign_of_node(mhi_cntrl, mhi_dev); |
| 790 | |
| 791 | ret = device_add(&mhi_dev->dev); |
| 792 | if (ret) { |
| 793 | MHI_ERR("Failed to register dev for chan:%s\n", |
| 794 | mhi_dev->chan_name); |
| 795 | mhi_dealloc_device(mhi_cntrl, mhi_dev); |
| 796 | return; |
| 797 | } |
| 798 | |
| 799 | mhi_cntrl->tsync_dev = mhi_dev; |
| 800 | } |
| 801 | |
| 802 | /* bind mhi channels into mhi devices */ |
| 803 | void mhi_create_devices(struct mhi_controller *mhi_cntrl) |
| 804 | { |
| 805 | int i; |
| 806 | struct mhi_chan *mhi_chan; |
| 807 | struct mhi_device *mhi_dev; |
| 808 | int ret; |
| 809 | |
| 810 | /* |
| 811 | * we need to create time sync device before creating other |
| 812 | * devices, because client may try to capture time during |
| 813 | * clint probe. |
| 814 | */ |
| 815 | mhi_create_time_sync_dev(mhi_cntrl); |
| 816 | |
| 817 | mhi_chan = mhi_cntrl->mhi_chan; |
| 818 | for (i = 0; i < mhi_cntrl->max_chan; i++, mhi_chan++) { |
| 819 | if (!mhi_chan->configured || mhi_chan->mhi_dev || |
| 820 | !(mhi_chan->ee_mask & BIT(mhi_cntrl->ee))) |
| 821 | continue; |
| 822 | mhi_dev = mhi_alloc_device(mhi_cntrl); |
| 823 | if (!mhi_dev) |
| 824 | return; |
| 825 | |
| 826 | mhi_dev->dev_type = MHI_XFER_TYPE; |
| 827 | switch (mhi_chan->dir) { |
| 828 | case DMA_TO_DEVICE: |
| 829 | mhi_dev->ul_chan = mhi_chan; |
| 830 | mhi_dev->ul_chan_id = mhi_chan->chan; |
| 831 | mhi_dev->ul_xfer = mhi_chan->queue_xfer; |
| 832 | mhi_dev->ul_event_id = mhi_chan->er_index; |
| 833 | break; |
| 834 | case DMA_NONE: |
| 835 | case DMA_BIDIRECTIONAL: |
| 836 | mhi_dev->ul_chan_id = mhi_chan->chan; |
| 837 | mhi_dev->ul_event_id = mhi_chan->er_index; |
| 838 | case DMA_FROM_DEVICE: |
| 839 | /* we use dl_chan for offload channels */ |
| 840 | mhi_dev->dl_chan = mhi_chan; |
| 841 | mhi_dev->dl_chan_id = mhi_chan->chan; |
| 842 | mhi_dev->dl_xfer = mhi_chan->queue_xfer; |
| 843 | mhi_dev->dl_event_id = mhi_chan->er_index; |
| 844 | } |
| 845 | |
| 846 | mhi_chan->mhi_dev = mhi_dev; |
| 847 | |
| 848 | /* check next channel if it matches */ |
| 849 | if ((i + 1) < mhi_cntrl->max_chan && mhi_chan[1].configured) { |
| 850 | if (!strcmp(mhi_chan[1].name, mhi_chan->name)) { |
| 851 | i++; |
| 852 | mhi_chan++; |
| 853 | if (mhi_chan->dir == DMA_TO_DEVICE) { |
| 854 | mhi_dev->ul_chan = mhi_chan; |
| 855 | mhi_dev->ul_chan_id = mhi_chan->chan; |
| 856 | mhi_dev->ul_xfer = mhi_chan->queue_xfer; |
| 857 | mhi_dev->ul_event_id = |
| 858 | mhi_chan->er_index; |
| 859 | } else { |
| 860 | mhi_dev->dl_chan = mhi_chan; |
| 861 | mhi_dev->dl_chan_id = mhi_chan->chan; |
| 862 | mhi_dev->dl_xfer = mhi_chan->queue_xfer; |
| 863 | mhi_dev->dl_event_id = |
| 864 | mhi_chan->er_index; |
| 865 | } |
| 866 | mhi_chan->mhi_dev = mhi_dev; |
| 867 | } |
| 868 | } |
| 869 | |
| 870 | mhi_dev->chan_name = mhi_chan->name; |
| 871 | dev_set_name(&mhi_dev->dev, "%04x_%02u.%02u.%02u_%s", |
| 872 | mhi_dev->dev_id, mhi_dev->domain, mhi_dev->bus, |
| 873 | mhi_dev->slot, mhi_dev->chan_name); |
| 874 | |
| 875 | /* add if there is a matching DT node */ |
| 876 | mhi_assign_of_node(mhi_cntrl, mhi_dev); |
| 877 | |
| 878 | /* |
| 879 | * if set, these device should get a early notification during |
| 880 | * early notification state |
| 881 | */ |
| 882 | mhi_dev->early_notif = |
| 883 | of_property_read_bool(mhi_dev->dev.of_node, |
| 884 | "mhi,early-notify"); |
| 885 | /* init wake source */ |
| 886 | if (mhi_dev->dl_chan && mhi_dev->dl_chan->wake_capable) |
| 887 | device_init_wakeup(&mhi_dev->dev, true); |
| 888 | |
| 889 | ret = device_add(&mhi_dev->dev); |
| 890 | if (ret) { |
| 891 | MHI_ERR("Failed to register dev for chan:%s\n", |
| 892 | mhi_dev->chan_name); |
| 893 | mhi_dealloc_device(mhi_cntrl, mhi_dev); |
| 894 | } |
| 895 | } |
| 896 | } |
| 897 | |
| 898 | static int parse_xfer_event(struct mhi_controller *mhi_cntrl, |
| 899 | struct mhi_tre *event, |
| 900 | struct mhi_chan *mhi_chan) |
| 901 | { |
| 902 | struct mhi_ring *buf_ring, *tre_ring; |
| 903 | u32 ev_code; |
| 904 | struct mhi_result result; |
| 905 | unsigned long flags = 0; |
| 906 | |
| 907 | ev_code = MHI_TRE_GET_EV_CODE(event); |
| 908 | buf_ring = &mhi_chan->buf_ring; |
| 909 | tre_ring = &mhi_chan->tre_ring; |
| 910 | |
| 911 | result.transaction_status = (ev_code == MHI_EV_CC_OVERFLOW) ? |
| 912 | -EOVERFLOW : 0; |
| 913 | |
| 914 | /* |
| 915 | * if it's a DB Event then we need to grab the lock |
| 916 | * with preemption disable and as a write because we |
| 917 | * have to update db register and another thread could |
| 918 | * be doing same. |
| 919 | */ |
| 920 | if (ev_code >= MHI_EV_CC_OOB) |
| 921 | write_lock_irqsave(&mhi_chan->lock, flags); |
| 922 | else |
| 923 | read_lock_bh(&mhi_chan->lock); |
| 924 | |
| 925 | if (mhi_chan->ch_state != MHI_CH_STATE_ENABLED) |
| 926 | goto end_process_tx_event; |
| 927 | |
| 928 | switch (ev_code) { |
| 929 | case MHI_EV_CC_OVERFLOW: |
| 930 | case MHI_EV_CC_EOB: |
| 931 | case MHI_EV_CC_EOT: |
| 932 | { |
| 933 | dma_addr_t ptr = MHI_TRE_GET_EV_PTR(event); |
| 934 | struct mhi_tre *local_rp, *ev_tre; |
| 935 | void *dev_rp; |
| 936 | struct mhi_buf_info *buf_info; |
| 937 | u16 xfer_len; |
| 938 | |
| 939 | /* Get the TRB this event points to */ |
| 940 | ev_tre = mhi_to_virtual(tre_ring, ptr); |
| 941 | |
| 942 | /* device rp after servicing the TREs */ |
| 943 | dev_rp = ev_tre + 1; |
| 944 | if (dev_rp >= (tre_ring->base + tre_ring->len)) |
| 945 | dev_rp = tre_ring->base; |
| 946 | |
| 947 | result.dir = mhi_chan->dir; |
| 948 | |
| 949 | /* local rp */ |
| 950 | local_rp = tre_ring->rp; |
| 951 | while (local_rp != dev_rp) { |
| 952 | buf_info = buf_ring->rp; |
| 953 | /* if it's last tre get len from the event */ |
| 954 | if (local_rp == ev_tre) |
| 955 | xfer_len = MHI_TRE_GET_EV_LEN(event); |
| 956 | else |
| 957 | xfer_len = buf_info->len; |
| 958 | |
| 959 | /* unmap if it's not premapped by client */ |
| 960 | if (likely(!buf_info->pre_mapped)) |
| 961 | mhi_cntrl->unmap_single(mhi_cntrl, buf_info); |
| 962 | |
| 963 | result.buf_addr = buf_info->cb_buf; |
Hemant Kumar | ebd869c | 2020-01-06 13:48:46 -0800 | [diff] [blame] | 964 | result.bytes_xferd = min_t(u16, xfer_len, |
| 965 | buf_info->len); |
Nitesh Gupta | 35b8ea6 | 2019-10-31 10:45:54 +0530 | [diff] [blame] | 966 | mhi_del_ring_element(mhi_cntrl, buf_ring); |
| 967 | mhi_del_ring_element(mhi_cntrl, tre_ring); |
| 968 | local_rp = tre_ring->rp; |
| 969 | |
| 970 | /* notify client */ |
| 971 | mhi_chan->xfer_cb(mhi_chan->mhi_dev, &result); |
| 972 | |
| 973 | if (mhi_chan->dir == DMA_TO_DEVICE) |
| 974 | atomic_dec(&mhi_cntrl->pending_pkts); |
| 975 | |
| 976 | /* |
| 977 | * recycle the buffer if buffer is pre-allocated, |
| 978 | * if there is error, not much we can do apart from |
| 979 | * dropping the packet |
| 980 | */ |
| 981 | if (mhi_chan->pre_alloc) { |
| 982 | if (mhi_queue_buf(mhi_chan->mhi_dev, mhi_chan, |
| 983 | buf_info->cb_buf, |
| 984 | buf_info->len, MHI_EOT)) { |
| 985 | MHI_ERR( |
| 986 | "Error recycling buffer for chan:%d\n", |
| 987 | mhi_chan->chan); |
| 988 | kfree(buf_info->cb_buf); |
| 989 | } |
| 990 | } |
| 991 | }; |
| 992 | break; |
| 993 | } /* CC_EOT */ |
| 994 | case MHI_EV_CC_OOB: |
| 995 | case MHI_EV_CC_DB_MODE: |
| 996 | { |
| 997 | unsigned long flags; |
| 998 | |
| 999 | MHI_VERB("DB_MODE/OOB Detected chan %d.\n", mhi_chan->chan); |
| 1000 | mhi_chan->db_cfg.db_mode = 1; |
| 1001 | read_lock_irqsave(&mhi_cntrl->pm_lock, flags); |
| 1002 | if (tre_ring->wp != tre_ring->rp && |
| 1003 | MHI_DB_ACCESS_VALID(mhi_cntrl)) { |
| 1004 | mhi_ring_chan_db(mhi_cntrl, mhi_chan); |
| 1005 | } |
| 1006 | read_unlock_irqrestore(&mhi_cntrl->pm_lock, flags); |
| 1007 | break; |
| 1008 | } |
| 1009 | case MHI_EV_CC_BAD_TRE: |
| 1010 | MHI_ASSERT(1, "Received BAD TRE event for ring"); |
| 1011 | break; |
| 1012 | default: |
| 1013 | MHI_CRITICAL("Unknown TX completion.\n"); |
| 1014 | |
| 1015 | break; |
| 1016 | } /* switch(MHI_EV_READ_CODE(EV_TRB_CODE,event)) */ |
| 1017 | |
| 1018 | end_process_tx_event: |
| 1019 | if (ev_code >= MHI_EV_CC_OOB) |
| 1020 | write_unlock_irqrestore(&mhi_chan->lock, flags); |
| 1021 | else |
| 1022 | read_unlock_bh(&mhi_chan->lock); |
| 1023 | |
| 1024 | return 0; |
| 1025 | } |
| 1026 | |
| 1027 | static int parse_rsc_event(struct mhi_controller *mhi_cntrl, |
| 1028 | struct mhi_tre *event, |
| 1029 | struct mhi_chan *mhi_chan) |
| 1030 | { |
| 1031 | struct mhi_ring *buf_ring, *tre_ring; |
| 1032 | struct mhi_buf_info *buf_info; |
| 1033 | struct mhi_result result; |
| 1034 | int ev_code; |
| 1035 | u32 cookie; /* offset to local descriptor */ |
| 1036 | u16 xfer_len; |
| 1037 | |
| 1038 | buf_ring = &mhi_chan->buf_ring; |
| 1039 | tre_ring = &mhi_chan->tre_ring; |
| 1040 | |
| 1041 | ev_code = MHI_TRE_GET_EV_CODE(event); |
| 1042 | cookie = MHI_TRE_GET_EV_COOKIE(event); |
| 1043 | xfer_len = MHI_TRE_GET_EV_LEN(event); |
| 1044 | |
| 1045 | /* received out of bound cookie */ |
| 1046 | MHI_ASSERT(cookie >= buf_ring->len, "Invalid Cookie\n"); |
| 1047 | |
| 1048 | buf_info = buf_ring->base + cookie; |
| 1049 | |
| 1050 | result.transaction_status = (ev_code == MHI_EV_CC_OVERFLOW) ? |
| 1051 | -EOVERFLOW : 0; |
| 1052 | result.bytes_xferd = xfer_len; |
| 1053 | result.buf_addr = buf_info->cb_buf; |
| 1054 | result.dir = mhi_chan->dir; |
| 1055 | |
| 1056 | read_lock_bh(&mhi_chan->lock); |
| 1057 | |
| 1058 | if (mhi_chan->ch_state != MHI_CH_STATE_ENABLED) |
| 1059 | goto end_process_rsc_event; |
| 1060 | |
| 1061 | MHI_ASSERT(!buf_info->used, "TRE already Freed\n"); |
| 1062 | |
| 1063 | /* notify the client */ |
| 1064 | mhi_chan->xfer_cb(mhi_chan->mhi_dev, &result); |
| 1065 | |
| 1066 | /* |
| 1067 | * Note: We're arbitrarily incrementing RP even though, completion |
| 1068 | * packet we processed might not be the same one, reason we can do this |
| 1069 | * is because device guaranteed to cache descriptors in order it |
| 1070 | * receive, so even though completion event is different we can re-use |
| 1071 | * all descriptors in between. |
| 1072 | * Example: |
| 1073 | * Transfer Ring has descriptors: A, B, C, D |
| 1074 | * Last descriptor host queue is D (WP) and first descriptor |
| 1075 | * host queue is A (RP). |
| 1076 | * The completion event we just serviced is descriptor C. |
| 1077 | * Then we can safely queue descriptors to replace A, B, and C |
| 1078 | * even though host did not receive any completions. |
| 1079 | */ |
| 1080 | mhi_del_ring_element(mhi_cntrl, tre_ring); |
| 1081 | buf_info->used = false; |
| 1082 | |
| 1083 | end_process_rsc_event: |
| 1084 | read_unlock_bh(&mhi_chan->lock); |
| 1085 | |
| 1086 | return 0; |
| 1087 | } |
| 1088 | |
| 1089 | static void mhi_process_cmd_completion(struct mhi_controller *mhi_cntrl, |
| 1090 | struct mhi_tre *tre) |
| 1091 | { |
| 1092 | dma_addr_t ptr = MHI_TRE_GET_EV_PTR(tre); |
| 1093 | struct mhi_cmd *cmd_ring = &mhi_cntrl->mhi_cmd[PRIMARY_CMD_RING]; |
| 1094 | struct mhi_ring *mhi_ring = &cmd_ring->ring; |
| 1095 | struct mhi_tre *cmd_pkt; |
| 1096 | struct mhi_chan *mhi_chan; |
| 1097 | struct mhi_timesync *mhi_tsync; |
| 1098 | enum mhi_cmd_type type; |
| 1099 | u32 chan; |
| 1100 | |
| 1101 | cmd_pkt = mhi_to_virtual(mhi_ring, ptr); |
| 1102 | |
| 1103 | /* out of order completion received */ |
| 1104 | MHI_ASSERT(cmd_pkt != mhi_ring->rp, "Out of order cmd completion"); |
| 1105 | |
| 1106 | type = MHI_TRE_GET_CMD_TYPE(cmd_pkt); |
| 1107 | |
| 1108 | if (type == MHI_CMD_TYPE_TSYNC) { |
| 1109 | mhi_tsync = mhi_cntrl->mhi_tsync; |
| 1110 | mhi_tsync->ccs = MHI_TRE_GET_EV_CODE(tre); |
| 1111 | complete(&mhi_tsync->completion); |
| 1112 | } else { |
| 1113 | chan = MHI_TRE_GET_CMD_CHID(cmd_pkt); |
Hemant Kumar | 4f836c2 | 2020-01-14 17:35:10 -0800 | [diff] [blame] | 1114 | if (chan >= mhi_cntrl->max_chan) { |
| 1115 | MHI_ERR("invalid channel id %u\n", chan); |
Hemant Kumar | 36f7a16 | 2020-02-10 15:44:53 -0800 | [diff] [blame] | 1116 | goto del_ring_el; |
Hemant Kumar | 4f836c2 | 2020-01-14 17:35:10 -0800 | [diff] [blame] | 1117 | } |
Nitesh Gupta | 35b8ea6 | 2019-10-31 10:45:54 +0530 | [diff] [blame] | 1118 | mhi_chan = &mhi_cntrl->mhi_chan[chan]; |
| 1119 | write_lock_bh(&mhi_chan->lock); |
| 1120 | mhi_chan->ccs = MHI_TRE_GET_EV_CODE(tre); |
| 1121 | complete(&mhi_chan->completion); |
| 1122 | write_unlock_bh(&mhi_chan->lock); |
| 1123 | } |
| 1124 | |
Hemant Kumar | 36f7a16 | 2020-02-10 15:44:53 -0800 | [diff] [blame] | 1125 | del_ring_el: |
Nitesh Gupta | 35b8ea6 | 2019-10-31 10:45:54 +0530 | [diff] [blame] | 1126 | mhi_del_ring_element(mhi_cntrl, mhi_ring); |
| 1127 | } |
| 1128 | |
| 1129 | int mhi_process_ctrl_ev_ring(struct mhi_controller *mhi_cntrl, |
| 1130 | struct mhi_event *mhi_event, |
| 1131 | u32 event_quota) |
| 1132 | { |
| 1133 | struct mhi_tre *dev_rp, *local_rp; |
| 1134 | struct mhi_ring *ev_ring = &mhi_event->ring; |
| 1135 | struct mhi_event_ctxt *er_ctxt = |
| 1136 | &mhi_cntrl->mhi_ctxt->er_ctxt[mhi_event->er_index]; |
| 1137 | int count = 0; |
| 1138 | |
| 1139 | /* |
| 1140 | * this is a quick check to avoid unnecessary event processing |
| 1141 | * in case we already in error state, but it's still possible |
| 1142 | * to transition to error state while processing events |
| 1143 | */ |
| 1144 | if (unlikely(MHI_EVENT_ACCESS_INVALID(mhi_cntrl->pm_state))) { |
| 1145 | MHI_ERR("No EV access, PM_STATE:%s\n", |
| 1146 | to_mhi_pm_state_str(mhi_cntrl->pm_state)); |
| 1147 | return -EIO; |
| 1148 | } |
| 1149 | |
| 1150 | dev_rp = mhi_to_virtual(ev_ring, er_ctxt->rp); |
| 1151 | local_rp = ev_ring->rp; |
| 1152 | |
| 1153 | while (dev_rp != local_rp) { |
| 1154 | enum MHI_PKT_TYPE type = MHI_TRE_GET_EV_TYPE(local_rp); |
| 1155 | |
| 1156 | MHI_VERB("Processing Event:0x%llx 0x%08x 0x%08x\n", |
| 1157 | local_rp->ptr, local_rp->dword[0], local_rp->dword[1]); |
| 1158 | |
| 1159 | switch (type) { |
| 1160 | case MHI_PKT_TYPE_STATE_CHANGE_EVENT: |
| 1161 | { |
| 1162 | enum mhi_dev_state new_state; |
| 1163 | |
| 1164 | new_state = MHI_TRE_GET_EV_STATE(local_rp); |
| 1165 | |
| 1166 | MHI_LOG("MHI state change event to state:%s\n", |
| 1167 | TO_MHI_STATE_STR(new_state)); |
| 1168 | |
| 1169 | switch (new_state) { |
| 1170 | case MHI_STATE_M0: |
| 1171 | mhi_pm_m0_transition(mhi_cntrl); |
| 1172 | break; |
| 1173 | case MHI_STATE_M1: |
| 1174 | mhi_pm_m1_transition(mhi_cntrl); |
| 1175 | break; |
| 1176 | case MHI_STATE_M3: |
| 1177 | mhi_pm_m3_transition(mhi_cntrl); |
| 1178 | break; |
| 1179 | case MHI_STATE_SYS_ERR: |
| 1180 | { |
| 1181 | enum MHI_PM_STATE new_state; |
| 1182 | |
| 1183 | MHI_ERR("MHI system error detected\n"); |
| 1184 | write_lock_irq(&mhi_cntrl->pm_lock); |
| 1185 | new_state = mhi_tryset_pm_state(mhi_cntrl, |
| 1186 | MHI_PM_SYS_ERR_DETECT); |
| 1187 | write_unlock_irq(&mhi_cntrl->pm_lock); |
| 1188 | if (new_state == MHI_PM_SYS_ERR_DETECT) |
| 1189 | schedule_work( |
| 1190 | &mhi_cntrl->syserr_worker); |
| 1191 | break; |
| 1192 | } |
| 1193 | default: |
| 1194 | MHI_ERR("Unsupported STE:%s\n", |
| 1195 | TO_MHI_STATE_STR(new_state)); |
| 1196 | } |
| 1197 | |
| 1198 | break; |
| 1199 | } |
| 1200 | case MHI_PKT_TYPE_CMD_COMPLETION_EVENT: |
| 1201 | mhi_process_cmd_completion(mhi_cntrl, local_rp); |
| 1202 | break; |
| 1203 | case MHI_PKT_TYPE_EE_EVENT: |
| 1204 | { |
| 1205 | enum MHI_ST_TRANSITION st = MHI_ST_TRANSITION_MAX; |
| 1206 | enum mhi_ee event = MHI_TRE_GET_EV_EXECENV(local_rp); |
| 1207 | |
| 1208 | /* convert device ee to host ee */ |
| 1209 | event = mhi_translate_dev_ee(mhi_cntrl, event); |
| 1210 | |
| 1211 | MHI_LOG("MHI EE received event:%s\n", |
| 1212 | TO_MHI_EXEC_STR(event)); |
| 1213 | switch (event) { |
| 1214 | case MHI_EE_SBL: |
| 1215 | st = MHI_ST_TRANSITION_SBL; |
| 1216 | break; |
| 1217 | case MHI_EE_WFW: |
| 1218 | case MHI_EE_AMSS: |
| 1219 | st = MHI_ST_TRANSITION_MISSION_MODE; |
| 1220 | break; |
| 1221 | case MHI_EE_RDDM: |
| 1222 | mhi_cntrl->status_cb(mhi_cntrl, |
| 1223 | mhi_cntrl->priv_data, |
| 1224 | MHI_CB_EE_RDDM); |
| 1225 | write_lock_irq(&mhi_cntrl->pm_lock); |
| 1226 | mhi_cntrl->ee = event; |
| 1227 | write_unlock_irq(&mhi_cntrl->pm_lock); |
| 1228 | wake_up_all(&mhi_cntrl->state_event); |
| 1229 | break; |
| 1230 | default: |
| 1231 | MHI_ERR("Unhandled EE event:%s\n", |
| 1232 | TO_MHI_EXEC_STR(event)); |
| 1233 | } |
| 1234 | if (st != MHI_ST_TRANSITION_MAX) |
| 1235 | mhi_queue_state_transition(mhi_cntrl, st); |
| 1236 | |
| 1237 | break; |
| 1238 | } |
| 1239 | default: |
| 1240 | MHI_ERR("Unhandled Event: 0x%x\n", type); |
| 1241 | break; |
| 1242 | } |
| 1243 | |
| 1244 | mhi_recycle_ev_ring_element(mhi_cntrl, ev_ring); |
| 1245 | local_rp = ev_ring->rp; |
| 1246 | dev_rp = mhi_to_virtual(ev_ring, er_ctxt->rp); |
| 1247 | count++; |
| 1248 | } |
| 1249 | |
| 1250 | read_lock_bh(&mhi_cntrl->pm_lock); |
| 1251 | if (likely(MHI_DB_ACCESS_VALID(mhi_cntrl))) |
| 1252 | mhi_ring_er_db(mhi_event); |
| 1253 | read_unlock_bh(&mhi_cntrl->pm_lock); |
| 1254 | |
| 1255 | MHI_VERB("exit er_index:%u\n", mhi_event->er_index); |
| 1256 | |
| 1257 | return count; |
| 1258 | } |
| 1259 | |
| 1260 | int mhi_process_data_event_ring(struct mhi_controller *mhi_cntrl, |
| 1261 | struct mhi_event *mhi_event, |
| 1262 | u32 event_quota) |
| 1263 | { |
| 1264 | struct mhi_tre *dev_rp, *local_rp; |
| 1265 | struct mhi_ring *ev_ring = &mhi_event->ring; |
| 1266 | struct mhi_event_ctxt *er_ctxt = |
| 1267 | &mhi_cntrl->mhi_ctxt->er_ctxt[mhi_event->er_index]; |
| 1268 | int count = 0; |
| 1269 | u32 chan; |
| 1270 | struct mhi_chan *mhi_chan; |
| 1271 | |
| 1272 | if (unlikely(MHI_EVENT_ACCESS_INVALID(mhi_cntrl->pm_state))) { |
| 1273 | MHI_ERR("No EV access, PM_STATE:%s\n", |
| 1274 | to_mhi_pm_state_str(mhi_cntrl->pm_state)); |
| 1275 | return -EIO; |
| 1276 | } |
| 1277 | |
| 1278 | dev_rp = mhi_to_virtual(ev_ring, er_ctxt->rp); |
| 1279 | local_rp = ev_ring->rp; |
| 1280 | |
| 1281 | while (dev_rp != local_rp && event_quota > 0) { |
| 1282 | enum MHI_PKT_TYPE type = MHI_TRE_GET_EV_TYPE(local_rp); |
| 1283 | |
| 1284 | MHI_VERB("Processing Event:0x%llx 0x%08x 0x%08x\n", |
| 1285 | local_rp->ptr, local_rp->dword[0], local_rp->dword[1]); |
| 1286 | |
| 1287 | chan = MHI_TRE_GET_EV_CHID(local_rp); |
Hemant Kumar | 146e6bb | 2020-02-06 17:32:38 -0800 | [diff] [blame] | 1288 | if (chan >= mhi_cntrl->max_chan) { |
| 1289 | MHI_ERR("invalid channel id %u\n", chan); |
| 1290 | continue; |
| 1291 | } |
Nitesh Gupta | 35b8ea6 | 2019-10-31 10:45:54 +0530 | [diff] [blame] | 1292 | mhi_chan = &mhi_cntrl->mhi_chan[chan]; |
| 1293 | |
| 1294 | if (likely(type == MHI_PKT_TYPE_TX_EVENT)) { |
| 1295 | parse_xfer_event(mhi_cntrl, local_rp, mhi_chan); |
| 1296 | event_quota--; |
| 1297 | } else if (type == MHI_PKT_TYPE_RSC_TX_EVENT) { |
| 1298 | parse_rsc_event(mhi_cntrl, local_rp, mhi_chan); |
| 1299 | event_quota--; |
| 1300 | } |
| 1301 | |
| 1302 | mhi_recycle_ev_ring_element(mhi_cntrl, ev_ring); |
| 1303 | local_rp = ev_ring->rp; |
| 1304 | dev_rp = mhi_to_virtual(ev_ring, er_ctxt->rp); |
| 1305 | count++; |
| 1306 | } |
| 1307 | read_lock_bh(&mhi_cntrl->pm_lock); |
| 1308 | if (likely(MHI_DB_ACCESS_VALID(mhi_cntrl))) |
| 1309 | mhi_ring_er_db(mhi_event); |
| 1310 | read_unlock_bh(&mhi_cntrl->pm_lock); |
| 1311 | |
| 1312 | MHI_VERB("exit er_index:%u\n", mhi_event->er_index); |
| 1313 | |
| 1314 | return count; |
| 1315 | } |
| 1316 | |
| 1317 | int mhi_process_tsync_event_ring(struct mhi_controller *mhi_cntrl, |
| 1318 | struct mhi_event *mhi_event, |
| 1319 | u32 event_quota) |
| 1320 | { |
| 1321 | struct mhi_tre *dev_rp, *local_rp; |
| 1322 | struct mhi_ring *ev_ring = &mhi_event->ring; |
| 1323 | struct mhi_event_ctxt *er_ctxt = |
| 1324 | &mhi_cntrl->mhi_ctxt->er_ctxt[mhi_event->er_index]; |
| 1325 | struct mhi_timesync *mhi_tsync = mhi_cntrl->mhi_tsync; |
| 1326 | int count = 0; |
| 1327 | u32 sequence; |
| 1328 | u64 remote_time; |
| 1329 | |
| 1330 | if (unlikely(MHI_EVENT_ACCESS_INVALID(mhi_cntrl->pm_state))) { |
| 1331 | MHI_ERR("No EV access, PM_STATE:%s\n", |
| 1332 | to_mhi_pm_state_str(mhi_cntrl->pm_state)); |
| 1333 | read_unlock_bh(&mhi_cntrl->pm_lock); |
| 1334 | return -EIO; |
| 1335 | } |
| 1336 | |
| 1337 | dev_rp = mhi_to_virtual(ev_ring, er_ctxt->rp); |
| 1338 | local_rp = ev_ring->rp; |
| 1339 | |
| 1340 | while (dev_rp != local_rp) { |
| 1341 | enum MHI_PKT_TYPE type = MHI_TRE_GET_EV_TYPE(local_rp); |
| 1342 | struct tsync_node *tsync_node; |
| 1343 | |
| 1344 | MHI_VERB("Processing Event:0x%llx 0x%08x 0x%08x\n", |
| 1345 | local_rp->ptr, local_rp->dword[0], local_rp->dword[1]); |
| 1346 | |
| 1347 | MHI_ASSERT(type != MHI_PKT_TYPE_TSYNC_EVENT, "!TSYNC event"); |
| 1348 | |
| 1349 | sequence = MHI_TRE_GET_EV_TSYNC_SEQ(local_rp); |
| 1350 | remote_time = MHI_TRE_GET_EV_TIME(local_rp); |
| 1351 | |
| 1352 | do { |
| 1353 | spin_lock_irq(&mhi_tsync->lock); |
| 1354 | tsync_node = list_first_entry_or_null(&mhi_tsync->head, |
| 1355 | struct tsync_node, node); |
| 1356 | MHI_ASSERT(!tsync_node, "Unexpected Event"); |
| 1357 | |
| 1358 | if (unlikely(!tsync_node)) |
| 1359 | break; |
| 1360 | |
| 1361 | list_del(&tsync_node->node); |
| 1362 | spin_unlock_irq(&mhi_tsync->lock); |
| 1363 | |
| 1364 | /* |
| 1365 | * device may not able to process all time sync commands |
| 1366 | * host issue and only process last command it receive |
| 1367 | */ |
| 1368 | if (tsync_node->sequence == sequence) { |
| 1369 | tsync_node->cb_func(tsync_node->mhi_dev, |
| 1370 | sequence, |
| 1371 | tsync_node->local_time, |
| 1372 | remote_time); |
| 1373 | kfree(tsync_node); |
| 1374 | } else { |
| 1375 | kfree(tsync_node); |
| 1376 | } |
| 1377 | } while (true); |
| 1378 | |
| 1379 | mhi_recycle_ev_ring_element(mhi_cntrl, ev_ring); |
| 1380 | local_rp = ev_ring->rp; |
| 1381 | dev_rp = mhi_to_virtual(ev_ring, er_ctxt->rp); |
| 1382 | count++; |
| 1383 | } |
| 1384 | |
| 1385 | read_lock_bh(&mhi_cntrl->pm_lock); |
| 1386 | if (likely(MHI_DB_ACCESS_VALID(mhi_cntrl))) |
| 1387 | mhi_ring_er_db(mhi_event); |
| 1388 | read_unlock_bh(&mhi_cntrl->pm_lock); |
| 1389 | |
| 1390 | MHI_VERB("exit er_index:%u\n", mhi_event->er_index); |
| 1391 | |
| 1392 | return count; |
| 1393 | } |
| 1394 | |
| 1395 | int mhi_process_bw_scale_ev_ring(struct mhi_controller *mhi_cntrl, |
| 1396 | struct mhi_event *mhi_event, |
| 1397 | u32 event_quota) |
| 1398 | { |
| 1399 | struct mhi_tre *dev_rp; |
| 1400 | struct mhi_ring *ev_ring = &mhi_event->ring; |
| 1401 | struct mhi_event_ctxt *er_ctxt = |
| 1402 | &mhi_cntrl->mhi_ctxt->er_ctxt[mhi_event->er_index]; |
| 1403 | struct mhi_link_info link_info, *cur_info = &mhi_cntrl->mhi_link_info; |
| 1404 | int result, ret = 0; |
| 1405 | |
| 1406 | mutex_lock(&mhi_cntrl->pm_mutex); |
| 1407 | |
| 1408 | if (unlikely(MHI_EVENT_ACCESS_INVALID(mhi_cntrl->pm_state))) { |
| 1409 | MHI_LOG("No EV access, PM_STATE:%s\n", |
| 1410 | to_mhi_pm_state_str(mhi_cntrl->pm_state)); |
| 1411 | ret = -EIO; |
| 1412 | goto exit_bw_process; |
| 1413 | } |
| 1414 | |
| 1415 | /* |
| 1416 | * BW change is not process during suspend since we're suspending link, |
| 1417 | * host will process it during resume |
| 1418 | */ |
| 1419 | if (MHI_PM_IN_SUSPEND_STATE(mhi_cntrl->pm_state)) { |
| 1420 | ret = -EACCES; |
| 1421 | goto exit_bw_process; |
| 1422 | } |
| 1423 | |
| 1424 | spin_lock_bh(&mhi_event->lock); |
| 1425 | dev_rp = mhi_to_virtual(ev_ring, er_ctxt->rp); |
| 1426 | |
| 1427 | if (ev_ring->rp == dev_rp) { |
| 1428 | spin_unlock_bh(&mhi_event->lock); |
| 1429 | goto exit_bw_process; |
| 1430 | } |
| 1431 | |
| 1432 | /* if rp points to base, we need to wrap it around */ |
| 1433 | if (dev_rp == ev_ring->base) |
| 1434 | dev_rp = ev_ring->base + ev_ring->len; |
| 1435 | dev_rp--; |
| 1436 | |
| 1437 | MHI_ASSERT(MHI_TRE_GET_EV_TYPE(dev_rp) != MHI_PKT_TYPE_BW_REQ_EVENT, |
| 1438 | "!BW SCALE REQ event"); |
| 1439 | |
| 1440 | link_info.target_link_speed = MHI_TRE_GET_EV_LINKSPEED(dev_rp); |
| 1441 | link_info.target_link_width = MHI_TRE_GET_EV_LINKWIDTH(dev_rp); |
| 1442 | link_info.sequence_num = MHI_TRE_GET_EV_BW_REQ_SEQ(dev_rp); |
| 1443 | |
| 1444 | MHI_VERB("Received BW_REQ with seq:%d link speed:0x%x width:0x%x\n", |
| 1445 | link_info.sequence_num, |
| 1446 | link_info.target_link_speed, |
| 1447 | link_info.target_link_width); |
| 1448 | |
| 1449 | /* fast forward to currently processed element and recycle er */ |
| 1450 | ev_ring->rp = dev_rp; |
| 1451 | ev_ring->wp = dev_rp - 1; |
| 1452 | if (ev_ring->wp < ev_ring->base) |
| 1453 | ev_ring->wp = ev_ring->base + ev_ring->len - ev_ring->el_size; |
| 1454 | mhi_recycle_ev_ring_element(mhi_cntrl, ev_ring); |
| 1455 | |
| 1456 | read_lock_bh(&mhi_cntrl->pm_lock); |
| 1457 | if (likely(MHI_DB_ACCESS_VALID(mhi_cntrl))) |
| 1458 | mhi_ring_er_db(mhi_event); |
| 1459 | read_unlock_bh(&mhi_cntrl->pm_lock); |
| 1460 | spin_unlock_bh(&mhi_event->lock); |
| 1461 | |
| 1462 | ret = mhi_cntrl->bw_scale(mhi_cntrl, &link_info); |
| 1463 | if (!ret) |
| 1464 | *cur_info = link_info; |
| 1465 | |
| 1466 | result = ret ? MHI_BW_SCALE_NACK : 0; |
| 1467 | |
| 1468 | read_lock_bh(&mhi_cntrl->pm_lock); |
| 1469 | if (likely(MHI_DB_ACCESS_VALID(mhi_cntrl))) |
| 1470 | mhi_write_reg(mhi_cntrl, mhi_cntrl->bw_scale_db, 0, |
| 1471 | MHI_BW_SCALE_RESULT(result, |
| 1472 | link_info.sequence_num)); |
| 1473 | read_unlock_bh(&mhi_cntrl->pm_lock); |
| 1474 | |
| 1475 | exit_bw_process: |
| 1476 | MHI_VERB("exit er_index:%u\n", mhi_event->er_index); |
| 1477 | |
| 1478 | mutex_unlock(&mhi_cntrl->pm_mutex); |
| 1479 | |
| 1480 | return ret; |
| 1481 | } |
| 1482 | |
| 1483 | void mhi_ev_task(unsigned long data) |
| 1484 | { |
| 1485 | struct mhi_event *mhi_event = (struct mhi_event *)data; |
| 1486 | struct mhi_controller *mhi_cntrl = mhi_event->mhi_cntrl; |
| 1487 | |
| 1488 | MHI_VERB("Enter for ev_index:%d\n", mhi_event->er_index); |
| 1489 | |
| 1490 | /* process all pending events */ |
| 1491 | spin_lock_bh(&mhi_event->lock); |
| 1492 | mhi_event->process_event(mhi_cntrl, mhi_event, U32_MAX); |
| 1493 | spin_unlock_bh(&mhi_event->lock); |
| 1494 | } |
| 1495 | |
| 1496 | void mhi_ctrl_ev_task(unsigned long data) |
| 1497 | { |
| 1498 | struct mhi_event *mhi_event = (struct mhi_event *)data; |
| 1499 | struct mhi_controller *mhi_cntrl = mhi_event->mhi_cntrl; |
| 1500 | enum mhi_dev_state state; |
| 1501 | enum MHI_PM_STATE pm_state = 0; |
| 1502 | int ret; |
| 1503 | |
| 1504 | MHI_VERB("Enter for ev_index:%d\n", mhi_event->er_index); |
| 1505 | |
| 1506 | /* |
| 1507 | * we can check pm_state w/o a lock here because there is no way |
| 1508 | * pm_state can change from reg access valid to no access while this |
| 1509 | * therad being executed. |
| 1510 | */ |
| 1511 | if (!MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) { |
| 1512 | /* |
| 1513 | * we may have a pending event but not allowed to |
| 1514 | * process it since we probably in a suspended state, |
| 1515 | * trigger a resume. |
| 1516 | */ |
| 1517 | mhi_cntrl->runtime_get(mhi_cntrl, mhi_cntrl->priv_data); |
| 1518 | mhi_cntrl->runtime_put(mhi_cntrl, mhi_cntrl->priv_data); |
| 1519 | return; |
| 1520 | } |
| 1521 | |
| 1522 | /* process ctrl events events */ |
| 1523 | ret = mhi_event->process_event(mhi_cntrl, mhi_event, U32_MAX); |
| 1524 | |
| 1525 | /* |
| 1526 | * we received a MSI but no events to process maybe device went to |
| 1527 | * SYS_ERR state, check the state |
| 1528 | */ |
| 1529 | if (!ret) { |
| 1530 | write_lock_irq(&mhi_cntrl->pm_lock); |
| 1531 | state = mhi_get_mhi_state(mhi_cntrl); |
| 1532 | if (state == MHI_STATE_SYS_ERR) { |
| 1533 | MHI_ERR("MHI system error detected\n"); |
| 1534 | pm_state = mhi_tryset_pm_state(mhi_cntrl, |
| 1535 | MHI_PM_SYS_ERR_DETECT); |
| 1536 | } |
| 1537 | write_unlock_irq(&mhi_cntrl->pm_lock); |
| 1538 | if (pm_state == MHI_PM_SYS_ERR_DETECT) |
| 1539 | schedule_work(&mhi_cntrl->syserr_worker); |
| 1540 | } |
| 1541 | } |
| 1542 | |
| 1543 | irqreturn_t mhi_msi_handlr(int irq_number, void *dev) |
| 1544 | { |
| 1545 | struct mhi_event *mhi_event = dev; |
| 1546 | struct mhi_controller *mhi_cntrl = mhi_event->mhi_cntrl; |
| 1547 | struct mhi_event_ctxt *er_ctxt = |
| 1548 | &mhi_cntrl->mhi_ctxt->er_ctxt[mhi_event->er_index]; |
| 1549 | struct mhi_ring *ev_ring = &mhi_event->ring; |
| 1550 | void *dev_rp = mhi_to_virtual(ev_ring, er_ctxt->rp); |
| 1551 | |
| 1552 | /* confirm ER has pending events to process before scheduling work */ |
| 1553 | if (ev_ring->rp == dev_rp) |
| 1554 | return IRQ_HANDLED; |
| 1555 | |
| 1556 | /* client managed event ring, notify pending data */ |
| 1557 | if (mhi_event->cl_manage) { |
| 1558 | struct mhi_chan *mhi_chan = mhi_event->mhi_chan; |
| 1559 | struct mhi_device *mhi_dev = mhi_chan->mhi_dev; |
| 1560 | |
| 1561 | if (mhi_dev) |
| 1562 | mhi_dev->status_cb(mhi_dev, MHI_CB_PENDING_DATA); |
| 1563 | |
| 1564 | return IRQ_HANDLED; |
| 1565 | } |
| 1566 | |
| 1567 | if (IS_MHI_ER_PRIORITY_HIGH(mhi_event)) |
| 1568 | tasklet_hi_schedule(&mhi_event->task); |
| 1569 | else |
| 1570 | tasklet_schedule(&mhi_event->task); |
| 1571 | |
| 1572 | return IRQ_HANDLED; |
| 1573 | } |
| 1574 | |
| 1575 | /* this is the threaded fn */ |
| 1576 | irqreturn_t mhi_intvec_threaded_handlr(int irq_number, void *dev) |
| 1577 | { |
| 1578 | struct mhi_controller *mhi_cntrl = dev; |
| 1579 | enum mhi_dev_state state = MHI_STATE_MAX; |
| 1580 | enum MHI_PM_STATE pm_state = 0; |
| 1581 | enum mhi_ee ee = 0; |
| 1582 | |
| 1583 | MHI_VERB("Enter\n"); |
| 1584 | |
| 1585 | write_lock_irq(&mhi_cntrl->pm_lock); |
| 1586 | if (MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) { |
| 1587 | state = mhi_get_mhi_state(mhi_cntrl); |
| 1588 | ee = mhi_cntrl->ee; |
| 1589 | mhi_cntrl->ee = mhi_get_exec_env(mhi_cntrl); |
| 1590 | MHI_LOG("device ee:%s dev_state:%s\n", |
| 1591 | TO_MHI_EXEC_STR(mhi_cntrl->ee), |
| 1592 | TO_MHI_STATE_STR(state)); |
| 1593 | } |
| 1594 | |
| 1595 | if (state == MHI_STATE_SYS_ERR) { |
| 1596 | MHI_ERR("MHI system error detected\n"); |
| 1597 | pm_state = mhi_tryset_pm_state(mhi_cntrl, |
| 1598 | MHI_PM_SYS_ERR_DETECT); |
| 1599 | } |
| 1600 | write_unlock_irq(&mhi_cntrl->pm_lock); |
| 1601 | |
| 1602 | /* if device in rddm don't bother processing sys error */ |
| 1603 | if (mhi_cntrl->ee == MHI_EE_RDDM) { |
| 1604 | if (mhi_cntrl->ee != ee) { |
| 1605 | mhi_cntrl->status_cb(mhi_cntrl, mhi_cntrl->priv_data, |
| 1606 | MHI_CB_EE_RDDM); |
| 1607 | wake_up_all(&mhi_cntrl->state_event); |
| 1608 | } |
| 1609 | goto exit_intvec; |
| 1610 | } |
| 1611 | |
| 1612 | if (pm_state == MHI_PM_SYS_ERR_DETECT) { |
| 1613 | wake_up_all(&mhi_cntrl->state_event); |
| 1614 | |
| 1615 | /* for fatal errors, we let controller decide next step */ |
| 1616 | if (MHI_IN_PBL(ee)) |
| 1617 | mhi_cntrl->status_cb(mhi_cntrl, mhi_cntrl->priv_data, |
| 1618 | MHI_CB_FATAL_ERROR); |
| 1619 | else |
| 1620 | schedule_work(&mhi_cntrl->syserr_worker); |
| 1621 | } |
| 1622 | |
| 1623 | exit_intvec: |
| 1624 | MHI_VERB("Exit\n"); |
| 1625 | |
| 1626 | return IRQ_HANDLED; |
| 1627 | } |
| 1628 | |
| 1629 | irqreturn_t mhi_intvec_handlr(int irq_number, void *dev) |
| 1630 | { |
| 1631 | |
| 1632 | struct mhi_controller *mhi_cntrl = dev; |
| 1633 | |
| 1634 | /* wake up any events waiting for state change */ |
| 1635 | MHI_VERB("Enter\n"); |
| 1636 | wake_up_all(&mhi_cntrl->state_event); |
| 1637 | MHI_VERB("Exit\n"); |
| 1638 | |
| 1639 | schedule_work(&mhi_cntrl->low_priority_worker); |
| 1640 | |
| 1641 | return IRQ_WAKE_THREAD; |
| 1642 | } |
| 1643 | |
| 1644 | int mhi_send_cmd(struct mhi_controller *mhi_cntrl, |
| 1645 | struct mhi_chan *mhi_chan, |
| 1646 | enum MHI_CMD cmd) |
| 1647 | { |
| 1648 | struct mhi_tre *cmd_tre = NULL; |
| 1649 | struct mhi_cmd *mhi_cmd = &mhi_cntrl->mhi_cmd[PRIMARY_CMD_RING]; |
| 1650 | struct mhi_ring *ring = &mhi_cmd->ring; |
| 1651 | int chan = 0; |
| 1652 | |
| 1653 | MHI_VERB("Entered, MHI pm_state:%s dev_state:%s ee:%s\n", |
| 1654 | to_mhi_pm_state_str(mhi_cntrl->pm_state), |
| 1655 | TO_MHI_STATE_STR(mhi_cntrl->dev_state), |
| 1656 | TO_MHI_EXEC_STR(mhi_cntrl->ee)); |
| 1657 | |
| 1658 | if (mhi_chan) |
| 1659 | chan = mhi_chan->chan; |
| 1660 | |
| 1661 | spin_lock_bh(&mhi_cmd->lock); |
| 1662 | if (!get_nr_avail_ring_elements(mhi_cntrl, ring)) { |
| 1663 | spin_unlock_bh(&mhi_cmd->lock); |
| 1664 | return -ENOMEM; |
| 1665 | } |
| 1666 | |
| 1667 | /* prepare the cmd tre */ |
| 1668 | cmd_tre = ring->wp; |
| 1669 | switch (cmd) { |
| 1670 | case MHI_CMD_RESET_CHAN: |
| 1671 | cmd_tre->ptr = MHI_TRE_CMD_RESET_PTR; |
| 1672 | cmd_tre->dword[0] = MHI_TRE_CMD_RESET_DWORD0; |
| 1673 | cmd_tre->dword[1] = MHI_TRE_CMD_RESET_DWORD1(chan); |
| 1674 | break; |
| 1675 | case MHI_CMD_START_CHAN: |
| 1676 | cmd_tre->ptr = MHI_TRE_CMD_START_PTR; |
| 1677 | cmd_tre->dword[0] = MHI_TRE_CMD_START_DWORD0; |
| 1678 | cmd_tre->dword[1] = MHI_TRE_CMD_START_DWORD1(chan); |
| 1679 | break; |
| 1680 | case MHI_CMD_TIMSYNC_CFG: |
| 1681 | cmd_tre->ptr = MHI_TRE_CMD_TSYNC_CFG_PTR; |
| 1682 | cmd_tre->dword[0] = MHI_TRE_CMD_TSYNC_CFG_DWORD0; |
| 1683 | cmd_tre->dword[1] = MHI_TRE_CMD_TSYNC_CFG_DWORD1 |
| 1684 | (mhi_cntrl->mhi_tsync->er_index); |
| 1685 | break; |
| 1686 | } |
| 1687 | |
| 1688 | |
| 1689 | MHI_VERB("WP:0x%llx TRE: 0x%llx 0x%08x 0x%08x\n", |
| 1690 | (u64)mhi_to_physical(ring, cmd_tre), cmd_tre->ptr, |
| 1691 | cmd_tre->dword[0], cmd_tre->dword[1]); |
| 1692 | |
| 1693 | /* queue to hardware */ |
| 1694 | mhi_add_ring_element(mhi_cntrl, ring); |
| 1695 | read_lock_bh(&mhi_cntrl->pm_lock); |
| 1696 | if (likely(MHI_DB_ACCESS_VALID(mhi_cntrl))) |
| 1697 | mhi_ring_cmd_db(mhi_cntrl, mhi_cmd); |
| 1698 | read_unlock_bh(&mhi_cntrl->pm_lock); |
| 1699 | spin_unlock_bh(&mhi_cmd->lock); |
| 1700 | |
| 1701 | return 0; |
| 1702 | } |
| 1703 | |
| 1704 | int mhi_prepare_channel(struct mhi_controller *mhi_cntrl, |
| 1705 | struct mhi_chan *mhi_chan) |
| 1706 | { |
| 1707 | int ret = 0; |
| 1708 | |
| 1709 | MHI_LOG("Entered: preparing channel:%d\n", mhi_chan->chan); |
| 1710 | |
| 1711 | if (!(BIT(mhi_cntrl->ee) & mhi_chan->ee_mask)) { |
| 1712 | MHI_ERR("Current EE:%s Required EE Mask:0x%x for chan:%s\n", |
| 1713 | TO_MHI_EXEC_STR(mhi_cntrl->ee), mhi_chan->ee_mask, |
| 1714 | mhi_chan->name); |
| 1715 | return -ENOTCONN; |
| 1716 | } |
| 1717 | |
| 1718 | mutex_lock(&mhi_chan->mutex); |
| 1719 | |
| 1720 | /* if channel is not disable state do not allow to start */ |
| 1721 | if (mhi_chan->ch_state != MHI_CH_STATE_DISABLED) { |
| 1722 | ret = -EIO; |
| 1723 | MHI_LOG("channel:%d is not in disabled state, ch_state%d\n", |
| 1724 | mhi_chan->chan, mhi_chan->ch_state); |
| 1725 | goto error_init_chan; |
| 1726 | } |
| 1727 | |
| 1728 | /* client manages channel context for offload channels */ |
| 1729 | if (!mhi_chan->offload_ch) { |
| 1730 | ret = mhi_init_chan_ctxt(mhi_cntrl, mhi_chan); |
| 1731 | if (ret) { |
| 1732 | MHI_ERR("Error with init chan\n"); |
| 1733 | goto error_init_chan; |
| 1734 | } |
| 1735 | } |
| 1736 | |
| 1737 | reinit_completion(&mhi_chan->completion); |
| 1738 | read_lock_bh(&mhi_cntrl->pm_lock); |
| 1739 | if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) { |
| 1740 | MHI_ERR("MHI host is not in active state\n"); |
| 1741 | read_unlock_bh(&mhi_cntrl->pm_lock); |
| 1742 | ret = -EIO; |
| 1743 | goto error_pm_state; |
| 1744 | } |
| 1745 | |
| 1746 | mhi_cntrl->wake_toggle(mhi_cntrl); |
| 1747 | read_unlock_bh(&mhi_cntrl->pm_lock); |
| 1748 | mhi_cntrl->runtime_get(mhi_cntrl, mhi_cntrl->priv_data); |
| 1749 | mhi_cntrl->runtime_put(mhi_cntrl, mhi_cntrl->priv_data); |
| 1750 | |
| 1751 | ret = mhi_send_cmd(mhi_cntrl, mhi_chan, MHI_CMD_START_CHAN); |
| 1752 | if (ret) { |
| 1753 | MHI_ERR("Failed to send start chan cmd\n"); |
| 1754 | goto error_pm_state; |
| 1755 | } |
| 1756 | |
| 1757 | ret = wait_for_completion_timeout(&mhi_chan->completion, |
| 1758 | msecs_to_jiffies(mhi_cntrl->timeout_ms)); |
| 1759 | if (!ret || mhi_chan->ccs != MHI_EV_CC_SUCCESS) { |
| 1760 | MHI_ERR("Failed to receive cmd completion for chan:%d\n", |
| 1761 | mhi_chan->chan); |
| 1762 | ret = -EIO; |
| 1763 | goto error_pm_state; |
| 1764 | } |
| 1765 | |
| 1766 | write_lock_irq(&mhi_chan->lock); |
| 1767 | mhi_chan->ch_state = MHI_CH_STATE_ENABLED; |
| 1768 | write_unlock_irq(&mhi_chan->lock); |
| 1769 | |
| 1770 | /* pre allocate buffer for xfer ring */ |
| 1771 | if (mhi_chan->pre_alloc) { |
| 1772 | int nr_el = get_nr_avail_ring_elements(mhi_cntrl, |
| 1773 | &mhi_chan->tre_ring); |
| 1774 | size_t len = mhi_cntrl->buffer_len; |
| 1775 | |
| 1776 | while (nr_el--) { |
| 1777 | void *buf; |
| 1778 | |
| 1779 | buf = kmalloc(len, GFP_KERNEL); |
| 1780 | if (!buf) { |
| 1781 | ret = -ENOMEM; |
| 1782 | goto error_pre_alloc; |
| 1783 | } |
| 1784 | |
| 1785 | /* prepare transfer descriptors */ |
| 1786 | ret = mhi_chan->gen_tre(mhi_cntrl, mhi_chan, buf, buf, |
| 1787 | len, MHI_EOT); |
| 1788 | if (ret) { |
| 1789 | MHI_ERR("Chan:%d error prepare buffer\n", |
| 1790 | mhi_chan->chan); |
| 1791 | kfree(buf); |
| 1792 | goto error_pre_alloc; |
| 1793 | } |
| 1794 | } |
| 1795 | |
| 1796 | read_lock_bh(&mhi_cntrl->pm_lock); |
| 1797 | if (MHI_DB_ACCESS_VALID(mhi_cntrl)) { |
| 1798 | read_lock_irq(&mhi_chan->lock); |
| 1799 | mhi_ring_chan_db(mhi_cntrl, mhi_chan); |
| 1800 | read_unlock_irq(&mhi_chan->lock); |
| 1801 | } |
| 1802 | read_unlock_bh(&mhi_cntrl->pm_lock); |
| 1803 | } |
| 1804 | |
| 1805 | mutex_unlock(&mhi_chan->mutex); |
| 1806 | |
| 1807 | MHI_LOG("Chan:%d successfully moved to start state\n", mhi_chan->chan); |
| 1808 | |
| 1809 | return 0; |
| 1810 | |
| 1811 | error_pm_state: |
| 1812 | if (!mhi_chan->offload_ch) |
| 1813 | mhi_deinit_chan_ctxt(mhi_cntrl, mhi_chan); |
| 1814 | |
| 1815 | error_init_chan: |
| 1816 | mutex_unlock(&mhi_chan->mutex); |
| 1817 | |
| 1818 | return ret; |
| 1819 | |
| 1820 | error_pre_alloc: |
| 1821 | mutex_unlock(&mhi_chan->mutex); |
| 1822 | __mhi_unprepare_channel(mhi_cntrl, mhi_chan); |
| 1823 | |
| 1824 | return ret; |
| 1825 | } |
| 1826 | |
| 1827 | static void mhi_mark_stale_events(struct mhi_controller *mhi_cntrl, |
| 1828 | struct mhi_event *mhi_event, |
| 1829 | struct mhi_event_ctxt *er_ctxt, |
| 1830 | int chan) |
| 1831 | { |
| 1832 | struct mhi_tre *dev_rp, *local_rp; |
| 1833 | struct mhi_ring *ev_ring; |
| 1834 | unsigned long flags; |
| 1835 | |
| 1836 | MHI_LOG("Marking all events for chan:%d as stale\n", chan); |
| 1837 | |
| 1838 | ev_ring = &mhi_event->ring; |
| 1839 | |
| 1840 | /* mark all stale events related to channel as STALE event */ |
| 1841 | spin_lock_irqsave(&mhi_event->lock, flags); |
| 1842 | dev_rp = mhi_to_virtual(ev_ring, er_ctxt->rp); |
| 1843 | |
| 1844 | local_rp = ev_ring->rp; |
| 1845 | while (dev_rp != local_rp) { |
| 1846 | if (MHI_TRE_GET_EV_TYPE(local_rp) == |
| 1847 | MHI_PKT_TYPE_TX_EVENT && |
| 1848 | chan == MHI_TRE_GET_EV_CHID(local_rp)) |
| 1849 | local_rp->dword[1] = MHI_TRE_EV_DWORD1(chan, |
| 1850 | MHI_PKT_TYPE_STALE_EVENT); |
| 1851 | local_rp++; |
| 1852 | if (local_rp == (ev_ring->base + ev_ring->len)) |
| 1853 | local_rp = ev_ring->base; |
| 1854 | } |
| 1855 | |
| 1856 | |
| 1857 | MHI_LOG("Finished marking events as stale events\n"); |
| 1858 | spin_unlock_irqrestore(&mhi_event->lock, flags); |
| 1859 | } |
| 1860 | |
| 1861 | static void mhi_reset_data_chan(struct mhi_controller *mhi_cntrl, |
| 1862 | struct mhi_chan *mhi_chan) |
| 1863 | { |
| 1864 | struct mhi_ring *buf_ring, *tre_ring; |
| 1865 | struct mhi_result result; |
| 1866 | |
| 1867 | /* reset any pending buffers */ |
| 1868 | buf_ring = &mhi_chan->buf_ring; |
| 1869 | tre_ring = &mhi_chan->tre_ring; |
| 1870 | result.transaction_status = -ENOTCONN; |
| 1871 | result.bytes_xferd = 0; |
| 1872 | while (tre_ring->rp != tre_ring->wp) { |
| 1873 | struct mhi_buf_info *buf_info = buf_ring->rp; |
| 1874 | |
| 1875 | if (mhi_chan->dir == DMA_TO_DEVICE) |
| 1876 | atomic_dec(&mhi_cntrl->pending_pkts); |
| 1877 | |
| 1878 | if (!buf_info->pre_mapped) |
| 1879 | mhi_cntrl->unmap_single(mhi_cntrl, buf_info); |
| 1880 | mhi_del_ring_element(mhi_cntrl, buf_ring); |
| 1881 | mhi_del_ring_element(mhi_cntrl, tre_ring); |
| 1882 | |
| 1883 | if (mhi_chan->pre_alloc) { |
| 1884 | kfree(buf_info->cb_buf); |
| 1885 | } else { |
| 1886 | result.buf_addr = buf_info->cb_buf; |
| 1887 | mhi_chan->xfer_cb(mhi_chan->mhi_dev, &result); |
| 1888 | } |
| 1889 | } |
| 1890 | } |
| 1891 | |
| 1892 | static void mhi_reset_rsc_chan(struct mhi_controller *mhi_cntrl, |
| 1893 | struct mhi_chan *mhi_chan) |
| 1894 | { |
| 1895 | struct mhi_ring *buf_ring, *tre_ring; |
| 1896 | struct mhi_result result; |
| 1897 | struct mhi_buf_info *buf_info; |
| 1898 | |
| 1899 | /* reset any pending buffers */ |
| 1900 | buf_ring = &mhi_chan->buf_ring; |
| 1901 | tre_ring = &mhi_chan->tre_ring; |
| 1902 | result.transaction_status = -ENOTCONN; |
| 1903 | result.bytes_xferd = 0; |
| 1904 | |
| 1905 | buf_info = buf_ring->base; |
| 1906 | for (; (void *)buf_info < buf_ring->base + buf_ring->len; buf_info++) { |
| 1907 | if (!buf_info->used) |
| 1908 | continue; |
| 1909 | |
| 1910 | result.buf_addr = buf_info->cb_buf; |
| 1911 | mhi_chan->xfer_cb(mhi_chan->mhi_dev, &result); |
| 1912 | buf_info->used = false; |
| 1913 | } |
| 1914 | } |
| 1915 | |
| 1916 | void mhi_reset_chan(struct mhi_controller *mhi_cntrl, struct mhi_chan *mhi_chan) |
| 1917 | { |
| 1918 | |
| 1919 | struct mhi_event *mhi_event; |
| 1920 | struct mhi_event_ctxt *er_ctxt; |
| 1921 | int chan = mhi_chan->chan; |
| 1922 | |
| 1923 | /* nothing to reset, client don't queue buffers */ |
| 1924 | if (mhi_chan->offload_ch) |
| 1925 | return; |
| 1926 | |
| 1927 | read_lock_bh(&mhi_cntrl->pm_lock); |
| 1928 | mhi_event = &mhi_cntrl->mhi_event[mhi_chan->er_index]; |
| 1929 | er_ctxt = &mhi_cntrl->mhi_ctxt->er_ctxt[mhi_chan->er_index]; |
| 1930 | |
| 1931 | mhi_mark_stale_events(mhi_cntrl, mhi_event, er_ctxt, chan); |
| 1932 | |
| 1933 | if (mhi_chan->xfer_type == MHI_XFER_RSC_DMA) |
| 1934 | mhi_reset_rsc_chan(mhi_cntrl, mhi_chan); |
| 1935 | else |
| 1936 | mhi_reset_data_chan(mhi_cntrl, mhi_chan); |
| 1937 | |
| 1938 | read_unlock_bh(&mhi_cntrl->pm_lock); |
| 1939 | MHI_LOG("Reset complete.\n"); |
| 1940 | } |
| 1941 | |
| 1942 | static void __mhi_unprepare_channel(struct mhi_controller *mhi_cntrl, |
| 1943 | struct mhi_chan *mhi_chan) |
| 1944 | { |
| 1945 | int ret; |
| 1946 | |
| 1947 | MHI_LOG("Entered: unprepare channel:%d\n", mhi_chan->chan); |
| 1948 | |
| 1949 | /* no more processing events for this channel */ |
| 1950 | mutex_lock(&mhi_chan->mutex); |
| 1951 | write_lock_irq(&mhi_chan->lock); |
| 1952 | if (mhi_chan->ch_state != MHI_CH_STATE_ENABLED) { |
| 1953 | MHI_LOG("chan:%d is already disabled\n", mhi_chan->chan); |
| 1954 | write_unlock_irq(&mhi_chan->lock); |
| 1955 | mutex_unlock(&mhi_chan->mutex); |
| 1956 | return; |
| 1957 | } |
| 1958 | |
| 1959 | mhi_chan->ch_state = MHI_CH_STATE_DISABLED; |
| 1960 | write_unlock_irq(&mhi_chan->lock); |
| 1961 | |
| 1962 | reinit_completion(&mhi_chan->completion); |
| 1963 | read_lock_bh(&mhi_cntrl->pm_lock); |
| 1964 | if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) { |
| 1965 | read_unlock_bh(&mhi_cntrl->pm_lock); |
| 1966 | goto error_invalid_state; |
| 1967 | } |
| 1968 | |
| 1969 | mhi_cntrl->wake_toggle(mhi_cntrl); |
| 1970 | read_unlock_bh(&mhi_cntrl->pm_lock); |
| 1971 | |
| 1972 | mhi_cntrl->runtime_get(mhi_cntrl, mhi_cntrl->priv_data); |
| 1973 | mhi_cntrl->runtime_put(mhi_cntrl, mhi_cntrl->priv_data); |
| 1974 | ret = mhi_send_cmd(mhi_cntrl, mhi_chan, MHI_CMD_RESET_CHAN); |
| 1975 | if (ret) { |
| 1976 | MHI_ERR("Failed to send reset chan cmd\n"); |
| 1977 | goto error_invalid_state; |
| 1978 | } |
| 1979 | |
| 1980 | /* even if it fails we will still reset */ |
| 1981 | ret = wait_for_completion_timeout(&mhi_chan->completion, |
| 1982 | msecs_to_jiffies(mhi_cntrl->timeout_ms)); |
| 1983 | if (!ret || mhi_chan->ccs != MHI_EV_CC_SUCCESS) |
| 1984 | MHI_ERR("Failed to receive cmd completion, still resetting\n"); |
| 1985 | |
| 1986 | error_invalid_state: |
| 1987 | if (!mhi_chan->offload_ch) { |
| 1988 | mhi_reset_chan(mhi_cntrl, mhi_chan); |
| 1989 | mhi_deinit_chan_ctxt(mhi_cntrl, mhi_chan); |
| 1990 | } |
| 1991 | MHI_LOG("chan:%d successfully resetted\n", mhi_chan->chan); |
| 1992 | mutex_unlock(&mhi_chan->mutex); |
| 1993 | } |
| 1994 | |
| 1995 | int mhi_debugfs_mhi_states_show(struct seq_file *m, void *d) |
| 1996 | { |
| 1997 | struct mhi_controller *mhi_cntrl = m->private; |
| 1998 | |
| 1999 | seq_printf(m, |
| 2000 | "pm_state:%s dev_state:%s EE:%s M0:%u M2:%u M3:%u M3_Fast:%u wake:%d dev_wake:%u alloc_size:%u pending_pkts:%u\n", |
| 2001 | to_mhi_pm_state_str(mhi_cntrl->pm_state), |
| 2002 | TO_MHI_STATE_STR(mhi_cntrl->dev_state), |
| 2003 | TO_MHI_EXEC_STR(mhi_cntrl->ee), |
| 2004 | mhi_cntrl->M0, mhi_cntrl->M2, mhi_cntrl->M3, |
| 2005 | mhi_cntrl->M3_FAST, mhi_cntrl->wake_set, |
| 2006 | atomic_read(&mhi_cntrl->dev_wake), |
| 2007 | atomic_read(&mhi_cntrl->alloc_size), |
| 2008 | atomic_read(&mhi_cntrl->pending_pkts)); |
| 2009 | return 0; |
| 2010 | } |
| 2011 | |
| 2012 | int mhi_debugfs_mhi_event_show(struct seq_file *m, void *d) |
| 2013 | { |
| 2014 | struct mhi_controller *mhi_cntrl = m->private; |
| 2015 | struct mhi_event *mhi_event; |
| 2016 | struct mhi_event_ctxt *er_ctxt; |
| 2017 | |
| 2018 | int i; |
| 2019 | |
| 2020 | er_ctxt = mhi_cntrl->mhi_ctxt->er_ctxt; |
| 2021 | mhi_event = mhi_cntrl->mhi_event; |
| 2022 | for (i = 0; i < mhi_cntrl->total_ev_rings; i++, er_ctxt++, |
| 2023 | mhi_event++) { |
| 2024 | struct mhi_ring *ring = &mhi_event->ring; |
| 2025 | |
| 2026 | if (mhi_event->offload_ev) { |
| 2027 | seq_printf(m, "Index:%d offload event ring\n", i); |
| 2028 | } else { |
| 2029 | seq_printf(m, |
| 2030 | "Index:%d modc:%d modt:%d base:0x%0llx len:0x%llx", |
| 2031 | i, er_ctxt->intmodc, er_ctxt->intmodt, |
| 2032 | er_ctxt->rbase, er_ctxt->rlen); |
| 2033 | seq_printf(m, |
| 2034 | " rp:0x%llx wp:0x%llx local_rp:0x%llx db:0x%llx\n", |
| 2035 | er_ctxt->rp, er_ctxt->wp, |
Nitesh Gupta | f2b595d | 2019-10-31 11:22:01 +0530 | [diff] [blame] | 2036 | (u64)mhi_to_physical(ring, ring->rp), |
| 2037 | (u64)mhi_event->db_cfg.db_val); |
Nitesh Gupta | 35b8ea6 | 2019-10-31 10:45:54 +0530 | [diff] [blame] | 2038 | } |
| 2039 | } |
| 2040 | |
| 2041 | return 0; |
| 2042 | } |
| 2043 | |
| 2044 | int mhi_debugfs_mhi_chan_show(struct seq_file *m, void *d) |
| 2045 | { |
| 2046 | struct mhi_controller *mhi_cntrl = m->private; |
| 2047 | struct mhi_chan *mhi_chan; |
| 2048 | struct mhi_chan_ctxt *chan_ctxt; |
| 2049 | int i; |
| 2050 | |
| 2051 | mhi_chan = mhi_cntrl->mhi_chan; |
| 2052 | chan_ctxt = mhi_cntrl->mhi_ctxt->chan_ctxt; |
| 2053 | for (i = 0; i < mhi_cntrl->max_chan; i++, chan_ctxt++, mhi_chan++) { |
| 2054 | struct mhi_ring *ring = &mhi_chan->tre_ring; |
| 2055 | |
| 2056 | if (mhi_chan->offload_ch) { |
| 2057 | seq_printf(m, "%s(%u) offload channel\n", |
| 2058 | mhi_chan->name, mhi_chan->chan); |
| 2059 | } else if (mhi_chan->mhi_dev) { |
| 2060 | seq_printf(m, |
| 2061 | "%s(%u) state:0x%x brstmode:0x%x pllcfg:0x%x type:0x%x erindex:%u", |
| 2062 | mhi_chan->name, mhi_chan->chan, |
| 2063 | chan_ctxt->chstate, chan_ctxt->brstmode, |
| 2064 | chan_ctxt->pollcfg, chan_ctxt->chtype, |
| 2065 | chan_ctxt->erindex); |
| 2066 | seq_printf(m, |
| 2067 | " base:0x%llx len:0x%llx wp:0x%llx local_rp:0x%llx local_wp:0x%llx db:0x%llx\n", |
| 2068 | chan_ctxt->rbase, chan_ctxt->rlen, |
| 2069 | chan_ctxt->wp, |
Nitesh Gupta | f2b595d | 2019-10-31 11:22:01 +0530 | [diff] [blame] | 2070 | (u64)mhi_to_physical(ring, ring->rp), |
| 2071 | (u64)mhi_to_physical(ring, ring->wp), |
| 2072 | (u64)mhi_chan->db_cfg.db_val); |
Nitesh Gupta | 35b8ea6 | 2019-10-31 10:45:54 +0530 | [diff] [blame] | 2073 | } |
| 2074 | } |
| 2075 | |
| 2076 | return 0; |
| 2077 | } |
| 2078 | |
| 2079 | /* move channel to start state */ |
| 2080 | int mhi_prepare_for_transfer(struct mhi_device *mhi_dev) |
| 2081 | { |
| 2082 | int ret, dir; |
| 2083 | struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; |
| 2084 | struct mhi_chan *mhi_chan; |
| 2085 | |
| 2086 | for (dir = 0; dir < 2; dir++) { |
| 2087 | mhi_chan = dir ? mhi_dev->dl_chan : mhi_dev->ul_chan; |
| 2088 | |
| 2089 | if (!mhi_chan) |
| 2090 | continue; |
| 2091 | |
| 2092 | ret = mhi_prepare_channel(mhi_cntrl, mhi_chan); |
| 2093 | if (ret) { |
| 2094 | MHI_ERR("Error moving chan %s,%d to START state\n", |
| 2095 | mhi_chan->name, mhi_chan->chan); |
| 2096 | goto error_open_chan; |
| 2097 | } |
| 2098 | } |
| 2099 | |
| 2100 | return 0; |
| 2101 | |
| 2102 | error_open_chan: |
| 2103 | for (--dir; dir >= 0; dir--) { |
| 2104 | mhi_chan = dir ? mhi_dev->dl_chan : mhi_dev->ul_chan; |
| 2105 | |
| 2106 | if (!mhi_chan) |
| 2107 | continue; |
| 2108 | |
| 2109 | __mhi_unprepare_channel(mhi_cntrl, mhi_chan); |
| 2110 | } |
| 2111 | |
| 2112 | return ret; |
| 2113 | } |
| 2114 | EXPORT_SYMBOL(mhi_prepare_for_transfer); |
| 2115 | |
| 2116 | void mhi_unprepare_from_transfer(struct mhi_device *mhi_dev) |
| 2117 | { |
| 2118 | struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; |
| 2119 | struct mhi_chan *mhi_chan; |
| 2120 | int dir; |
| 2121 | |
| 2122 | for (dir = 0; dir < 2; dir++) { |
| 2123 | mhi_chan = dir ? mhi_dev->ul_chan : mhi_dev->dl_chan; |
| 2124 | |
| 2125 | if (!mhi_chan) |
| 2126 | continue; |
| 2127 | |
| 2128 | __mhi_unprepare_channel(mhi_cntrl, mhi_chan); |
| 2129 | } |
| 2130 | } |
| 2131 | EXPORT_SYMBOL(mhi_unprepare_from_transfer); |
| 2132 | |
| 2133 | int mhi_get_no_free_descriptors(struct mhi_device *mhi_dev, |
| 2134 | enum dma_data_direction dir) |
| 2135 | { |
| 2136 | struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; |
| 2137 | struct mhi_chan *mhi_chan = (dir == DMA_TO_DEVICE) ? |
| 2138 | mhi_dev->ul_chan : mhi_dev->dl_chan; |
| 2139 | struct mhi_ring *tre_ring = &mhi_chan->tre_ring; |
| 2140 | |
| 2141 | return get_nr_avail_ring_elements(mhi_cntrl, tre_ring); |
| 2142 | } |
| 2143 | EXPORT_SYMBOL(mhi_get_no_free_descriptors); |
| 2144 | |
| 2145 | static int __mhi_bdf_to_controller(struct device *dev, void *tmp) |
| 2146 | { |
| 2147 | struct mhi_device *mhi_dev = to_mhi_device(dev); |
| 2148 | struct mhi_device *match = tmp; |
| 2149 | |
| 2150 | /* return any none-zero value if match */ |
| 2151 | if (mhi_dev->dev_type == MHI_CONTROLLER_TYPE && |
| 2152 | mhi_dev->domain == match->domain && mhi_dev->bus == match->bus && |
| 2153 | mhi_dev->slot == match->slot && mhi_dev->dev_id == match->dev_id) |
| 2154 | return 1; |
| 2155 | |
| 2156 | return 0; |
| 2157 | } |
| 2158 | |
| 2159 | struct mhi_controller *mhi_bdf_to_controller(u32 domain, |
| 2160 | u32 bus, |
| 2161 | u32 slot, |
| 2162 | u32 dev_id) |
| 2163 | { |
| 2164 | struct mhi_device tmp, *mhi_dev; |
| 2165 | struct device *dev; |
| 2166 | |
| 2167 | tmp.domain = domain; |
| 2168 | tmp.bus = bus; |
| 2169 | tmp.slot = slot; |
| 2170 | tmp.dev_id = dev_id; |
| 2171 | |
| 2172 | dev = bus_find_device(&mhi_bus_type, NULL, &tmp, |
| 2173 | __mhi_bdf_to_controller); |
| 2174 | if (!dev) |
| 2175 | return NULL; |
| 2176 | |
| 2177 | mhi_dev = to_mhi_device(dev); |
| 2178 | |
| 2179 | return mhi_dev->mhi_cntrl; |
| 2180 | } |
| 2181 | EXPORT_SYMBOL(mhi_bdf_to_controller); |
| 2182 | |
| 2183 | int mhi_poll(struct mhi_device *mhi_dev, |
| 2184 | u32 budget) |
| 2185 | { |
| 2186 | struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; |
| 2187 | struct mhi_chan *mhi_chan = mhi_dev->dl_chan; |
| 2188 | struct mhi_event *mhi_event = &mhi_cntrl->mhi_event[mhi_chan->er_index]; |
| 2189 | int ret; |
| 2190 | |
| 2191 | spin_lock_bh(&mhi_event->lock); |
| 2192 | ret = mhi_event->process_event(mhi_cntrl, mhi_event, budget); |
| 2193 | spin_unlock_bh(&mhi_event->lock); |
| 2194 | |
| 2195 | return ret; |
| 2196 | } |
| 2197 | EXPORT_SYMBOL(mhi_poll); |
| 2198 | |
| 2199 | int mhi_get_remote_time_sync(struct mhi_device *mhi_dev, |
| 2200 | u64 *t_host, |
| 2201 | u64 *t_dev) |
| 2202 | { |
| 2203 | struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; |
| 2204 | struct mhi_timesync *mhi_tsync = mhi_cntrl->mhi_tsync; |
| 2205 | int ret; |
| 2206 | |
| 2207 | /* not all devices support time feature */ |
| 2208 | if (!mhi_tsync) |
| 2209 | return -EIO; |
| 2210 | |
| 2211 | /* bring to M0 state */ |
| 2212 | ret = __mhi_device_get_sync(mhi_cntrl); |
| 2213 | if (ret) |
| 2214 | return ret; |
| 2215 | |
| 2216 | mutex_lock(&mhi_tsync->lpm_mutex); |
| 2217 | |
| 2218 | read_lock_bh(&mhi_cntrl->pm_lock); |
| 2219 | if (unlikely(MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state))) { |
| 2220 | MHI_ERR("MHI is not in active state, pm_state:%s\n", |
| 2221 | to_mhi_pm_state_str(mhi_cntrl->pm_state)); |
| 2222 | ret = -EIO; |
| 2223 | goto error_invalid_state; |
| 2224 | } |
| 2225 | |
| 2226 | /* disable link level low power modes */ |
| 2227 | ret = mhi_cntrl->lpm_disable(mhi_cntrl, mhi_cntrl->priv_data); |
| 2228 | if (ret) |
| 2229 | goto error_invalid_state; |
| 2230 | |
| 2231 | /* |
| 2232 | * time critical code to fetch device times, |
| 2233 | * delay between these two steps should be |
| 2234 | * deterministic as possible. |
| 2235 | */ |
| 2236 | preempt_disable(); |
| 2237 | local_irq_disable(); |
| 2238 | |
| 2239 | *t_host = mhi_cntrl->time_get(mhi_cntrl, mhi_cntrl->priv_data); |
| 2240 | *t_dev = readq_relaxed_no_log(mhi_tsync->time_reg); |
| 2241 | |
| 2242 | local_irq_enable(); |
| 2243 | preempt_enable(); |
| 2244 | |
| 2245 | mhi_cntrl->lpm_enable(mhi_cntrl, mhi_cntrl->priv_data); |
| 2246 | |
| 2247 | error_invalid_state: |
| 2248 | mhi_cntrl->wake_put(mhi_cntrl, false); |
| 2249 | read_unlock_bh(&mhi_cntrl->pm_lock); |
| 2250 | mutex_unlock(&mhi_tsync->lpm_mutex); |
| 2251 | |
| 2252 | return ret; |
| 2253 | } |
| 2254 | EXPORT_SYMBOL(mhi_get_remote_time_sync); |
| 2255 | |
| 2256 | /** |
| 2257 | * mhi_get_remote_time - Get external modem time relative to host time |
| 2258 | * Trigger event to capture modem time, also capture host time so client |
| 2259 | * can do a relative drift comparision. |
| 2260 | * Recommended only tsync device calls this method and do not call this |
| 2261 | * from atomic context |
| 2262 | * @mhi_dev: Device associated with the channels |
| 2263 | * @sequence:unique sequence id track event |
| 2264 | * @cb_func: callback function to call back |
| 2265 | */ |
| 2266 | int mhi_get_remote_time(struct mhi_device *mhi_dev, |
| 2267 | u32 sequence, |
| 2268 | void (*cb_func)(struct mhi_device *mhi_dev, |
| 2269 | u32 sequence, |
| 2270 | u64 local_time, |
| 2271 | u64 remote_time)) |
| 2272 | { |
| 2273 | struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; |
| 2274 | struct mhi_timesync *mhi_tsync = mhi_cntrl->mhi_tsync; |
| 2275 | struct tsync_node *tsync_node; |
| 2276 | int ret; |
| 2277 | |
| 2278 | /* not all devices support time feature */ |
| 2279 | if (!mhi_tsync) |
| 2280 | return -EIO; |
| 2281 | |
| 2282 | /* tsync db can only be rung in M0 state */ |
| 2283 | ret = __mhi_device_get_sync(mhi_cntrl); |
| 2284 | if (ret) |
| 2285 | return ret; |
| 2286 | |
| 2287 | /* |
| 2288 | * technically we can use GFP_KERNEL, but wants to avoid |
| 2289 | * # of times scheduling out |
| 2290 | */ |
| 2291 | tsync_node = kzalloc(sizeof(*tsync_node), GFP_ATOMIC); |
| 2292 | if (!tsync_node) { |
| 2293 | ret = -ENOMEM; |
| 2294 | goto error_no_mem; |
| 2295 | } |
| 2296 | |
| 2297 | tsync_node->sequence = sequence; |
| 2298 | tsync_node->cb_func = cb_func; |
| 2299 | tsync_node->mhi_dev = mhi_dev; |
| 2300 | |
| 2301 | /* disable link level low power modes */ |
| 2302 | mhi_cntrl->lpm_disable(mhi_cntrl, mhi_cntrl->priv_data); |
| 2303 | |
| 2304 | read_lock_bh(&mhi_cntrl->pm_lock); |
| 2305 | if (unlikely(MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state))) { |
| 2306 | MHI_ERR("MHI is not in active state, pm_state:%s\n", |
| 2307 | to_mhi_pm_state_str(mhi_cntrl->pm_state)); |
| 2308 | ret = -EIO; |
| 2309 | goto error_invalid_state; |
| 2310 | } |
| 2311 | |
| 2312 | spin_lock_irq(&mhi_tsync->lock); |
| 2313 | list_add_tail(&tsync_node->node, &mhi_tsync->head); |
| 2314 | spin_unlock_irq(&mhi_tsync->lock); |
| 2315 | |
| 2316 | /* |
| 2317 | * time critical code, delay between these two steps should be |
| 2318 | * deterministic as possible. |
| 2319 | */ |
| 2320 | preempt_disable(); |
| 2321 | local_irq_disable(); |
| 2322 | |
| 2323 | tsync_node->local_time = |
| 2324 | mhi_cntrl->time_get(mhi_cntrl, mhi_cntrl->priv_data); |
| 2325 | writel_relaxed_no_log(tsync_node->sequence, mhi_tsync->db); |
| 2326 | /* write must go thru immediately */ |
| 2327 | wmb(); |
| 2328 | |
| 2329 | local_irq_enable(); |
| 2330 | preempt_enable(); |
| 2331 | |
| 2332 | ret = 0; |
| 2333 | |
| 2334 | error_invalid_state: |
| 2335 | if (ret) |
| 2336 | kfree(tsync_node); |
| 2337 | read_unlock_bh(&mhi_cntrl->pm_lock); |
| 2338 | mhi_cntrl->lpm_enable(mhi_cntrl, mhi_cntrl->priv_data); |
| 2339 | |
| 2340 | error_no_mem: |
| 2341 | read_lock_bh(&mhi_cntrl->pm_lock); |
| 2342 | mhi_cntrl->wake_put(mhi_cntrl, false); |
| 2343 | read_unlock_bh(&mhi_cntrl->pm_lock); |
| 2344 | |
| 2345 | return ret; |
| 2346 | } |
| 2347 | EXPORT_SYMBOL(mhi_get_remote_time); |
| 2348 | |
| 2349 | void mhi_debug_reg_dump(struct mhi_controller *mhi_cntrl) |
| 2350 | { |
| 2351 | enum mhi_dev_state state; |
| 2352 | enum mhi_ee ee; |
| 2353 | int i, ret; |
| 2354 | u32 val; |
| 2355 | void __iomem *mhi_base = mhi_cntrl->regs; |
| 2356 | void __iomem *bhi_base = mhi_cntrl->bhi; |
| 2357 | void __iomem *bhie_base = mhi_cntrl->bhie; |
| 2358 | void __iomem *wake_db = mhi_cntrl->wake_db; |
| 2359 | struct { |
| 2360 | const char *name; |
| 2361 | int offset; |
| 2362 | void *base; |
| 2363 | } debug_reg[] = { |
| 2364 | { "MHI_CNTRL", MHICTRL, mhi_base}, |
| 2365 | { "MHI_STATUS", MHISTATUS, mhi_base}, |
| 2366 | { "MHI_WAKE_DB", 0, wake_db}, |
| 2367 | { "BHI_EXECENV", BHI_EXECENV, bhi_base}, |
| 2368 | { "BHI_STATUS", BHI_STATUS, bhi_base}, |
| 2369 | { "BHI_ERRCODE", BHI_ERRCODE, bhi_base}, |
| 2370 | { "BHI_ERRDBG1", BHI_ERRDBG1, bhi_base}, |
| 2371 | { "BHI_ERRDBG2", BHI_ERRDBG2, bhi_base}, |
| 2372 | { "BHI_ERRDBG3", BHI_ERRDBG3, bhi_base}, |
| 2373 | { "BHIE_TXVEC_DB", BHIE_TXVECDB_OFFS, bhie_base}, |
| 2374 | { "BHIE_TXVEC_STATUS", BHIE_TXVECSTATUS_OFFS, bhie_base}, |
| 2375 | { "BHIE_RXVEC_DB", BHIE_RXVECDB_OFFS, bhie_base}, |
| 2376 | { "BHIE_RXVEC_STATUS", BHIE_RXVECSTATUS_OFFS, bhie_base}, |
| 2377 | { NULL }, |
| 2378 | }; |
| 2379 | |
| 2380 | MHI_LOG("host pm_state:%s dev_state:%s ee:%s\n", |
| 2381 | to_mhi_pm_state_str(mhi_cntrl->pm_state), |
| 2382 | TO_MHI_STATE_STR(mhi_cntrl->dev_state), |
| 2383 | TO_MHI_EXEC_STR(mhi_cntrl->ee)); |
| 2384 | |
| 2385 | state = mhi_get_mhi_state(mhi_cntrl); |
| 2386 | ee = mhi_get_exec_env(mhi_cntrl); |
| 2387 | |
| 2388 | MHI_LOG("device ee:%s dev_state:%s\n", TO_MHI_EXEC_STR(ee), |
| 2389 | TO_MHI_STATE_STR(state)); |
| 2390 | |
| 2391 | for (i = 0; debug_reg[i].name; i++) { |
| 2392 | ret = mhi_read_reg(mhi_cntrl, debug_reg[i].base, |
| 2393 | debug_reg[i].offset, &val); |
| 2394 | MHI_LOG("reg:%s val:0x%x, ret:%d\n", debug_reg[i].name, val, |
| 2395 | ret); |
| 2396 | } |
| 2397 | } |
| 2398 | EXPORT_SYMBOL(mhi_debug_reg_dump); |