blob: 64cf57e4bb859d76aacedf5e9bfd61cfd094fd72 [file] [log] [blame]
Michal Simek4e07dba2010-08-12 14:28:53 +02001#include <linux/linkage.h>
2
3/*
4* Unsigned divide operation.
5* Input : Divisor in Reg r5
6* Dividend in Reg r6
7* Output: Result in Reg r3
8*/
9
10 .text
11 .globl __udivsi3
12 .type __udivsi3, @function
13 .ent __udivsi3
14
15__udivsi3:
16
17 .frame r1, 0, r15
18
19 addik r1, r1, -12
20 swi r29, r1, 0
21 swi r30, r1, 4
22 swi r31, r1, 8
23
24 beqi r6, div_by_zero /* div_by_zero /* division error */
25 beqid r5, result_is_zero /* result is zero */
26 addik r30, r0, 0 /* clear mod */
27 addik r29, r0, 32 /* initialize the loop count */
28
29/* check if r6 and r5 are equal - if yes, return 1 */
30 rsub r18, r5, r6
31 beqid r18, return_here
32 addik r3, r0, 1
33
34/* check if (uns)r6 is greater than (uns)r5. in that case, just return 0 */
35 xor r18, r5, r6
36 bgeid r18, 16
37 add r3, r0, r0 /* we would anyways clear r3 */
38 blti r6, return_here /* r6[bit 31 = 1] hence is greater */
39 bri checkr6
40 rsub r18, r6, r5 /* microblazecmp */
41 blti r18, return_here
42
43/* if r6 [bit 31] is set, then return result as 1 */
44checkr6:
45 bgti r6, div0
46 brid return_here
47 addik r3, r0, 1
48
49/* first part try to find the first '1' in the r5 */
50div0:
51 blti r5, div2
52div1:
53 add r5, r5, r5 /* left shift logical r5 */
54 bgtid r5, div1
55 addik r29, r29, -1
56div2:
57/* left shift logical r5 get the '1' into the carry */
58 add r5, r5, r5
59 addc r30, r30, r30 /* move that bit into the mod register */
60 rsub r31, r6, r30 /* try to subtract (r30 a r6) */
61 blti r31, mod_too_small
62/* move the r31 to mod since the result was positive */
63 or r30, r0, r31
64 addik r3, r3, 1
65mod_too_small:
66 addik r29, r29, -1
67 beqi r29, loop_end
68 add r3, r3, r3 /* shift in the '1' into div */
69 bri div2 /* div2 */
70loop_end:
71 bri return_here
72div_by_zero:
73result_is_zero:
74 or r3, r0, r0 /* set result to 0 */
75return_here:
76/* restore values of csrs and that of r3 and the divisor and the dividend */
77 lwi r29, r1, 0
78 lwi r30, r1, 4
79 lwi r31, r1, 8
80 rtsd r15, 8
81 addik r1, r1, 12
82
83.size __udivsi3, . - __udivsi3
84.end __udivsi3