Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2013-2017, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | */ |
| 13 | |
| 14 | #include "adreno.h" |
| 15 | #include "adreno_a4xx.h" |
| 16 | #include "adreno_trace.h" |
| 17 | #include "adreno_pm4types.h" |
| 18 | |
| 19 | #define ADRENO_RB_PREEMPT_TOKEN_DWORDS 125 |
| 20 | |
| 21 | static void a4xx_preemption_timer(unsigned long data) |
| 22 | { |
| 23 | struct adreno_device *adreno_dev = (struct adreno_device *) data; |
| 24 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
| 25 | unsigned int cur_rptr = adreno_get_rptr(adreno_dev->cur_rb); |
| 26 | unsigned int next_rptr = adreno_get_rptr(adreno_dev->next_rb); |
| 27 | |
| 28 | KGSL_DRV_ERR(device, |
| 29 | "Preemption timed out. cur_rb rptr/wptr %x/%x id %d, next_rb rptr/wptr %x/%x id %d, disp_state: %d\n", |
| 30 | cur_rptr, adreno_dev->cur_rb->wptr, adreno_dev->cur_rb->id, |
| 31 | next_rptr, adreno_dev->next_rb->wptr, adreno_dev->next_rb->id, |
| 32 | atomic_read(&adreno_dev->preempt.state)); |
| 33 | |
| 34 | adreno_set_gpu_fault(adreno_dev, ADRENO_PREEMPT_FAULT); |
| 35 | adreno_dispatcher_schedule(device); |
| 36 | } |
| 37 | |
| 38 | static unsigned int a4xx_preemption_token(struct adreno_device *adreno_dev, |
| 39 | unsigned int *cmds, uint64_t gpuaddr) |
| 40 | { |
| 41 | unsigned int *cmds_orig = cmds; |
| 42 | |
| 43 | /* Turn on preemption flag */ |
| 44 | /* preemption token - fill when pt switch command size is known */ |
| 45 | *cmds++ = cp_type3_packet(CP_PREEMPT_TOKEN, 3); |
| 46 | *cmds++ = (uint)gpuaddr; |
| 47 | *cmds++ = 1; |
| 48 | /* generate interrupt on preemption completion */ |
| 49 | *cmds++ = 1 << CP_PREEMPT_ORDINAL_INTERRUPT; |
| 50 | |
| 51 | return (unsigned int) (cmds - cmds_orig); |
| 52 | } |
| 53 | |
| 54 | unsigned int a4xx_preemption_pre_ibsubmit(struct adreno_device *adreno_dev, |
| 55 | struct adreno_ringbuffer *rb, unsigned int *cmds, |
| 56 | struct kgsl_context *context) |
| 57 | { |
| 58 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
| 59 | unsigned int *cmds_orig = cmds; |
| 60 | unsigned int cond_addr = device->memstore.gpuaddr + |
| 61 | MEMSTORE_ID_GPU_ADDR(device, context->id, preempted); |
| 62 | |
| 63 | cmds += a4xx_preemption_token(adreno_dev, cmds, cond_addr); |
| 64 | |
| 65 | *cmds++ = cp_type3_packet(CP_COND_EXEC, 4); |
| 66 | *cmds++ = cond_addr; |
| 67 | *cmds++ = cond_addr; |
| 68 | *cmds++ = 1; |
| 69 | *cmds++ = 7; |
| 70 | |
| 71 | /* clear preemption flag */ |
| 72 | *cmds++ = cp_type3_packet(CP_MEM_WRITE, 2); |
| 73 | *cmds++ = cond_addr; |
| 74 | *cmds++ = 0; |
| 75 | *cmds++ = cp_type3_packet(CP_WAIT_MEM_WRITES, 1); |
| 76 | *cmds++ = 0; |
| 77 | *cmds++ = cp_type3_packet(CP_WAIT_FOR_ME, 1); |
| 78 | *cmds++ = 0; |
| 79 | |
| 80 | return (unsigned int) (cmds - cmds_orig); |
| 81 | } |
| 82 | |
| 83 | |
| 84 | static void a4xx_preemption_start(struct adreno_device *adreno_dev, |
| 85 | struct adreno_ringbuffer *rb) |
| 86 | { |
| 87 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
| 88 | uint32_t val; |
| 89 | |
| 90 | /* |
| 91 | * Setup scratch registers from which the GPU will program the |
| 92 | * registers required to start execution of new ringbuffer |
| 93 | * set ringbuffer address |
| 94 | */ |
| 95 | kgsl_regwrite(device, A4XX_CP_SCRATCH_REG8, |
| 96 | rb->buffer_desc.gpuaddr); |
| 97 | kgsl_regread(device, A4XX_CP_RB_CNTL, &val); |
| 98 | /* scratch REG9 corresponds to CP_RB_CNTL register */ |
| 99 | kgsl_regwrite(device, A4XX_CP_SCRATCH_REG9, val); |
| 100 | /* scratch REG10 corresponds to rptr address */ |
| 101 | kgsl_regwrite(device, A4XX_CP_SCRATCH_REG10, |
| 102 | SCRATCH_RPTR_GPU_ADDR(device, rb->id)); |
| 103 | /* scratch REG11 corresponds to rptr */ |
| 104 | kgsl_regwrite(device, A4XX_CP_SCRATCH_REG11, adreno_get_rptr(rb)); |
| 105 | /* scratch REG12 corresponds to wptr */ |
| 106 | kgsl_regwrite(device, A4XX_CP_SCRATCH_REG12, rb->wptr); |
| 107 | /* |
| 108 | * scratch REG13 corresponds to IB1_BASE, |
| 109 | * 0 since we do not do switches in between IB's |
| 110 | */ |
| 111 | kgsl_regwrite(device, A4XX_CP_SCRATCH_REG13, 0); |
| 112 | /* scratch REG14 corresponds to IB1_BUFSZ */ |
| 113 | kgsl_regwrite(device, A4XX_CP_SCRATCH_REG14, 0); |
| 114 | /* scratch REG15 corresponds to IB2_BASE */ |
| 115 | kgsl_regwrite(device, A4XX_CP_SCRATCH_REG15, 0); |
| 116 | /* scratch REG16 corresponds to IB2_BUFSZ */ |
| 117 | kgsl_regwrite(device, A4XX_CP_SCRATCH_REG16, 0); |
| 118 | /* scratch REG17 corresponds to GPR11 */ |
| 119 | kgsl_regwrite(device, A4XX_CP_SCRATCH_REG17, rb->gpr11); |
| 120 | } |
| 121 | |
| 122 | static void a4xx_preemption_save(struct adreno_device *adreno_dev, |
| 123 | struct adreno_ringbuffer *rb) |
| 124 | { |
| 125 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
| 126 | |
| 127 | kgsl_regread(device, A4XX_CP_SCRATCH_REG23, &rb->gpr11); |
| 128 | } |
| 129 | |
| 130 | |
| 131 | static int a4xx_submit_preempt_token(struct adreno_ringbuffer *rb, |
| 132 | struct adreno_ringbuffer *incoming_rb) |
| 133 | { |
| 134 | struct adreno_device *adreno_dev = ADRENO_RB_DEVICE(rb); |
| 135 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
| 136 | unsigned int *ringcmds, *start; |
| 137 | int ptname; |
| 138 | struct kgsl_pagetable *pt; |
| 139 | int pt_switch_sizedwords = 0, total_sizedwords = 20; |
| 140 | unsigned int link[ADRENO_RB_PREEMPT_TOKEN_DWORDS]; |
| 141 | uint i; |
| 142 | |
| 143 | if (incoming_rb->preempted_midway) { |
| 144 | |
| 145 | kgsl_sharedmem_readl(&incoming_rb->pagetable_desc, |
| 146 | &ptname, PT_INFO_OFFSET(current_rb_ptname)); |
| 147 | pt = kgsl_mmu_get_pt_from_ptname(&(device->mmu), |
| 148 | ptname); |
| 149 | if (IS_ERR_OR_NULL(pt)) |
| 150 | return (pt == NULL) ? -ENOENT : PTR_ERR(pt); |
| 151 | /* set the ringbuffer for incoming RB */ |
| 152 | pt_switch_sizedwords = |
| 153 | adreno_iommu_set_pt_generate_cmds(incoming_rb, |
| 154 | &link[0], pt); |
| 155 | total_sizedwords += pt_switch_sizedwords; |
| 156 | } |
| 157 | |
| 158 | /* |
| 159 | * Allocate total_sizedwords space in RB, this is the max space |
| 160 | * required. |
| 161 | */ |
| 162 | ringcmds = adreno_ringbuffer_allocspace(rb, total_sizedwords); |
| 163 | |
| 164 | if (IS_ERR(ringcmds)) |
| 165 | return PTR_ERR(ringcmds); |
| 166 | |
| 167 | start = ringcmds; |
| 168 | |
| 169 | *ringcmds++ = cp_packet(adreno_dev, CP_SET_PROTECTED_MODE, 1); |
| 170 | *ringcmds++ = 0; |
| 171 | |
| 172 | if (incoming_rb->preempted_midway) { |
| 173 | for (i = 0; i < pt_switch_sizedwords; i++) |
| 174 | *ringcmds++ = link[i]; |
| 175 | } |
| 176 | |
| 177 | *ringcmds++ = cp_register(adreno_dev, adreno_getreg(adreno_dev, |
| 178 | ADRENO_REG_CP_PREEMPT_DISABLE), 1); |
| 179 | *ringcmds++ = 0; |
| 180 | |
| 181 | *ringcmds++ = cp_packet(adreno_dev, CP_SET_PROTECTED_MODE, 1); |
| 182 | *ringcmds++ = 1; |
| 183 | |
| 184 | ringcmds += a4xx_preemption_token(adreno_dev, ringcmds, |
| 185 | device->memstore.gpuaddr + |
| 186 | MEMSTORE_RB_OFFSET(rb, preempted)); |
| 187 | |
| 188 | if ((uint)(ringcmds - start) > total_sizedwords) |
| 189 | KGSL_DRV_ERR(device, "Insufficient rb size allocated\n"); |
| 190 | |
| 191 | /* |
| 192 | * If we have commands less than the space reserved in RB |
| 193 | * adjust the wptr accordingly |
| 194 | */ |
| 195 | rb->wptr = rb->wptr - (total_sizedwords - (uint)(ringcmds - start)); |
| 196 | |
| 197 | /* submit just the preempt token */ |
| 198 | mb(); |
| 199 | kgsl_pwrscale_busy(device); |
| 200 | adreno_writereg(adreno_dev, ADRENO_REG_CP_RB_WPTR, rb->wptr); |
| 201 | return 0; |
| 202 | } |
| 203 | |
| 204 | static void a4xx_preempt_trig_state(struct adreno_device *adreno_dev) |
| 205 | { |
| 206 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
| 207 | unsigned int rbbase, val; |
| 208 | int ret; |
| 209 | |
| 210 | /* |
| 211 | * Hardware not yet idle means that preemption interrupt |
| 212 | * may still occur, nothing to do here until interrupt signals |
| 213 | * completion of preemption, just return here |
| 214 | */ |
| 215 | if (!adreno_hw_isidle(adreno_dev)) |
| 216 | return; |
| 217 | |
| 218 | /* |
| 219 | * We just changed states, reschedule dispatcher to change |
| 220 | * preemption states |
| 221 | */ |
| 222 | |
| 223 | if (atomic_read(&adreno_dev->preempt.state) != |
| 224 | ADRENO_PREEMPT_TRIGGERED) { |
| 225 | adreno_dispatcher_schedule(device); |
| 226 | return; |
| 227 | } |
| 228 | |
| 229 | /* |
| 230 | * H/W is idle and we did not get a preemption interrupt, may |
| 231 | * be device went idle w/o encountering any preempt token or |
| 232 | * we already preempted w/o interrupt |
| 233 | */ |
| 234 | adreno_readreg(adreno_dev, ADRENO_REG_CP_RB_BASE, &rbbase); |
| 235 | /* Did preemption occur, if so then change states and return */ |
| 236 | if (rbbase != adreno_dev->cur_rb->buffer_desc.gpuaddr) { |
| 237 | adreno_readreg(adreno_dev, ADRENO_REG_CP_PREEMPT_DEBUG, &val); |
| 238 | if (val && rbbase == adreno_dev->next_rb->buffer_desc.gpuaddr) { |
| 239 | KGSL_DRV_INFO(device, |
| 240 | "Preemption completed without interrupt\n"); |
| 241 | trace_adreno_hw_preempt_trig_to_comp(adreno_dev->cur_rb, |
| 242 | adreno_dev->next_rb, |
| 243 | adreno_get_rptr(adreno_dev->cur_rb), |
| 244 | adreno_get_rptr(adreno_dev->next_rb)); |
| 245 | adreno_set_preempt_state(adreno_dev, |
| 246 | ADRENO_PREEMPT_COMPLETE); |
| 247 | adreno_dispatcher_schedule(device); |
| 248 | return; |
| 249 | } |
| 250 | adreno_set_gpu_fault(adreno_dev, ADRENO_PREEMPT_FAULT); |
| 251 | /* reschedule dispatcher to take care of the fault */ |
| 252 | adreno_dispatcher_schedule(device); |
| 253 | return; |
| 254 | } |
| 255 | /* |
| 256 | * Check if preempt token was submitted after preemption trigger, if so |
| 257 | * then preemption should have occurred, since device is already idle it |
| 258 | * means something went wrong - trigger FT |
| 259 | */ |
| 260 | if (adreno_dev->preempt.token_submit) { |
| 261 | adreno_set_gpu_fault(adreno_dev, ADRENO_PREEMPT_FAULT); |
| 262 | /* reschedule dispatcher to take care of the fault */ |
| 263 | adreno_dispatcher_schedule(device); |
| 264 | return; |
| 265 | } |
| 266 | /* |
| 267 | * Preempt token was not submitted after preemption trigger so device |
| 268 | * may have gone idle before preemption could occur, if there are |
| 269 | * commands that got submitted to current RB after triggering preemption |
| 270 | * then submit them as those commands may have a preempt token in them |
| 271 | */ |
| 272 | if (!adreno_rb_empty(adreno_dev->cur_rb)) { |
| 273 | /* |
| 274 | * Memory barrier before informing the |
| 275 | * hardware of new commands |
| 276 | */ |
| 277 | mb(); |
| 278 | kgsl_pwrscale_busy(device); |
| 279 | adreno_writereg(adreno_dev, ADRENO_REG_CP_RB_WPTR, |
| 280 | adreno_dev->cur_rb->wptr); |
| 281 | return; |
| 282 | } |
| 283 | |
| 284 | /* Submit preempt token to make preemption happen */ |
| 285 | ret = adreno_drawctxt_switch(adreno_dev, adreno_dev->cur_rb, |
| 286 | NULL, 0); |
| 287 | if (ret) |
| 288 | KGSL_DRV_ERR(device, |
| 289 | "Unable to switch context to NULL: %d\n", ret); |
| 290 | |
| 291 | ret = a4xx_submit_preempt_token(adreno_dev->cur_rb, |
| 292 | adreno_dev->next_rb); |
| 293 | if (ret) |
| 294 | KGSL_DRV_ERR(device, |
| 295 | "Unable to submit preempt token: %d\n", ret); |
| 296 | |
| 297 | adreno_dev->preempt.token_submit = true; |
| 298 | adreno_dev->cur_rb->wptr_preempt_end = adreno_dev->cur_rb->wptr; |
| 299 | trace_adreno_hw_preempt_token_submit(adreno_dev->cur_rb, |
| 300 | adreno_dev->next_rb, |
| 301 | adreno_get_rptr(adreno_dev->cur_rb), |
| 302 | adreno_get_rptr(adreno_dev->next_rb)); |
| 303 | } |
| 304 | |
| 305 | static struct adreno_ringbuffer *a4xx_next_ringbuffer( |
| 306 | struct adreno_device *adreno_dev) |
| 307 | { |
| 308 | struct adreno_ringbuffer *rb, *next = NULL; |
| 309 | int i; |
| 310 | |
| 311 | FOR_EACH_RINGBUFFER(adreno_dev, rb, i) { |
| 312 | if (!adreno_rb_empty(rb) && next == NULL) { |
| 313 | next = rb; |
| 314 | continue; |
| 315 | } |
| 316 | |
| 317 | if (!adreno_disp_preempt_fair_sched) |
| 318 | continue; |
| 319 | |
| 320 | switch (rb->starve_timer_state) { |
| 321 | case ADRENO_DISPATCHER_RB_STARVE_TIMER_UNINIT: |
| 322 | if (!adreno_rb_empty(rb) && |
| 323 | adreno_dev->cur_rb != rb) { |
| 324 | rb->starve_timer_state = |
| 325 | ADRENO_DISPATCHER_RB_STARVE_TIMER_INIT; |
| 326 | rb->sched_timer = jiffies; |
| 327 | } |
| 328 | break; |
| 329 | case ADRENO_DISPATCHER_RB_STARVE_TIMER_INIT: |
| 330 | if (time_after(jiffies, rb->sched_timer + |
| 331 | msecs_to_jiffies( |
| 332 | adreno_dispatch_starvation_time))) { |
| 333 | rb->starve_timer_state = |
| 334 | ADRENO_DISPATCHER_RB_STARVE_TIMER_ELAPSED; |
| 335 | /* halt dispatcher to remove starvation */ |
| 336 | adreno_get_gpu_halt(adreno_dev); |
| 337 | } |
| 338 | break; |
| 339 | case ADRENO_DISPATCHER_RB_STARVE_TIMER_SCHEDULED: |
| 340 | /* |
| 341 | * If the RB has not been running for the minimum |
| 342 | * time slice then allow it to run |
| 343 | */ |
| 344 | if (!adreno_rb_empty(rb) && time_before(jiffies, |
| 345 | adreno_dev->cur_rb->sched_timer + |
| 346 | msecs_to_jiffies(adreno_dispatch_time_slice))) |
| 347 | next = rb; |
| 348 | else |
| 349 | rb->starve_timer_state = |
| 350 | ADRENO_DISPATCHER_RB_STARVE_TIMER_UNINIT; |
| 351 | break; |
| 352 | case ADRENO_DISPATCHER_RB_STARVE_TIMER_ELAPSED: |
| 353 | default: |
| 354 | break; |
| 355 | } |
| 356 | } |
| 357 | |
| 358 | return next; |
| 359 | } |
| 360 | |
| 361 | static void a4xx_preempt_clear_state(struct adreno_device *adreno_dev) |
| 362 | |
| 363 | { |
| 364 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
| 365 | struct adreno_ringbuffer *highest_busy_rb; |
| 366 | int switch_low_to_high; |
| 367 | int ret; |
| 368 | |
| 369 | /* Device not awake means there is nothing to do */ |
| 370 | if (!kgsl_state_is_awake(device)) |
| 371 | return; |
| 372 | |
| 373 | highest_busy_rb = a4xx_next_ringbuffer(adreno_dev); |
| 374 | if (!highest_busy_rb || highest_busy_rb == adreno_dev->cur_rb) |
| 375 | return; |
| 376 | |
| 377 | switch_low_to_high = adreno_compare_prio_level( |
| 378 | highest_busy_rb->id, |
| 379 | adreno_dev->cur_rb->id); |
| 380 | |
| 381 | if (switch_low_to_high < 0) { |
| 382 | /* |
| 383 | * if switching to lower priority make sure that the rptr and |
| 384 | * wptr are equal, when the lower rb is not starved |
| 385 | */ |
| 386 | if (!adreno_rb_empty(adreno_dev->cur_rb)) |
| 387 | return; |
| 388 | /* |
| 389 | * switch to default context because when we switch back |
| 390 | * to higher context then its not known which pt will |
| 391 | * be current, so by making it default here the next |
| 392 | * commands submitted will set the right pt |
| 393 | */ |
| 394 | ret = adreno_drawctxt_switch(adreno_dev, |
| 395 | adreno_dev->cur_rb, |
| 396 | NULL, 0); |
| 397 | /* |
| 398 | * lower priority RB has to wait until space opens up in |
| 399 | * higher RB |
| 400 | */ |
| 401 | if (ret) { |
| 402 | KGSL_DRV_ERR(device, |
| 403 | "Unable to switch context to NULL: %d", |
| 404 | ret); |
| 405 | |
| 406 | return; |
| 407 | } |
| 408 | |
| 409 | adreno_writereg(adreno_dev, |
| 410 | ADRENO_REG_CP_PREEMPT_DISABLE, 1); |
| 411 | } |
| 412 | |
| 413 | /* |
| 414 | * setup registers to do the switch to highest priority RB |
| 415 | * which is not empty or may be starving away(poor thing) |
| 416 | */ |
| 417 | a4xx_preemption_start(adreno_dev, highest_busy_rb); |
| 418 | |
| 419 | adreno_set_preempt_state(adreno_dev, ADRENO_PREEMPT_TRIGGERED); |
| 420 | |
| 421 | adreno_dev->next_rb = highest_busy_rb; |
| 422 | mod_timer(&adreno_dev->preempt.timer, jiffies + |
| 423 | msecs_to_jiffies(ADRENO_PREEMPT_TIMEOUT)); |
| 424 | |
| 425 | trace_adreno_hw_preempt_clear_to_trig(adreno_dev->cur_rb, |
| 426 | adreno_dev->next_rb, |
| 427 | adreno_get_rptr(adreno_dev->cur_rb), |
| 428 | adreno_get_rptr(adreno_dev->next_rb)); |
| 429 | /* issue PREEMPT trigger */ |
| 430 | adreno_writereg(adreno_dev, ADRENO_REG_CP_PREEMPT, 1); |
| 431 | |
| 432 | /* submit preempt token packet to ensure preemption */ |
| 433 | if (switch_low_to_high < 0) { |
| 434 | ret = a4xx_submit_preempt_token( |
| 435 | adreno_dev->cur_rb, adreno_dev->next_rb); |
| 436 | KGSL_DRV_ERR(device, |
| 437 | "Unable to submit preempt token: %d\n", ret); |
| 438 | adreno_dev->preempt.token_submit = true; |
| 439 | adreno_dev->cur_rb->wptr_preempt_end = adreno_dev->cur_rb->wptr; |
| 440 | } else { |
| 441 | adreno_dev->preempt.token_submit = false; |
| 442 | adreno_dispatcher_schedule(device); |
| 443 | adreno_dev->cur_rb->wptr_preempt_end = 0xFFFFFFFF; |
| 444 | } |
| 445 | } |
| 446 | |
| 447 | static void a4xx_preempt_complete_state(struct adreno_device *adreno_dev) |
| 448 | |
| 449 | { |
| 450 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
| 451 | unsigned int wptr, rbbase; |
| 452 | unsigned int val, val1; |
| 453 | unsigned int prevrptr; |
| 454 | |
| 455 | del_timer_sync(&adreno_dev->preempt.timer); |
| 456 | |
| 457 | adreno_readreg(adreno_dev, ADRENO_REG_CP_PREEMPT, &val); |
| 458 | adreno_readreg(adreno_dev, ADRENO_REG_CP_PREEMPT_DEBUG, &val1); |
| 459 | |
| 460 | if (val || !val1) { |
| 461 | KGSL_DRV_ERR(device, |
| 462 | "Invalid state after preemption CP_PREEMPT: %08x, CP_PREEMPT_DEBUG: %08x\n", |
| 463 | val, val1); |
| 464 | adreno_set_gpu_fault(adreno_dev, ADRENO_PREEMPT_FAULT); |
| 465 | adreno_dispatcher_schedule(device); |
| 466 | return; |
| 467 | } |
| 468 | adreno_readreg(adreno_dev, ADRENO_REG_CP_RB_BASE, &rbbase); |
| 469 | if (rbbase != adreno_dev->next_rb->buffer_desc.gpuaddr) { |
| 470 | KGSL_DRV_ERR(device, |
| 471 | "RBBASE incorrect after preemption, expected %x got %016llx\b", |
| 472 | rbbase, |
| 473 | adreno_dev->next_rb->buffer_desc.gpuaddr); |
| 474 | adreno_set_gpu_fault(adreno_dev, ADRENO_PREEMPT_FAULT); |
| 475 | adreno_dispatcher_schedule(device); |
| 476 | return; |
| 477 | } |
| 478 | |
| 479 | a4xx_preemption_save(adreno_dev, adreno_dev->cur_rb); |
| 480 | |
| 481 | /* new RB is the current RB */ |
| 482 | trace_adreno_hw_preempt_comp_to_clear(adreno_dev->next_rb, |
| 483 | adreno_dev->cur_rb, |
| 484 | adreno_get_rptr(adreno_dev->next_rb), |
| 485 | adreno_get_rptr(adreno_dev->cur_rb)); |
| 486 | |
| 487 | adreno_dev->prev_rb = adreno_dev->cur_rb; |
| 488 | adreno_dev->cur_rb = adreno_dev->next_rb; |
| 489 | adreno_dev->cur_rb->preempted_midway = 0; |
| 490 | adreno_dev->cur_rb->wptr_preempt_end = 0xFFFFFFFF; |
| 491 | adreno_dev->next_rb = NULL; |
| 492 | |
| 493 | if (adreno_disp_preempt_fair_sched) { |
| 494 | /* starved rb is now scheduled so unhalt dispatcher */ |
| 495 | if (ADRENO_DISPATCHER_RB_STARVE_TIMER_ELAPSED == |
| 496 | adreno_dev->cur_rb->starve_timer_state) |
| 497 | adreno_put_gpu_halt(adreno_dev); |
| 498 | adreno_dev->cur_rb->starve_timer_state = |
| 499 | ADRENO_DISPATCHER_RB_STARVE_TIMER_SCHEDULED; |
| 500 | adreno_dev->cur_rb->sched_timer = jiffies; |
| 501 | /* |
| 502 | * If the outgoing RB is has commands then set the |
| 503 | * busy time for it |
| 504 | */ |
| 505 | if (!adreno_rb_empty(adreno_dev->prev_rb)) { |
| 506 | adreno_dev->prev_rb->starve_timer_state = |
| 507 | ADRENO_DISPATCHER_RB_STARVE_TIMER_INIT; |
| 508 | adreno_dev->prev_rb->sched_timer = jiffies; |
| 509 | } else { |
| 510 | adreno_dev->prev_rb->starve_timer_state = |
| 511 | ADRENO_DISPATCHER_RB_STARVE_TIMER_UNINIT; |
| 512 | } |
| 513 | } |
| 514 | adreno_set_preempt_state(adreno_dev, ADRENO_PREEMPT_NONE); |
| 515 | |
| 516 | prevrptr = adreno_get_rptr(adreno_dev->prev_rb); |
| 517 | |
| 518 | if (adreno_compare_prio_level(adreno_dev->prev_rb->id, |
| 519 | adreno_dev->cur_rb->id) < 0) { |
| 520 | if (adreno_dev->prev_rb->wptr_preempt_end != prevrptr) |
| 521 | adreno_dev->prev_rb->preempted_midway = 1; |
| 522 | } |
| 523 | |
| 524 | /* submit wptr if required for new rb */ |
| 525 | adreno_readreg(adreno_dev, ADRENO_REG_CP_RB_WPTR, &wptr); |
| 526 | if (adreno_dev->cur_rb->wptr != wptr) { |
| 527 | kgsl_pwrscale_busy(device); |
| 528 | adreno_writereg(adreno_dev, ADRENO_REG_CP_RB_WPTR, |
| 529 | adreno_dev->cur_rb->wptr); |
| 530 | } |
| 531 | /* clear preemption register */ |
| 532 | adreno_writereg(adreno_dev, ADRENO_REG_CP_PREEMPT_DEBUG, 0); |
| 533 | } |
| 534 | |
| 535 | void a4xx_preemption_schedule(struct adreno_device *adreno_dev) |
| 536 | { |
| 537 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
| 538 | |
| 539 | if (!adreno_is_preemption_enabled(adreno_dev)) |
| 540 | return; |
| 541 | |
| 542 | mutex_lock(&device->mutex); |
| 543 | |
| 544 | switch (atomic_read(&adreno_dev->preempt.state)) { |
| 545 | case ADRENO_PREEMPT_NONE: |
| 546 | a4xx_preempt_clear_state(adreno_dev); |
| 547 | break; |
| 548 | case ADRENO_PREEMPT_TRIGGERED: |
| 549 | a4xx_preempt_trig_state(adreno_dev); |
| 550 | /* |
| 551 | * if we transitioned to next state then fall-through |
| 552 | * processing to next state |
| 553 | */ |
| 554 | if (!adreno_in_preempt_state(adreno_dev, |
| 555 | ADRENO_PREEMPT_COMPLETE)) |
| 556 | break; |
| 557 | case ADRENO_PREEMPT_COMPLETE: |
| 558 | a4xx_preempt_complete_state(adreno_dev); |
| 559 | break; |
| 560 | default: |
| 561 | break; |
| 562 | } |
| 563 | |
| 564 | mutex_unlock(&device->mutex); |
| 565 | } |
| 566 | |
| 567 | int a4xx_preemption_init(struct adreno_device *adreno_dev) |
| 568 | { |
| 569 | setup_timer(&adreno_dev->preempt.timer, a4xx_preemption_timer, |
| 570 | (unsigned long) adreno_dev); |
| 571 | |
| 572 | return 0; |
| 573 | } |