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Ben Skeggs9274f4a2012-07-06 07:36:43 +10001/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include <subdev/device.h>
Ben Skeggs70c0f262012-07-10 10:49:22 +100026#include <subdev/bios.h>
Ben Skeggse0996ae2012-07-10 12:20:17 +100027#include <subdev/gpio.h>
Ben Skeggs4196faa2012-07-10 14:36:38 +100028#include <subdev/i2c.h>
Ben Skeggs8aceb7d2012-07-10 16:45:24 +100029#include <subdev/clock.h>
Ben Skeggscb75d972012-07-11 10:44:20 +100030#include <subdev/devinit.h>
Ben Skeggs7d9115d2012-07-11 15:58:56 +100031#include <subdev/mc.h>
Ben Skeggs5a5c7432012-07-11 16:08:25 +100032#include <subdev/timer.h>
Ben Skeggs861d2102012-07-11 19:05:01 +100033#include <subdev/fb.h>
34#include <subdev/ltcg.h>
Ben Skeggs9274f4a2012-07-06 07:36:43 +100035
36int
37nvc0_identify(struct nouveau_device *device)
38{
39 switch (device->chipset) {
40 case 0xc0:
Ben Skeggs70c0f262012-07-10 10:49:22 +100041 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +100042 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +100043 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +100044 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +100045 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +100046 device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +100047 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +100048 device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
49 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +100050 break;
51 case 0xc4:
Ben Skeggs70c0f262012-07-10 10:49:22 +100052 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +100053 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +100054 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +100055 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +100056 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +100057 device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +100058 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +100059 device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
60 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +100061 break;
62 case 0xc3:
Ben Skeggs70c0f262012-07-10 10:49:22 +100063 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +100064 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +100065 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +100066 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +100067 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +100068 device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +100069 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +100070 device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
71 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +100072 break;
73 case 0xce:
Ben Skeggs70c0f262012-07-10 10:49:22 +100074 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +100075 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +100076 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +100077 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +100078 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +100079 device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +100080 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +100081 device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
82 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +100083 break;
84 case 0xcf:
Ben Skeggs70c0f262012-07-10 10:49:22 +100085 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +100086 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +100087 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +100088 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +100089 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +100090 device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +100091 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +100092 device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
93 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +100094 break;
95 case 0xc1:
Ben Skeggs70c0f262012-07-10 10:49:22 +100096 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +100097 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +100098 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +100099 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000100 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000101 device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000102 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000103 device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
104 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000105 break;
106 case 0xc8:
Ben Skeggs70c0f262012-07-10 10:49:22 +1000107 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000108 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000109 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000110 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000111 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000112 device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000113 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000114 device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
115 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000116 break;
117 case 0xd9:
Ben Skeggs70c0f262012-07-10 10:49:22 +1000118 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000119 device->oclass[NVDEV_SUBDEV_GPIO ] = &nvd0_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000120 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000121 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000122 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000123 device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000124 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000125 device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
126 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000127 break;
128 default:
129 nv_fatal(device, "unknown Fermi chipset\n");
130 return -EINVAL;
131 }
132
133 return 0;
134}