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Jean-Christophe PLAGNIOL-VILLARD23fa6482012-02-27 11:19:34 +01001Atmel AT91 device tree bindings.
2================================
3
4PIT Timer required properties:
5- compatible: Should be "atmel,at91sam9260-pit"
6- reg: Should contain registers location and length
7- interrupts: Should contain interrupt for the PIT which is the IRQ line
8 shared across all System Controller members.
Nicolas Ferre3a61a5d2012-01-19 10:13:40 +01009
Joachim Eastwood454c46d2012-10-28 18:31:07 +000010System Timer (ST) required properties:
11- compatible: Should be "atmel,at91rm9200-st"
12- reg: Should contain registers location and length
13- interrupts: Should contain interrupt for the ST which is the IRQ line
14 shared across all System Controller members.
15
Nicolas Ferre3a61a5d2012-01-19 10:13:40 +010016TC/TCLIB Timer required properties:
Josh Wu11930c52012-09-14 17:01:29 +080017- compatible: Should be "atmel,<chip>-tcb".
Nicolas Ferre3a61a5d2012-01-19 10:13:40 +010018 <chip> can be "at91rm9200" or "at91sam9x5"
19- reg: Should contain registers location and length
20- interrupts: Should contain all interrupts for the TC block
21 Note that you can specify several interrupt cells if the TC
22 block has one interrupt per channel.
Boris BREZILLON864382d2013-12-17 16:47:14 +010023- clock-names: tuple listing input clock names.
24 Required elements: "t0_clk"
25 Optional elements: "t1_clk", "t2_clk"
26- clocks: phandles to input clocks.
Nicolas Ferre3a61a5d2012-01-19 10:13:40 +010027
28Examples:
29
30One interrupt per TC block:
31 tcb0: timer@fff7c000 {
32 compatible = "atmel,at91rm9200-tcb";
33 reg = <0xfff7c000 0x100>;
34 interrupts = <18 4>;
Boris BREZILLON864382d2013-12-17 16:47:14 +010035 clocks = <&tcb0_clk>;
36 clock-names = "t0_clk";
Nicolas Ferre3a61a5d2012-01-19 10:13:40 +010037 };
38
39One interrupt per TC channel in a TC block:
40 tcb1: timer@fffdc000 {
41 compatible = "atmel,at91rm9200-tcb";
42 reg = <0xfffdc000 0x100>;
43 interrupts = <26 4 27 4 28 4>;
Boris BREZILLON864382d2013-12-17 16:47:14 +010044 clocks = <&tcb1_clk>;
45 clock-names = "t0_clk";
Nicolas Ferre3a61a5d2012-01-19 10:13:40 +010046 };
Jean-Christophe PLAGNIOL-VILLARDc8082d32012-03-03 03:16:27 +080047
48RSTC Reset Controller required properties:
49- compatible: Should be "atmel,<chip>-rstc".
50 <chip> can be "at91sam9260" or "at91sam9g45"
51- reg: Should contain registers location and length
52
53Example:
54
55 rstc@fffffd00 {
56 compatible = "atmel,at91sam9260-rstc";
57 reg = <0xfffffd00 0x10>;
58 };
Jean-Christophe PLAGNIOL-VILLARDa7776ec2012-03-02 20:54:37 +080059
60RAMC SDRAM/DDR Controller required properties:
61- compatible: Should be "atmel,at91sam9260-sdramc",
62 "atmel,at91sam9g45-ddramc",
63- reg: Should contain registers location and length
64 For at91sam9263 and at91sam9g45 you must specify 2 entries.
65
66Examples:
67
68 ramc0: ramc@ffffe800 {
69 compatible = "atmel,at91sam9g45-ddramc";
70 reg = <0xffffe800 0x200>;
71 };
72
73 ramc0: ramc@ffffe400 {
74 compatible = "atmel,at91sam9g45-ddramc";
75 reg = <0xffffe400 0x200
76 0xffffe600 0x200>;
77 };
Jean-Christophe PLAGNIOL-VILLARD82015c42012-03-02 21:01:00 +080078
79SHDWC Shutdown Controller
80
81required properties:
82- compatible: Should be "atmel,<chip>-shdwc".
83 <chip> can be "at91sam9260", "at91sam9rl" or "at91sam9x5".
84- reg: Should contain registers location and length
85
86optional properties:
87- atmel,wakeup-mode: String, operation mode of the wakeup mode.
88 Supported values are: "none", "high", "low", "any".
89- atmel,wakeup-counter: Counter on Wake-up 0 (between 0x0 and 0xf).
90
91optional at91sam9260 properties:
92- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
93
94optional at91sam9rl properties:
95- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up.
96- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
97
98optional at91sam9x5 properties:
99- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up.
100
101Example:
102
103 rstc@fffffd00 {
104 compatible = "atmel,at91sam9260-rstc";
105 reg = <0xfffffd00 0x10>;
106 };