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Sergei Shtylyov60e7a822007-05-05 22:03:49 +02001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 * Due to massive hardware bugs, UltraDMA is only supported
4 * on the 646U2 and not on the 646U.
5 *
6 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
7 * Copyright (C) 1998 David S. Miller (davem@redhat.com)
8 *
9 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
Sergei Shtylyovf92d50e62007-03-03 17:48:53 +010010 * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
Linus Torvalds1da177e2005-04-16 15:20:36 -070011 */
12
Linus Torvalds1da177e2005-04-16 15:20:36 -070013#include <linux/module.h>
14#include <linux/types.h>
15#include <linux/pci.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070016#include <linux/hdreg.h>
17#include <linux/ide.h>
18#include <linux/init.h>
19
20#include <asm/io.h>
21
Linus Torvalds1da177e2005-04-16 15:20:36 -070022#define CMD_DEBUG 0
23
24#if CMD_DEBUG
25#define cmdprintk(x...) printk(x)
26#else
27#define cmdprintk(x...)
28#endif
29
30/*
31 * CMD64x specific registers definition.
32 */
33#define CFR 0x50
Sergei Shtylyove51e2522007-05-05 22:03:49 +020034#define CFR_INTR_CH0 0x04
Linus Torvalds1da177e2005-04-16 15:20:36 -070035
36#define CMDTIM 0x52
37#define ARTTIM0 0x53
38#define DRWTIM0 0x54
39#define ARTTIM1 0x55
40#define DRWTIM1 0x56
41#define ARTTIM23 0x57
42#define ARTTIM23_DIS_RA2 0x04
43#define ARTTIM23_DIS_RA3 0x08
44#define ARTTIM23_INTR_CH1 0x10
Linus Torvalds1da177e2005-04-16 15:20:36 -070045#define DRWTIM2 0x58
46#define BRST 0x59
47#define DRWTIM3 0x5b
48
49#define BMIDECR0 0x70
50#define MRDMODE 0x71
51#define MRDMODE_INTR_CH0 0x04
52#define MRDMODE_INTR_CH1 0x08
Linus Torvalds1da177e2005-04-16 15:20:36 -070053#define UDIDETCR0 0x73
54#define DTPR0 0x74
55#define BMIDECR1 0x78
56#define BMIDECSR 0x79
Linus Torvalds1da177e2005-04-16 15:20:36 -070057#define UDIDETCR1 0x7B
58#define DTPR1 0x7C
59
Sergei Shtylyove277a1a2007-03-17 21:57:24 +010060static u8 quantize_timing(int timing, int quant)
61{
62 return (timing + quant - 1) / quant;
63}
64
Linus Torvalds1da177e2005-04-16 15:20:36 -070065/*
Sergei Shtylyov60e7a822007-05-05 22:03:49 +020066 * This routine calculates active/recovery counts and then writes them into
67 * the chipset registers.
Linus Torvalds1da177e2005-04-16 15:20:36 -070068 */
Sergei Shtylyov60e7a822007-05-05 22:03:49 +020069static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_time)
Linus Torvalds1da177e2005-04-16 15:20:36 -070070{
Bartlomiej Zolnierkiewiczebae41a2008-04-27 15:38:29 +020071 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
Bartlomiej Zolnierkiewicz30e5ee42008-07-15 21:21:46 +020072 int clock_time = 1000 / (ide_pci_clk ? ide_pci_clk : 33);
Sergei Shtylyov60e7a822007-05-05 22:03:49 +020073 u8 cycle_count, active_count, recovery_count, drwtim;
74 static const u8 recovery_values[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -070075 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
Sergei Shtylyov60e7a822007-05-05 22:03:49 +020076 static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};
Linus Torvalds1da177e2005-04-16 15:20:36 -070077
Sergei Shtylyov60e7a822007-05-05 22:03:49 +020078 cmdprintk("program_cycle_times parameters: total=%d, active=%d\n",
79 cycle_time, active_time);
80
81 cycle_count = quantize_timing( cycle_time, clock_time);
82 active_count = quantize_timing(active_time, clock_time);
83 recovery_count = cycle_count - active_count;
Linus Torvalds1da177e2005-04-16 15:20:36 -070084
85 /*
Sergei Shtylyov60e7a822007-05-05 22:03:49 +020086 * In case we've got too long recovery phase, try to lengthen
87 * the active phase
Linus Torvalds1da177e2005-04-16 15:20:36 -070088 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070089 if (recovery_count > 16) {
90 active_count += recovery_count - 16;
91 recovery_count = 16;
92 }
Sergei Shtylyov60e7a822007-05-05 22:03:49 +020093 if (active_count > 16) /* shouldn't actually happen... */
94 active_count = 16;
Linus Torvalds1da177e2005-04-16 15:20:36 -070095
Sergei Shtylyov60e7a822007-05-05 22:03:49 +020096 cmdprintk("Final counts: total=%d, active=%d, recovery=%d\n",
97 cycle_count, active_count, recovery_count);
Linus Torvalds1da177e2005-04-16 15:20:36 -070098
Sergei Shtylyov60e7a822007-05-05 22:03:49 +020099 /*
100 * Convert values to internal chipset representation
101 */
102 recovery_count = recovery_values[recovery_count];
103 active_count &= 0x0f;
104
105 /* Program the active/recovery counts into the DRWTIM register */
106 drwtim = (active_count << 4) | recovery_count;
107 (void) pci_write_config_byte(dev, drwtim_regs[drive->dn], drwtim);
108 cmdprintk("Write 0x%02x to reg 0x%x\n", drwtim, drwtim_regs[drive->dn]);
109}
110
111/*
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200112 * This routine writes into the chipset registers
113 * PIO setup/active/recovery timings.
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200114 */
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200115static void cmd64x_tune_pio(ide_drive_t *drive, const u8 pio)
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200116{
117 ide_hwif_t *hwif = HWIF(drive);
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100118 struct pci_dev *dev = to_pci_dev(hwif->dev);
Bartlomiej Zolnierkiewicz86a0e122008-07-16 20:33:38 +0200119 struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200120 unsigned int cycle_time;
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200121 u8 setup_count, arttim = 0;
122
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200123 static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
124 static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200125
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200126 cycle_time = ide_pio_cycle_time(drive, pio);
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200127
Bartlomiej Zolnierkiewicz86a0e122008-07-16 20:33:38 +0200128 program_cycle_times(drive, cycle_time, t->active);
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200129
Bartlomiej Zolnierkiewicz86a0e122008-07-16 20:33:38 +0200130 setup_count = quantize_timing(t->setup,
Bartlomiej Zolnierkiewicz30e5ee42008-07-15 21:21:46 +0200131 1000 / (ide_pci_clk ? ide_pci_clk : 33));
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200132
133 /*
134 * The primary channel has individual address setup timing registers
135 * for each drive and the hardware selects the slowest timing itself.
136 * The secondary channel has one common register and we have to select
137 * the slowest address setup timing ourselves.
138 */
139 if (hwif->channel) {
140 ide_drive_t *drives = hwif->drives;
141
142 drive->drive_data = setup_count;
143 setup_count = max(drives[0].drive_data, drives[1].drive_data);
144 }
145
146 if (setup_count > 5) /* shouldn't actually happen... */
147 setup_count = 5;
148 cmdprintk("Final address setup count: %d\n", setup_count);
149
150 /*
151 * Program the address setup clocks into the ARTTIM registers.
152 * Avoid clearing the secondary channel's interrupt bit.
153 */
154 (void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim);
155 if (hwif->channel)
156 arttim &= ~ARTTIM23_INTR_CH1;
157 arttim &= ~0xc0;
158 arttim |= setup_values[setup_count];
159 (void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
160 cmdprintk("Write 0x%02x to reg 0x%x\n", arttim, arttim_regs[drive->dn]);
Sergei Shtylyovf92d50e62007-03-03 17:48:53 +0100161}
162
163/*
164 * Attempts to set drive's PIO mode.
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200165 * Special cases are 8: prefetch off, 9: prefetch on (both never worked)
Sergei Shtylyovf92d50e62007-03-03 17:48:53 +0100166 */
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200167
168static void cmd64x_set_pio_mode(ide_drive_t *drive, const u8 pio)
Sergei Shtylyovf92d50e62007-03-03 17:48:53 +0100169{
170 /*
171 * Filter out the prefetch control values
172 * to prevent PIO5 from being programmed
173 */
174 if (pio == 8 || pio == 9)
175 return;
176
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200177 cmd64x_tune_pio(drive, pio);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700178}
179
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200180static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700181{
182 ide_hwif_t *hwif = HWIF(drive);
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100183 struct pci_dev *dev = to_pci_dev(hwif->dev);
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200184 u8 unit = drive->dn & 0x01;
185 u8 regU = 0, pciU = hwif->channel ? UDIDETCR1 : UDIDETCR0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700186
Sergei Shtylyovf92d50e62007-03-03 17:48:53 +0100187 if (speed >= XFER_SW_DMA_0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700188 (void) pci_read_config_byte(dev, pciU, &regU);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700189 regU &= ~(unit ? 0xCA : 0x35);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700190 }
191
192 switch(speed) {
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200193 case XFER_UDMA_5:
194 regU |= unit ? 0x0A : 0x05;
195 break;
196 case XFER_UDMA_4:
197 regU |= unit ? 0x4A : 0x15;
198 break;
199 case XFER_UDMA_3:
200 regU |= unit ? 0x8A : 0x25;
201 break;
202 case XFER_UDMA_2:
203 regU |= unit ? 0x42 : 0x11;
204 break;
205 case XFER_UDMA_1:
206 regU |= unit ? 0x82 : 0x21;
207 break;
208 case XFER_UDMA_0:
209 regU |= unit ? 0xC2 : 0x31;
210 break;
211 case XFER_MW_DMA_2:
212 program_cycle_times(drive, 120, 70);
213 break;
214 case XFER_MW_DMA_1:
215 program_cycle_times(drive, 150, 80);
216 break;
217 case XFER_MW_DMA_0:
218 program_cycle_times(drive, 480, 215);
219 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700220 }
221
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200222 if (speed >= XFER_SW_DMA_0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700223 (void) pci_write_config_byte(dev, pciU, regU);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700224}
225
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200226static int cmd648_dma_end(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700227{
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200228 ide_hwif_t *hwif = HWIF(drive);
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100229 unsigned long base = hwif->dma_base - (hwif->channel * 8);
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200230 int err = __ide_dma_end(drive);
231 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
232 MRDMODE_INTR_CH0;
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100233 u8 mrdmode = inb(base + 1);
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200234
235 /* clear the interrupt bit */
Sergei Shtylyov61832892007-11-13 22:09:14 +0100236 outb((mrdmode & ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1)) | irq_mask,
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100237 base + 1);
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200238
239 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700240}
241
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200242static int cmd64x_dma_end(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700243{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700244 ide_hwif_t *hwif = HWIF(drive);
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100245 struct pci_dev *dev = to_pci_dev(hwif->dev);
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200246 int irq_reg = hwif->channel ? ARTTIM23 : CFR;
247 u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
248 CFR_INTR_CH0;
249 u8 irq_stat = 0;
250 int err = __ide_dma_end(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700251
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200252 (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
253 /* clear the interrupt bit */
254 (void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask);
255
256 return err;
257}
258
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200259static int cmd648_dma_test_irq(ide_drive_t *drive)
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200260{
261 ide_hwif_t *hwif = HWIF(drive);
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100262 unsigned long base = hwif->dma_base - (hwif->channel * 8);
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200263 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
264 MRDMODE_INTR_CH0;
265 u8 dma_stat = inb(hwif->dma_status);
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100266 u8 mrdmode = inb(base + 1);
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200267
268#ifdef DEBUG
269 printk("%s: dma_stat: 0x%02x mrdmode: 0x%02x irq_mask: 0x%02x\n",
270 drive->name, dma_stat, mrdmode, irq_mask);
271#endif
272 if (!(mrdmode & irq_mask))
273 return 0;
274
275 /* return 1 if INTR asserted */
276 if (dma_stat & 4)
277 return 1;
278
279 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700280}
281
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200282static int cmd64x_dma_test_irq(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700283{
Sergei Shtylyove51e2522007-05-05 22:03:49 +0200284 ide_hwif_t *hwif = HWIF(drive);
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100285 struct pci_dev *dev = to_pci_dev(hwif->dev);
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200286 int irq_reg = hwif->channel ? ARTTIM23 : CFR;
287 u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
288 CFR_INTR_CH0;
289 u8 dma_stat = inb(hwif->dma_status);
290 u8 irq_stat = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700291
Sergei Shtylyove51e2522007-05-05 22:03:49 +0200292 (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
293
Linus Torvalds1da177e2005-04-16 15:20:36 -0700294#ifdef DEBUG
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200295 printk("%s: dma_stat: 0x%02x irq_stat: 0x%02x irq_mask: 0x%02x\n",
296 drive->name, dma_stat, irq_stat, irq_mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700297#endif
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200298 if (!(irq_stat & irq_mask))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700299 return 0;
300
301 /* return 1 if INTR asserted */
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200302 if (dma_stat & 4)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700303 return 1;
304
305 return 0;
306}
307
308/*
309 * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
310 * event order for DMA transfers.
311 */
312
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200313static int cmd646_1_dma_end(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700314{
315 ide_hwif_t *hwif = HWIF(drive);
316 u8 dma_stat = 0, dma_cmd = 0;
317
318 drive->waiting_for_dma = 0;
319 /* get DMA status */
Bartlomiej Zolnierkiewicz0ecdca22007-02-17 02:40:25 +0100320 dma_stat = inb(hwif->dma_status);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700321 /* read DMA command state */
Bartlomiej Zolnierkiewicz0ecdca22007-02-17 02:40:25 +0100322 dma_cmd = inb(hwif->dma_command);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700323 /* stop DMA */
Bartlomiej Zolnierkiewicz0ecdca22007-02-17 02:40:25 +0100324 outb(dma_cmd & ~1, hwif->dma_command);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700325 /* clear the INTR & ERROR bits */
Bartlomiej Zolnierkiewicz0ecdca22007-02-17 02:40:25 +0100326 outb(dma_stat | 6, hwif->dma_status);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700327 /* and free any DMA resources */
328 ide_destroy_dmatable(drive);
329 /* verify good DMA status */
330 return (dma_stat & 7) != 4;
331}
332
333static unsigned int __devinit init_chipset_cmd64x(struct pci_dev *dev, const char *name)
334{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700335 u8 mrdmode = 0;
336
Sergei Shtylyov83a6d4a2007-07-09 23:17:55 +0200337 if (dev->device == PCI_DEVICE_ID_CMD_646) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700338
Auke Kok1afa6552007-10-19 00:30:08 +0200339 switch (dev->revision) {
Sergei Shtylyov83a6d4a2007-07-09 23:17:55 +0200340 case 0x07:
341 case 0x05:
Meelis Roosb37c6b82007-08-01 23:46:44 +0200342 printk("%s: UltraDMA capable\n", name);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700343 break;
Sergei Shtylyov83a6d4a2007-07-09 23:17:55 +0200344 case 0x03:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700345 default:
Meelis Roosb37c6b82007-08-01 23:46:44 +0200346 printk("%s: MultiWord DMA force limited\n", name);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700347 break;
Sergei Shtylyov83a6d4a2007-07-09 23:17:55 +0200348 case 0x01:
349 printk("%s: MultiWord DMA limited, "
350 "IRQ workaround enabled\n", name);
351 break;
352 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700353 }
354
355 /* Set a good latency timer and cache line size value. */
356 (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
357 /* FIXME: pci_set_master() to ensure a good latency timer value */
358
Sergei Shtylyov83a6d4a2007-07-09 23:17:55 +0200359 /*
360 * Enable interrupts, select MEMORY READ LINE for reads.
361 *
362 * NOTE: although not mentioned in the PCI0646U specs,
363 * bits 0-1 are write only and won't be read back as
364 * set or not -- PCI0646U2 specs clarify this point.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700365 */
Sergei Shtylyov83a6d4a2007-07-09 23:17:55 +0200366 (void) pci_read_config_byte (dev, MRDMODE, &mrdmode);
367 mrdmode &= ~0x30;
368 (void) pci_write_config_byte(dev, MRDMODE, (mrdmode | 0x02));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700369
Linus Torvalds1da177e2005-04-16 15:20:36 -0700370 return 0;
371}
372
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +0200373static u8 __devinit cmd64x_cable_detect(ide_hwif_t *hwif)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700374{
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100375 struct pci_dev *dev = to_pci_dev(hwif->dev);
Sergei Shtylyov83a6d4a2007-07-09 23:17:55 +0200376 u8 bmidecsr = 0, mask = hwif->channel ? 0x02 : 0x01;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700377
Sergei Shtylyov83a6d4a2007-07-09 23:17:55 +0200378 switch (dev->device) {
379 case PCI_DEVICE_ID_CMD_648:
380 case PCI_DEVICE_ID_CMD_649:
381 pci_read_config_byte(dev, BMIDECSR, &bmidecsr);
Bartlomiej Zolnierkiewicz49521f92007-07-09 23:17:58 +0200382 return (bmidecsr & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
Sergei Shtylyov83a6d4a2007-07-09 23:17:55 +0200383 default:
Bartlomiej Zolnierkiewicz49521f92007-07-09 23:17:58 +0200384 return ATA_CBL_PATA40;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700385 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700386}
387
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +0200388static const struct ide_port_ops cmd64x_port_ops = {
389 .set_pio_mode = cmd64x_set_pio_mode,
390 .set_dma_mode = cmd64x_set_dma_mode,
391 .cable_detect = cmd64x_cable_detect,
392};
393
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +0200394static const struct ide_dma_ops cmd64x_dma_ops = {
395 .dma_host_set = ide_dma_host_set,
396 .dma_setup = ide_dma_setup,
397 .dma_exec_cmd = ide_dma_exec_cmd,
398 .dma_start = ide_dma_start,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200399 .dma_end = cmd64x_dma_end,
400 .dma_test_irq = cmd64x_dma_test_irq,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +0200401 .dma_lost_irq = ide_dma_lost_irq,
402 .dma_timeout = ide_dma_timeout,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200403};
404
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +0200405static const struct ide_dma_ops cmd646_rev1_dma_ops = {
406 .dma_host_set = ide_dma_host_set,
407 .dma_setup = ide_dma_setup,
408 .dma_exec_cmd = ide_dma_exec_cmd,
409 .dma_start = ide_dma_start,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200410 .dma_end = cmd646_1_dma_end,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +0200411 .dma_test_irq = ide_dma_test_irq,
412 .dma_lost_irq = ide_dma_lost_irq,
413 .dma_timeout = ide_dma_timeout,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200414};
415
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +0200416static const struct ide_dma_ops cmd648_dma_ops = {
417 .dma_host_set = ide_dma_host_set,
418 .dma_setup = ide_dma_setup,
419 .dma_exec_cmd = ide_dma_exec_cmd,
420 .dma_start = ide_dma_start,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200421 .dma_end = cmd648_dma_end,
422 .dma_test_irq = cmd648_dma_test_irq,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +0200423 .dma_lost_irq = ide_dma_lost_irq,
424 .dma_timeout = ide_dma_timeout,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200425};
426
Bartlomiej Zolnierkiewicz85620432007-10-20 00:32:34 +0200427static const struct ide_port_info cmd64x_chipsets[] __devinitdata = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700428 { /* 0 */
429 .name = "CMD643",
430 .init_chipset = init_chipset_cmd64x,
Sergei Shtylyov7accbff2007-05-05 22:03:49 +0200431 .enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +0200432 .port_ops = &cmd64x_port_ops,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200433 .dma_ops = &cmd64x_dma_ops,
Bartlomiej Zolnierkiewicz8ac2b42a2008-02-01 23:09:30 +0100434 .host_flags = IDE_HFLAG_CLEAR_SIMPLEX |
Bartlomiej Zolnierkiewicz5e71d9c2008-04-26 17:36:35 +0200435 IDE_HFLAG_ABUSE_PREFETCH,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +0200436 .pio_mask = ATA_PIO5,
Bartlomiej Zolnierkiewicz5f8b6c32007-10-19 00:30:07 +0200437 .mwdma_mask = ATA_MWDMA2,
Bartlomiej Zolnierkiewicz18137202007-05-10 00:01:07 +0200438 .udma_mask = 0x00, /* no udma */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700439 },{ /* 1 */
440 .name = "CMD646",
441 .init_chipset = init_chipset_cmd64x,
Sergei Shtylyov7accbff2007-05-05 22:03:49 +0200442 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
Bartlomiej Zolnierkiewiczdeffca12007-12-24 15:23:44 +0100443 .chipset = ide_cmd646,
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +0200444 .port_ops = &cmd64x_port_ops,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200445 .dma_ops = &cmd648_dma_ops,
Bartlomiej Zolnierkiewicz5e71d9c2008-04-26 17:36:35 +0200446 .host_flags = IDE_HFLAG_ABUSE_PREFETCH,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +0200447 .pio_mask = ATA_PIO5,
Bartlomiej Zolnierkiewicz5f8b6c32007-10-19 00:30:07 +0200448 .mwdma_mask = ATA_MWDMA2,
449 .udma_mask = ATA_UDMA2,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700450 },{ /* 2 */
451 .name = "CMD648",
452 .init_chipset = init_chipset_cmd64x,
Sergei Shtylyov7accbff2007-05-05 22:03:49 +0200453 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +0200454 .port_ops = &cmd64x_port_ops,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200455 .dma_ops = &cmd648_dma_ops,
Bartlomiej Zolnierkiewicz5e71d9c2008-04-26 17:36:35 +0200456 .host_flags = IDE_HFLAG_ABUSE_PREFETCH,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +0200457 .pio_mask = ATA_PIO5,
Bartlomiej Zolnierkiewicz5f8b6c32007-10-19 00:30:07 +0200458 .mwdma_mask = ATA_MWDMA2,
459 .udma_mask = ATA_UDMA4,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700460 },{ /* 3 */
461 .name = "CMD649",
462 .init_chipset = init_chipset_cmd64x,
Sergei Shtylyov7accbff2007-05-05 22:03:49 +0200463 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +0200464 .port_ops = &cmd64x_port_ops,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200465 .dma_ops = &cmd648_dma_ops,
Bartlomiej Zolnierkiewicz5e71d9c2008-04-26 17:36:35 +0200466 .host_flags = IDE_HFLAG_ABUSE_PREFETCH,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +0200467 .pio_mask = ATA_PIO5,
Bartlomiej Zolnierkiewicz5f8b6c32007-10-19 00:30:07 +0200468 .mwdma_mask = ATA_MWDMA2,
469 .udma_mask = ATA_UDMA5,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700470 }
471};
472
473static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
474{
Bartlomiej Zolnierkiewicz039788e2007-10-20 00:32:34 +0200475 struct ide_port_info d;
Bartlomiej Zolnierkiewiczbfd314a2007-10-19 00:30:09 +0200476 u8 idx = id->driver_data;
Sergei Shtylyov7accbff2007-05-05 22:03:49 +0200477
Bartlomiej Zolnierkiewiczbfd314a2007-10-19 00:30:09 +0200478 d = cmd64x_chipsets[idx];
479
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200480 if (idx == 1) {
481 /*
482 * UltraDMA only supported on PCI646U and PCI646U2, which
483 * correspond to revisions 0x03, 0x05 and 0x07 respectively.
484 * Actually, although the CMD tech support people won't
485 * tell me the details, the 0x03 revision cannot support
486 * UDMA correctly without hardware modifications, and even
487 * then it only works with Quantum disks due to some
488 * hold time assumptions in the 646U part which are fixed
489 * in the 646U2.
490 *
491 * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
492 */
493 if (dev->revision < 5) {
494 d.udma_mask = 0x00;
495 /*
496 * The original PCI0646 didn't have the primary
497 * channel enable bit, it appeared starting with
498 * PCI0646U (i.e. revision ID 3).
499 */
500 if (dev->revision < 3) {
501 d.enablebits[0].reg = 0;
502 if (dev->revision == 1)
503 d.dma_ops = &cmd646_rev1_dma_ops;
504 else
505 d.dma_ops = &cmd64x_dma_ops;
506 }
507 }
508 }
Bartlomiej Zolnierkiewiczbfd314a2007-10-19 00:30:09 +0200509
510 return ide_setup_pci_device(dev, &d);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700511}
512
Bartlomiej Zolnierkiewicz9cbcc5e2007-10-16 22:29:56 +0200513static const struct pci_device_id cmd64x_pci_tbl[] = {
514 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
515 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
516 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 2 },
517 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 3 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700518 { 0, },
519};
520MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl);
521
522static struct pci_driver driver = {
523 .name = "CMD64x_IDE",
524 .id_table = cmd64x_pci_tbl,
525 .probe = cmd64x_init_one,
526};
527
Bartlomiej Zolnierkiewicz82ab1ee2007-01-27 13:46:56 +0100528static int __init cmd64x_ide_init(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700529{
530 return ide_pci_register_driver(&driver);
531}
532
533module_init(cmd64x_ide_init);
534
535MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick");
536MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
537MODULE_LICENSE("GPL");