Hemant Kumar | 8e4c2f2 | 2017-01-24 18:13:07 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved. |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | */ |
| 13 | |
| 14 | #include <linux/module.h> |
| 15 | #include <linux/kernel.h> |
| 16 | #include <linux/slab.h> |
| 17 | #include <linux/cpu.h> |
| 18 | #include <linux/platform_device.h> |
| 19 | #include <linux/dma-mapping.h> |
| 20 | #include <linux/dmapool.h> |
| 21 | #include <linux/pm_runtime.h> |
| 22 | #include <linux/ratelimit.h> |
| 23 | #include <linux/interrupt.h> |
| 24 | #include <linux/ioport.h> |
| 25 | #include <linux/clk.h> |
| 26 | #include <linux/io.h> |
| 27 | #include <linux/module.h> |
| 28 | #include <linux/types.h> |
| 29 | #include <linux/delay.h> |
| 30 | #include <linux/of.h> |
| 31 | #include <linux/of_platform.h> |
| 32 | #include <linux/of_gpio.h> |
| 33 | #include <linux/list.h> |
| 34 | #include <linux/uaccess.h> |
| 35 | #include <linux/usb/ch9.h> |
| 36 | #include <linux/usb/gadget.h> |
| 37 | #include <linux/usb/of.h> |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 38 | #include <linux/regulator/consumer.h> |
| 39 | #include <linux/pm_wakeup.h> |
| 40 | #include <linux/power_supply.h> |
| 41 | #include <linux/cdev.h> |
| 42 | #include <linux/completion.h> |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 43 | #include <linux/msm-bus.h> |
| 44 | #include <linux/irq.h> |
| 45 | #include <linux/extcon.h> |
Amit Nischal | 4d27821 | 2016-06-06 17:54:34 +0530 | [diff] [blame] | 46 | #include <linux/reset.h> |
Hemant Kumar | 633dc33 | 2016-08-10 13:41:05 -0700 | [diff] [blame] | 47 | #include <linux/clk/qcom.h> |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 48 | |
| 49 | #include "power.h" |
| 50 | #include "core.h" |
| 51 | #include "gadget.h" |
| 52 | #include "dbm.h" |
| 53 | #include "debug.h" |
| 54 | #include "xhci.h" |
| 55 | |
| 56 | /* time out to wait for USB cable status notification (in ms)*/ |
| 57 | #define SM_INIT_TIMEOUT 30000 |
| 58 | |
| 59 | /* AHB2PHY register offsets */ |
| 60 | #define PERIPH_SS_AHB2PHY_TOP_CFG 0x10 |
| 61 | |
| 62 | /* AHB2PHY read/write waite value */ |
| 63 | #define ONE_READ_WRITE_WAIT 0x11 |
| 64 | |
| 65 | /* cpu to fix usb interrupt */ |
| 66 | static int cpu_to_affin; |
| 67 | module_param(cpu_to_affin, int, S_IRUGO|S_IWUSR); |
| 68 | MODULE_PARM_DESC(cpu_to_affin, "affin usb irq to this cpu"); |
| 69 | |
| 70 | /* XHCI registers */ |
| 71 | #define USB3_HCSPARAMS1 (0x4) |
| 72 | #define USB3_PORTSC (0x420) |
| 73 | |
| 74 | /** |
| 75 | * USB QSCRATCH Hardware registers |
| 76 | * |
| 77 | */ |
| 78 | #define QSCRATCH_REG_OFFSET (0x000F8800) |
| 79 | #define QSCRATCH_GENERAL_CFG (QSCRATCH_REG_OFFSET + 0x08) |
| 80 | #define CGCTL_REG (QSCRATCH_REG_OFFSET + 0x28) |
| 81 | #define PWR_EVNT_IRQ_STAT_REG (QSCRATCH_REG_OFFSET + 0x58) |
| 82 | #define PWR_EVNT_IRQ_MASK_REG (QSCRATCH_REG_OFFSET + 0x5C) |
| 83 | |
| 84 | #define PWR_EVNT_POWERDOWN_IN_P3_MASK BIT(2) |
| 85 | #define PWR_EVNT_POWERDOWN_OUT_P3_MASK BIT(3) |
| 86 | #define PWR_EVNT_LPM_IN_L2_MASK BIT(4) |
| 87 | #define PWR_EVNT_LPM_OUT_L2_MASK BIT(5) |
| 88 | #define PWR_EVNT_LPM_OUT_L1_MASK BIT(13) |
| 89 | |
| 90 | /* QSCRATCH_GENERAL_CFG register bit offset */ |
| 91 | #define PIPE_UTMI_CLK_SEL BIT(0) |
| 92 | #define PIPE3_PHYSTATUS_SW BIT(3) |
| 93 | #define PIPE_UTMI_CLK_DIS BIT(8) |
| 94 | |
| 95 | #define HS_PHY_CTRL_REG (QSCRATCH_REG_OFFSET + 0x10) |
| 96 | #define UTMI_OTG_VBUS_VALID BIT(20) |
| 97 | #define SW_SESSVLD_SEL BIT(28) |
| 98 | |
| 99 | #define SS_PHY_CTRL_REG (QSCRATCH_REG_OFFSET + 0x30) |
| 100 | #define LANE0_PWR_PRESENT BIT(24) |
| 101 | |
| 102 | /* GSI related registers */ |
| 103 | #define GSI_TRB_ADDR_BIT_53_MASK (1 << 21) |
| 104 | #define GSI_TRB_ADDR_BIT_55_MASK (1 << 23) |
| 105 | |
| 106 | #define GSI_GENERAL_CFG_REG (QSCRATCH_REG_OFFSET + 0xFC) |
| 107 | #define GSI_RESTART_DBL_PNTR_MASK BIT(20) |
| 108 | #define GSI_CLK_EN_MASK BIT(12) |
| 109 | #define BLOCK_GSI_WR_GO_MASK BIT(1) |
| 110 | #define GSI_EN_MASK BIT(0) |
| 111 | |
| 112 | #define GSI_DBL_ADDR_L(n) ((QSCRATCH_REG_OFFSET + 0x110) + (n*4)) |
| 113 | #define GSI_DBL_ADDR_H(n) ((QSCRATCH_REG_OFFSET + 0x120) + (n*4)) |
| 114 | #define GSI_RING_BASE_ADDR_L(n) ((QSCRATCH_REG_OFFSET + 0x130) + (n*4)) |
| 115 | #define GSI_RING_BASE_ADDR_H(n) ((QSCRATCH_REG_OFFSET + 0x140) + (n*4)) |
| 116 | |
| 117 | #define GSI_IF_STS (QSCRATCH_REG_OFFSET + 0x1A4) |
| 118 | #define GSI_WR_CTRL_STATE_MASK BIT(15) |
| 119 | |
Mayank Rana | f4918d3 | 2016-12-15 13:35:55 -0800 | [diff] [blame] | 120 | #define DWC3_GEVNTCOUNT_EVNTINTRPTMASK (1 << 31) |
| 121 | #define DWC3_GEVNTADRHI_EVNTADRHI_GSI_EN(n) (n << 22) |
| 122 | #define DWC3_GEVNTADRHI_EVNTADRHI_GSI_IDX(n) (n << 16) |
| 123 | #define DWC3_GEVENT_TYPE_GSI 0x3 |
| 124 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 125 | struct dwc3_msm_req_complete { |
| 126 | struct list_head list_item; |
| 127 | struct usb_request *req; |
| 128 | void (*orig_complete)(struct usb_ep *ep, |
| 129 | struct usb_request *req); |
| 130 | }; |
| 131 | |
| 132 | enum dwc3_id_state { |
| 133 | DWC3_ID_GROUND = 0, |
| 134 | DWC3_ID_FLOAT, |
| 135 | }; |
| 136 | |
| 137 | /* for type c cable */ |
| 138 | enum plug_orientation { |
| 139 | ORIENTATION_NONE, |
| 140 | ORIENTATION_CC1, |
| 141 | ORIENTATION_CC2, |
| 142 | }; |
| 143 | |
| 144 | /* Input bits to state machine (mdwc->inputs) */ |
| 145 | |
| 146 | #define ID 0 |
| 147 | #define B_SESS_VLD 1 |
| 148 | #define B_SUSPEND 2 |
| 149 | |
| 150 | struct dwc3_msm { |
| 151 | struct device *dev; |
| 152 | void __iomem *base; |
| 153 | void __iomem *ahb2phy_base; |
| 154 | struct platform_device *dwc3; |
| 155 | const struct usb_ep_ops *original_ep_ops[DWC3_ENDPOINTS_NUM]; |
| 156 | struct list_head req_complete_list; |
| 157 | struct clk *xo_clk; |
| 158 | struct clk *core_clk; |
| 159 | long core_clk_rate; |
Hemant Kumar | 8e4c2f2 | 2017-01-24 18:13:07 -0800 | [diff] [blame] | 160 | long core_clk_rate_hs; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 161 | struct clk *iface_clk; |
| 162 | struct clk *sleep_clk; |
| 163 | struct clk *utmi_clk; |
| 164 | unsigned int utmi_clk_rate; |
| 165 | struct clk *utmi_clk_src; |
| 166 | struct clk *bus_aggr_clk; |
Vijayavardhan Vennapusa | 934d9cd | 2016-11-30 13:10:01 +0530 | [diff] [blame] | 167 | struct clk *noc_aggr_clk; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 168 | struct clk *cfg_ahb_clk; |
Amit Nischal | 4d27821 | 2016-06-06 17:54:34 +0530 | [diff] [blame] | 169 | struct reset_control *core_reset; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 170 | struct regulator *dwc3_gdsc; |
| 171 | |
| 172 | struct usb_phy *hs_phy, *ss_phy; |
| 173 | |
| 174 | struct dbm *dbm; |
| 175 | |
| 176 | /* VBUS regulator for host mode */ |
| 177 | struct regulator *vbus_reg; |
| 178 | int vbus_retry_count; |
| 179 | bool resume_pending; |
| 180 | atomic_t pm_suspended; |
| 181 | int hs_phy_irq; |
| 182 | int ss_phy_irq; |
| 183 | struct work_struct resume_work; |
| 184 | struct work_struct restart_usb_work; |
| 185 | bool in_restart; |
| 186 | struct workqueue_struct *dwc3_wq; |
| 187 | struct delayed_work sm_work; |
| 188 | unsigned long inputs; |
| 189 | unsigned int max_power; |
| 190 | bool charging_disabled; |
| 191 | enum usb_otg_state otg_state; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 192 | struct work_struct bus_vote_w; |
| 193 | unsigned int bus_vote; |
| 194 | u32 bus_perf_client; |
| 195 | struct msm_bus_scale_pdata *bus_scale_table; |
| 196 | struct power_supply *usb_psy; |
Jack Pham | 4b8b4ae | 2016-08-09 11:36:34 -0700 | [diff] [blame] | 197 | struct work_struct vbus_draw_work; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 198 | bool in_host_mode; |
Hemant Kumar | 8e4c2f2 | 2017-01-24 18:13:07 -0800 | [diff] [blame] | 199 | enum usb_device_speed max_rh_port_speed; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 200 | unsigned int tx_fifo_size; |
| 201 | bool vbus_active; |
| 202 | bool suspend; |
| 203 | bool disable_host_mode_pm; |
| 204 | enum dwc3_id_state id_state; |
| 205 | unsigned long lpm_flags; |
| 206 | #define MDWC3_SS_PHY_SUSPEND BIT(0) |
| 207 | #define MDWC3_ASYNC_IRQ_WAKE_CAPABILITY BIT(1) |
| 208 | #define MDWC3_POWER_COLLAPSE BIT(2) |
| 209 | |
| 210 | unsigned int irq_to_affin; |
| 211 | struct notifier_block dwc3_cpu_notifier; |
| 212 | |
| 213 | struct extcon_dev *extcon_vbus; |
| 214 | struct extcon_dev *extcon_id; |
| 215 | struct notifier_block vbus_nb; |
| 216 | struct notifier_block id_nb; |
| 217 | |
Jack Pham | 4d4e934 | 2016-12-07 19:25:02 -0800 | [diff] [blame] | 218 | struct notifier_block host_nb; |
| 219 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 220 | int pwr_event_irq; |
| 221 | atomic_t in_p3; |
| 222 | unsigned int lpm_to_suspend_delay; |
| 223 | bool init; |
| 224 | enum plug_orientation typec_orientation; |
Mayank Rana | f4918d3 | 2016-12-15 13:35:55 -0800 | [diff] [blame] | 225 | u32 num_gsi_event_buffers; |
| 226 | struct dwc3_event_buffer **gsi_ev_buff; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 227 | }; |
| 228 | |
| 229 | #define USB_HSPHY_3P3_VOL_MIN 3050000 /* uV */ |
| 230 | #define USB_HSPHY_3P3_VOL_MAX 3300000 /* uV */ |
| 231 | #define USB_HSPHY_3P3_HPM_LOAD 16000 /* uA */ |
| 232 | |
| 233 | #define USB_HSPHY_1P8_VOL_MIN 1800000 /* uV */ |
| 234 | #define USB_HSPHY_1P8_VOL_MAX 1800000 /* uV */ |
| 235 | #define USB_HSPHY_1P8_HPM_LOAD 19000 /* uA */ |
| 236 | |
| 237 | #define USB_SSPHY_1P8_VOL_MIN 1800000 /* uV */ |
| 238 | #define USB_SSPHY_1P8_VOL_MAX 1800000 /* uV */ |
| 239 | #define USB_SSPHY_1P8_HPM_LOAD 23000 /* uA */ |
| 240 | |
| 241 | #define DSTS_CONNECTSPD_SS 0x4 |
| 242 | |
| 243 | |
| 244 | static void dwc3_pwr_event_handler(struct dwc3_msm *mdwc); |
| 245 | static int dwc3_msm_gadget_vbus_draw(struct dwc3_msm *mdwc, unsigned int mA); |
Mayank Rana | f4918d3 | 2016-12-15 13:35:55 -0800 | [diff] [blame] | 246 | static void dwc3_msm_notify_event(struct dwc3 *dwc, unsigned int event); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 247 | /** |
| 248 | * |
| 249 | * Read register with debug info. |
| 250 | * |
| 251 | * @base - DWC3 base virtual address. |
| 252 | * @offset - register offset. |
| 253 | * |
| 254 | * @return u32 |
| 255 | */ |
| 256 | static inline u32 dwc3_msm_read_reg(void *base, u32 offset) |
| 257 | { |
| 258 | u32 val = ioread32(base + offset); |
| 259 | return val; |
| 260 | } |
| 261 | |
| 262 | /** |
| 263 | * Read register masked field with debug info. |
| 264 | * |
| 265 | * @base - DWC3 base virtual address. |
| 266 | * @offset - register offset. |
| 267 | * @mask - register bitmask. |
| 268 | * |
| 269 | * @return u32 |
| 270 | */ |
| 271 | static inline u32 dwc3_msm_read_reg_field(void *base, |
| 272 | u32 offset, |
| 273 | const u32 mask) |
| 274 | { |
| 275 | u32 shift = find_first_bit((void *)&mask, 32); |
| 276 | u32 val = ioread32(base + offset); |
| 277 | |
| 278 | val &= mask; /* clear other bits */ |
| 279 | val >>= shift; |
| 280 | return val; |
| 281 | } |
| 282 | |
| 283 | /** |
| 284 | * |
| 285 | * Write register with debug info. |
| 286 | * |
| 287 | * @base - DWC3 base virtual address. |
| 288 | * @offset - register offset. |
| 289 | * @val - value to write. |
| 290 | * |
| 291 | */ |
| 292 | static inline void dwc3_msm_write_reg(void *base, u32 offset, u32 val) |
| 293 | { |
| 294 | iowrite32(val, base + offset); |
| 295 | } |
| 296 | |
| 297 | /** |
| 298 | * Write register masked field with debug info. |
| 299 | * |
| 300 | * @base - DWC3 base virtual address. |
| 301 | * @offset - register offset. |
| 302 | * @mask - register bitmask. |
| 303 | * @val - value to write. |
| 304 | * |
| 305 | */ |
| 306 | static inline void dwc3_msm_write_reg_field(void *base, u32 offset, |
| 307 | const u32 mask, u32 val) |
| 308 | { |
| 309 | u32 shift = find_first_bit((void *)&mask, 32); |
| 310 | u32 tmp = ioread32(base + offset); |
| 311 | |
| 312 | tmp &= ~mask; /* clear written bits */ |
| 313 | val = tmp | (val << shift); |
| 314 | iowrite32(val, base + offset); |
| 315 | } |
| 316 | |
| 317 | /** |
| 318 | * Write register and read back masked value to confirm it is written |
| 319 | * |
| 320 | * @base - DWC3 base virtual address. |
| 321 | * @offset - register offset. |
| 322 | * @mask - register bitmask specifying what should be updated |
| 323 | * @val - value to write. |
| 324 | * |
| 325 | */ |
| 326 | static inline void dwc3_msm_write_readback(void *base, u32 offset, |
| 327 | const u32 mask, u32 val) |
| 328 | { |
| 329 | u32 write_val, tmp = ioread32(base + offset); |
| 330 | |
| 331 | tmp &= ~mask; /* retain other bits */ |
| 332 | write_val = tmp | val; |
| 333 | |
| 334 | iowrite32(write_val, base + offset); |
| 335 | |
| 336 | /* Read back to see if val was written */ |
| 337 | tmp = ioread32(base + offset); |
| 338 | tmp &= mask; /* clear other bits */ |
| 339 | |
| 340 | if (tmp != val) |
| 341 | pr_err("%s: write: %x to QSCRATCH: %x FAILED\n", |
| 342 | __func__, val, offset); |
| 343 | } |
| 344 | |
Hemant Kumar | 8e4c2f2 | 2017-01-24 18:13:07 -0800 | [diff] [blame] | 345 | static bool dwc3_msm_is_ss_rhport_connected(struct dwc3_msm *mdwc) |
| 346 | { |
| 347 | int i, num_ports; |
| 348 | u32 reg; |
| 349 | |
| 350 | reg = dwc3_msm_read_reg(mdwc->base, USB3_HCSPARAMS1); |
| 351 | num_ports = HCS_MAX_PORTS(reg); |
| 352 | |
| 353 | for (i = 0; i < num_ports; i++) { |
| 354 | reg = dwc3_msm_read_reg(mdwc->base, USB3_PORTSC + i*0x10); |
| 355 | if ((reg & PORT_CONNECT) && DEV_SUPERSPEED(reg)) |
| 356 | return true; |
| 357 | } |
| 358 | |
| 359 | return false; |
| 360 | } |
| 361 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 362 | static bool dwc3_msm_is_host_superspeed(struct dwc3_msm *mdwc) |
| 363 | { |
| 364 | int i, num_ports; |
| 365 | u32 reg; |
| 366 | |
| 367 | reg = dwc3_msm_read_reg(mdwc->base, USB3_HCSPARAMS1); |
| 368 | num_ports = HCS_MAX_PORTS(reg); |
| 369 | |
| 370 | for (i = 0; i < num_ports; i++) { |
| 371 | reg = dwc3_msm_read_reg(mdwc->base, USB3_PORTSC + i*0x10); |
| 372 | if ((reg & PORT_PE) && DEV_SUPERSPEED(reg)) |
| 373 | return true; |
| 374 | } |
| 375 | |
| 376 | return false; |
| 377 | } |
| 378 | |
| 379 | static inline bool dwc3_msm_is_dev_superspeed(struct dwc3_msm *mdwc) |
| 380 | { |
| 381 | u8 speed; |
| 382 | |
| 383 | speed = dwc3_msm_read_reg(mdwc->base, DWC3_DSTS) & DWC3_DSTS_CONNECTSPD; |
| 384 | return !!(speed & DSTS_CONNECTSPD_SS); |
| 385 | } |
| 386 | |
| 387 | static inline bool dwc3_msm_is_superspeed(struct dwc3_msm *mdwc) |
| 388 | { |
| 389 | if (mdwc->in_host_mode) |
| 390 | return dwc3_msm_is_host_superspeed(mdwc); |
| 391 | |
| 392 | return dwc3_msm_is_dev_superspeed(mdwc); |
| 393 | } |
| 394 | |
| 395 | #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) |
| 396 | /** |
| 397 | * Configure the DBM with the BAM's data fifo. |
| 398 | * This function is called by the USB BAM Driver |
| 399 | * upon initialization. |
| 400 | * |
| 401 | * @ep - pointer to usb endpoint. |
| 402 | * @addr - address of data fifo. |
| 403 | * @size - size of data fifo. |
| 404 | * |
| 405 | */ |
| 406 | int msm_data_fifo_config(struct usb_ep *ep, phys_addr_t addr, |
| 407 | u32 size, u8 dst_pipe_idx) |
| 408 | { |
| 409 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 410 | struct dwc3 *dwc = dep->dwc; |
| 411 | struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent); |
| 412 | |
| 413 | dev_dbg(mdwc->dev, "%s\n", __func__); |
| 414 | |
| 415 | return dbm_data_fifo_config(mdwc->dbm, dep->number, addr, size, |
| 416 | dst_pipe_idx); |
| 417 | } |
| 418 | |
| 419 | |
| 420 | /** |
| 421 | * Cleanups for msm endpoint on request complete. |
| 422 | * |
| 423 | * Also call original request complete. |
| 424 | * |
| 425 | * @usb_ep - pointer to usb_ep instance. |
| 426 | * @request - pointer to usb_request instance. |
| 427 | * |
| 428 | * @return int - 0 on success, negative on error. |
| 429 | */ |
| 430 | static void dwc3_msm_req_complete_func(struct usb_ep *ep, |
| 431 | struct usb_request *request) |
| 432 | { |
| 433 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 434 | struct dwc3 *dwc = dep->dwc; |
| 435 | struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent); |
| 436 | struct dwc3_msm_req_complete *req_complete = NULL; |
| 437 | |
| 438 | /* Find original request complete function and remove it from list */ |
| 439 | list_for_each_entry(req_complete, &mdwc->req_complete_list, list_item) { |
| 440 | if (req_complete->req == request) |
| 441 | break; |
| 442 | } |
| 443 | if (!req_complete || req_complete->req != request) { |
| 444 | dev_err(dep->dwc->dev, "%s: could not find the request\n", |
| 445 | __func__); |
| 446 | return; |
| 447 | } |
| 448 | list_del(&req_complete->list_item); |
| 449 | |
| 450 | /* |
| 451 | * Release another one TRB to the pool since DBM queue took 2 TRBs |
| 452 | * (normal and link), and the dwc3/gadget.c :: dwc3_gadget_giveback |
| 453 | * released only one. |
| 454 | */ |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 455 | dep->trb_dequeue++; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 456 | |
| 457 | /* Unconfigure dbm ep */ |
| 458 | dbm_ep_unconfig(mdwc->dbm, dep->number); |
| 459 | |
| 460 | /* |
| 461 | * If this is the last endpoint we unconfigured, than reset also |
| 462 | * the event buffers; unless unconfiguring the ep due to lpm, |
| 463 | * in which case the event buffer only gets reset during the |
| 464 | * block reset. |
| 465 | */ |
| 466 | if (dbm_get_num_of_eps_configured(mdwc->dbm) == 0 && |
| 467 | !dbm_reset_ep_after_lpm(mdwc->dbm)) |
| 468 | dbm_event_buffer_config(mdwc->dbm, 0, 0, 0); |
| 469 | |
| 470 | /* |
| 471 | * Call original complete function, notice that dwc->lock is already |
| 472 | * taken by the caller of this function (dwc3_gadget_giveback()). |
| 473 | */ |
| 474 | request->complete = req_complete->orig_complete; |
| 475 | if (request->complete) |
| 476 | request->complete(ep, request); |
| 477 | |
| 478 | kfree(req_complete); |
| 479 | } |
| 480 | |
| 481 | |
| 482 | /** |
| 483 | * Helper function |
| 484 | * |
| 485 | * Reset DBM endpoint. |
| 486 | * |
| 487 | * @mdwc - pointer to dwc3_msm instance. |
| 488 | * @dep - pointer to dwc3_ep instance. |
| 489 | * |
| 490 | * @return int - 0 on success, negative on error. |
| 491 | */ |
| 492 | static int __dwc3_msm_dbm_ep_reset(struct dwc3_msm *mdwc, struct dwc3_ep *dep) |
| 493 | { |
| 494 | int ret; |
| 495 | |
| 496 | dev_dbg(mdwc->dev, "Resetting dbm endpoint %d\n", dep->number); |
| 497 | |
| 498 | /* Reset the dbm endpoint */ |
| 499 | ret = dbm_ep_soft_reset(mdwc->dbm, dep->number, true); |
| 500 | if (ret) { |
| 501 | dev_err(mdwc->dev, "%s: failed to assert dbm ep reset\n", |
| 502 | __func__); |
| 503 | return ret; |
| 504 | } |
| 505 | |
| 506 | /* |
| 507 | * The necessary delay between asserting and deasserting the dbm ep |
| 508 | * reset is based on the number of active endpoints. If there is more |
| 509 | * than one endpoint, a 1 msec delay is required. Otherwise, a shorter |
| 510 | * delay will suffice. |
| 511 | */ |
| 512 | if (dbm_get_num_of_eps_configured(mdwc->dbm) > 1) |
| 513 | usleep_range(1000, 1200); |
| 514 | else |
| 515 | udelay(10); |
| 516 | ret = dbm_ep_soft_reset(mdwc->dbm, dep->number, false); |
| 517 | if (ret) { |
| 518 | dev_err(mdwc->dev, "%s: failed to deassert dbm ep reset\n", |
| 519 | __func__); |
| 520 | return ret; |
| 521 | } |
| 522 | |
| 523 | return 0; |
| 524 | } |
| 525 | |
| 526 | /** |
| 527 | * Reset the DBM endpoint which is linked to the given USB endpoint. |
| 528 | * |
| 529 | * @usb_ep - pointer to usb_ep instance. |
| 530 | * |
| 531 | * @return int - 0 on success, negative on error. |
| 532 | */ |
| 533 | |
| 534 | int msm_dwc3_reset_dbm_ep(struct usb_ep *ep) |
| 535 | { |
| 536 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 537 | struct dwc3 *dwc = dep->dwc; |
| 538 | struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent); |
| 539 | |
| 540 | return __dwc3_msm_dbm_ep_reset(mdwc, dep); |
| 541 | } |
| 542 | EXPORT_SYMBOL(msm_dwc3_reset_dbm_ep); |
| 543 | |
| 544 | |
| 545 | /** |
| 546 | * Helper function. |
| 547 | * See the header of the dwc3_msm_ep_queue function. |
| 548 | * |
| 549 | * @dwc3_ep - pointer to dwc3_ep instance. |
| 550 | * @req - pointer to dwc3_request instance. |
| 551 | * |
| 552 | * @return int - 0 on success, negative on error. |
| 553 | */ |
| 554 | static int __dwc3_msm_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) |
| 555 | { |
| 556 | struct dwc3_trb *trb; |
| 557 | struct dwc3_trb *trb_link; |
| 558 | struct dwc3_gadget_ep_cmd_params params; |
| 559 | u32 cmd; |
| 560 | int ret = 0; |
| 561 | |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 562 | /* We push the request to the dep->started_list list to indicate that |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 563 | * this request is issued with start transfer. The request will be out |
| 564 | * from this list in 2 cases. The first is that the transfer will be |
| 565 | * completed (not if the transfer is endless using a circular TRBs with |
| 566 | * with link TRB). The second case is an option to do stop stransfer, |
| 567 | * this can be initiated by the function driver when calling dequeue. |
| 568 | */ |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 569 | req->started = true; |
| 570 | list_add_tail(&req->list, &dep->started_list); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 571 | |
| 572 | /* First, prepare a normal TRB, point to the fake buffer */ |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 573 | trb = &dep->trb_pool[dep->trb_enqueue & DWC3_TRB_NUM]; |
| 574 | dep->trb_enqueue++; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 575 | memset(trb, 0, sizeof(*trb)); |
| 576 | |
| 577 | req->trb = trb; |
| 578 | trb->bph = DBM_TRB_BIT | DBM_TRB_DMA | DBM_TRB_EP_NUM(dep->number); |
| 579 | trb->size = DWC3_TRB_SIZE_LENGTH(req->request.length); |
| 580 | trb->ctrl = DWC3_TRBCTL_NORMAL | DWC3_TRB_CTRL_HWO | |
| 581 | DWC3_TRB_CTRL_CHN | (req->direction ? 0 : DWC3_TRB_CTRL_CSP); |
| 582 | req->trb_dma = dwc3_trb_dma_offset(dep, trb); |
| 583 | |
| 584 | /* Second, prepare a Link TRB that points to the first TRB*/ |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 585 | trb_link = &dep->trb_pool[dep->trb_enqueue & DWC3_TRB_NUM]; |
| 586 | dep->trb_enqueue++; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 587 | memset(trb_link, 0, sizeof(*trb_link)); |
| 588 | |
| 589 | trb_link->bpl = lower_32_bits(req->trb_dma); |
| 590 | trb_link->bph = DBM_TRB_BIT | |
| 591 | DBM_TRB_DMA | DBM_TRB_EP_NUM(dep->number); |
| 592 | trb_link->size = 0; |
| 593 | trb_link->ctrl = DWC3_TRBCTL_LINK_TRB | DWC3_TRB_CTRL_HWO; |
| 594 | |
| 595 | /* |
| 596 | * Now start the transfer |
| 597 | */ |
| 598 | memset(¶ms, 0, sizeof(params)); |
| 599 | params.param0 = 0; /* TDAddr High */ |
| 600 | params.param1 = lower_32_bits(req->trb_dma); /* DAddr Low */ |
| 601 | |
| 602 | /* DBM requires IOC to be set */ |
| 603 | cmd = DWC3_DEPCMD_STARTTRANSFER | DWC3_DEPCMD_CMDIOC; |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 604 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 605 | if (ret < 0) { |
| 606 | dev_dbg(dep->dwc->dev, |
| 607 | "%s: failed to send STARTTRANSFER command\n", |
| 608 | __func__); |
| 609 | |
| 610 | list_del(&req->list); |
| 611 | return ret; |
| 612 | } |
| 613 | dep->flags |= DWC3_EP_BUSY; |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 614 | dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 615 | |
| 616 | return ret; |
| 617 | } |
| 618 | |
| 619 | /** |
| 620 | * Queue a usb request to the DBM endpoint. |
| 621 | * This function should be called after the endpoint |
| 622 | * was enabled by the ep_enable. |
| 623 | * |
| 624 | * This function prepares special structure of TRBs which |
| 625 | * is familiar with the DBM HW, so it will possible to use |
| 626 | * this endpoint in DBM mode. |
| 627 | * |
| 628 | * The TRBs prepared by this function, is one normal TRB |
| 629 | * which point to a fake buffer, followed by a link TRB |
| 630 | * that points to the first TRB. |
| 631 | * |
| 632 | * The API of this function follow the regular API of |
| 633 | * usb_ep_queue (see usb_ep_ops in include/linuk/usb/gadget.h). |
| 634 | * |
| 635 | * @usb_ep - pointer to usb_ep instance. |
| 636 | * @request - pointer to usb_request instance. |
| 637 | * @gfp_flags - possible flags. |
| 638 | * |
| 639 | * @return int - 0 on success, negative on error. |
| 640 | */ |
| 641 | static int dwc3_msm_ep_queue(struct usb_ep *ep, |
| 642 | struct usb_request *request, gfp_t gfp_flags) |
| 643 | { |
| 644 | struct dwc3_request *req = to_dwc3_request(request); |
| 645 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 646 | struct dwc3 *dwc = dep->dwc; |
| 647 | struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent); |
| 648 | struct dwc3_msm_req_complete *req_complete; |
| 649 | unsigned long flags; |
| 650 | int ret = 0, size; |
| 651 | u8 bam_pipe; |
| 652 | bool producer; |
| 653 | bool disable_wb; |
| 654 | bool internal_mem; |
| 655 | bool ioc; |
| 656 | bool superspeed; |
| 657 | |
| 658 | if (!(request->udc_priv & MSM_SPS_MODE)) { |
| 659 | /* Not SPS mode, call original queue */ |
| 660 | dev_vdbg(mdwc->dev, "%s: not sps mode, use regular queue\n", |
| 661 | __func__); |
| 662 | |
| 663 | return (mdwc->original_ep_ops[dep->number])->queue(ep, |
| 664 | request, |
| 665 | gfp_flags); |
| 666 | } |
| 667 | |
| 668 | /* HW restriction regarding TRB size (8KB) */ |
| 669 | if (req->request.length < 0x2000) { |
| 670 | dev_err(mdwc->dev, "%s: Min TRB size is 8KB\n", __func__); |
| 671 | return -EINVAL; |
| 672 | } |
| 673 | |
| 674 | /* |
| 675 | * Override req->complete function, but before doing that, |
| 676 | * store it's original pointer in the req_complete_list. |
| 677 | */ |
| 678 | req_complete = kzalloc(sizeof(*req_complete), gfp_flags); |
| 679 | if (!req_complete) |
| 680 | return -ENOMEM; |
| 681 | |
| 682 | req_complete->req = request; |
| 683 | req_complete->orig_complete = request->complete; |
| 684 | list_add_tail(&req_complete->list_item, &mdwc->req_complete_list); |
| 685 | request->complete = dwc3_msm_req_complete_func; |
| 686 | |
| 687 | /* |
| 688 | * Configure the DBM endpoint |
| 689 | */ |
| 690 | bam_pipe = request->udc_priv & MSM_PIPE_ID_MASK; |
| 691 | producer = ((request->udc_priv & MSM_PRODUCER) ? true : false); |
| 692 | disable_wb = ((request->udc_priv & MSM_DISABLE_WB) ? true : false); |
| 693 | internal_mem = ((request->udc_priv & MSM_INTERNAL_MEM) ? true : false); |
| 694 | ioc = ((request->udc_priv & MSM_ETD_IOC) ? true : false); |
| 695 | |
| 696 | ret = dbm_ep_config(mdwc->dbm, dep->number, bam_pipe, producer, |
| 697 | disable_wb, internal_mem, ioc); |
| 698 | if (ret < 0) { |
| 699 | dev_err(mdwc->dev, |
| 700 | "error %d after calling dbm_ep_config\n", ret); |
| 701 | return ret; |
| 702 | } |
| 703 | |
| 704 | dev_vdbg(dwc->dev, "%s: queing request %p to ep %s length %d\n", |
| 705 | __func__, request, ep->name, request->length); |
| 706 | size = dwc3_msm_read_reg(mdwc->base, DWC3_GEVNTSIZ(0)); |
| 707 | dbm_event_buffer_config(mdwc->dbm, |
| 708 | dwc3_msm_read_reg(mdwc->base, DWC3_GEVNTADRLO(0)), |
| 709 | dwc3_msm_read_reg(mdwc->base, DWC3_GEVNTADRHI(0)), |
| 710 | DWC3_GEVNTSIZ_SIZE(size)); |
| 711 | |
| 712 | /* |
| 713 | * We must obtain the lock of the dwc3 core driver, |
| 714 | * including disabling interrupts, so we will be sure |
| 715 | * that we are the only ones that configure the HW device |
| 716 | * core and ensure that we queuing the request will finish |
| 717 | * as soon as possible so we will release back the lock. |
| 718 | */ |
| 719 | spin_lock_irqsave(&dwc->lock, flags); |
| 720 | if (!dep->endpoint.desc) { |
| 721 | dev_err(mdwc->dev, |
| 722 | "%s: trying to queue request %p to disabled ep %s\n", |
| 723 | __func__, request, ep->name); |
| 724 | ret = -EPERM; |
| 725 | goto err; |
| 726 | } |
| 727 | |
| 728 | if (dep->number == 0 || dep->number == 1) { |
| 729 | dev_err(mdwc->dev, |
| 730 | "%s: trying to queue dbm request %p to control ep %s\n", |
| 731 | __func__, request, ep->name); |
| 732 | ret = -EPERM; |
| 733 | goto err; |
| 734 | } |
| 735 | |
| 736 | |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 737 | if (dep->trb_dequeue != dep->trb_enqueue || |
| 738 | !list_empty(&dep->pending_list) |
| 739 | || !list_empty(&dep->started_list)) { |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 740 | dev_err(mdwc->dev, |
| 741 | "%s: trying to queue dbm request %p tp ep %s\n", |
| 742 | __func__, request, ep->name); |
| 743 | ret = -EPERM; |
| 744 | goto err; |
| 745 | } else { |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 746 | dep->trb_dequeue = 0; |
| 747 | dep->trb_enqueue = 0; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 748 | } |
| 749 | |
| 750 | ret = __dwc3_msm_ep_queue(dep, req); |
| 751 | if (ret < 0) { |
| 752 | dev_err(mdwc->dev, |
| 753 | "error %d after calling __dwc3_msm_ep_queue\n", ret); |
| 754 | goto err; |
| 755 | } |
| 756 | |
| 757 | spin_unlock_irqrestore(&dwc->lock, flags); |
| 758 | superspeed = dwc3_msm_is_dev_superspeed(mdwc); |
| 759 | dbm_set_speed(mdwc->dbm, (u8)superspeed); |
| 760 | |
| 761 | return 0; |
| 762 | |
| 763 | err: |
| 764 | spin_unlock_irqrestore(&dwc->lock, flags); |
| 765 | kfree(req_complete); |
| 766 | return ret; |
| 767 | } |
| 768 | |
| 769 | /* |
| 770 | * Returns XferRscIndex for the EP. This is stored at StartXfer GSI EP OP |
| 771 | * |
| 772 | * @usb_ep - pointer to usb_ep instance. |
| 773 | * |
| 774 | * @return int - XferRscIndex |
| 775 | */ |
| 776 | static inline int gsi_get_xfer_index(struct usb_ep *ep) |
| 777 | { |
| 778 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 779 | |
| 780 | return dep->resource_index; |
| 781 | } |
| 782 | |
| 783 | /* |
| 784 | * Fills up the GSI channel information needed in call to IPA driver |
| 785 | * for GSI channel creation. |
| 786 | * |
| 787 | * @usb_ep - pointer to usb_ep instance. |
| 788 | * @ch_info - output parameter with requested channel info |
| 789 | */ |
| 790 | static void gsi_get_channel_info(struct usb_ep *ep, |
| 791 | struct gsi_channel_info *ch_info) |
| 792 | { |
| 793 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 794 | int last_trb_index = 0; |
| 795 | struct dwc3 *dwc = dep->dwc; |
| 796 | struct usb_gsi_request *request = ch_info->ch_req; |
| 797 | |
| 798 | /* Provide physical USB addresses for DEPCMD and GEVENTCNT registers */ |
| 799 | ch_info->depcmd_low_addr = (u32)(dwc->reg_phys + |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 800 | DWC3_DEPCMD); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 801 | ch_info->depcmd_hi_addr = 0; |
| 802 | |
| 803 | ch_info->xfer_ring_base_addr = dwc3_trb_dma_offset(dep, |
| 804 | &dep->trb_pool[0]); |
| 805 | /* Convert to multipled of 1KB */ |
| 806 | ch_info->const_buffer_size = request->buf_len/1024; |
| 807 | |
| 808 | /* IN direction */ |
| 809 | if (dep->direction) { |
| 810 | /* |
| 811 | * Multiply by size of each TRB for xfer_ring_len in bytes. |
| 812 | * 2n + 2 TRBs as per GSI h/w requirement. n Xfer TRBs + 1 |
| 813 | * extra Xfer TRB followed by n ZLP TRBs + 1 LINK TRB. |
| 814 | */ |
| 815 | ch_info->xfer_ring_len = (2 * request->num_bufs + 2) * 0x10; |
| 816 | last_trb_index = 2 * request->num_bufs + 2; |
| 817 | } else { /* OUT direction */ |
| 818 | /* |
| 819 | * Multiply by size of each TRB for xfer_ring_len in bytes. |
| 820 | * n + 1 TRBs as per GSI h/w requirement. n Xfer TRBs + 1 |
| 821 | * LINK TRB. |
| 822 | */ |
| 823 | ch_info->xfer_ring_len = (request->num_bufs + 1) * 0x10; |
| 824 | last_trb_index = request->num_bufs + 1; |
| 825 | } |
| 826 | |
| 827 | /* Store last 16 bits of LINK TRB address as per GSI hw requirement */ |
| 828 | ch_info->last_trb_addr = (dwc3_trb_dma_offset(dep, |
| 829 | &dep->trb_pool[last_trb_index - 1]) & 0x0000FFFF); |
| 830 | ch_info->gevntcount_low_addr = (u32)(dwc->reg_phys + |
| 831 | DWC3_GEVNTCOUNT(ep->ep_intr_num)); |
| 832 | ch_info->gevntcount_hi_addr = 0; |
| 833 | |
| 834 | dev_dbg(dwc->dev, |
| 835 | "depcmd_laddr=%x last_trb_addr=%x gevtcnt_laddr=%x gevtcnt_haddr=%x", |
| 836 | ch_info->depcmd_low_addr, ch_info->last_trb_addr, |
| 837 | ch_info->gevntcount_low_addr, ch_info->gevntcount_hi_addr); |
| 838 | } |
| 839 | |
| 840 | /* |
| 841 | * Perform StartXfer on GSI EP. Stores XferRscIndex. |
| 842 | * |
| 843 | * @usb_ep - pointer to usb_ep instance. |
| 844 | * |
| 845 | * @return int - 0 on success |
| 846 | */ |
| 847 | static int gsi_startxfer_for_ep(struct usb_ep *ep) |
| 848 | { |
| 849 | int ret; |
| 850 | struct dwc3_gadget_ep_cmd_params params; |
| 851 | u32 cmd; |
| 852 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 853 | struct dwc3 *dwc = dep->dwc; |
| 854 | |
| 855 | memset(¶ms, 0, sizeof(params)); |
| 856 | params.param0 = GSI_TRB_ADDR_BIT_53_MASK | GSI_TRB_ADDR_BIT_55_MASK; |
| 857 | params.param0 |= (ep->ep_intr_num << 16); |
| 858 | params.param1 = lower_32_bits(dwc3_trb_dma_offset(dep, |
| 859 | &dep->trb_pool[0])); |
| 860 | cmd = DWC3_DEPCMD_STARTTRANSFER; |
| 861 | cmd |= DWC3_DEPCMD_PARAM(0); |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 862 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 863 | |
| 864 | if (ret < 0) |
| 865 | dev_dbg(dwc->dev, "Fail StrtXfr on GSI EP#%d\n", dep->number); |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 866 | dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 867 | dev_dbg(dwc->dev, "XferRsc = %x", dep->resource_index); |
| 868 | return ret; |
| 869 | } |
| 870 | |
| 871 | /* |
| 872 | * Store Ring Base and Doorbell Address for GSI EP |
| 873 | * for GSI channel creation. |
| 874 | * |
| 875 | * @usb_ep - pointer to usb_ep instance. |
| 876 | * @dbl_addr - Doorbell address obtained from IPA driver |
| 877 | */ |
| 878 | static void gsi_store_ringbase_dbl_info(struct usb_ep *ep, u32 dbl_addr) |
| 879 | { |
| 880 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 881 | struct dwc3 *dwc = dep->dwc; |
| 882 | struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent); |
| 883 | int n = ep->ep_intr_num - 1; |
| 884 | |
| 885 | dwc3_msm_write_reg(mdwc->base, GSI_RING_BASE_ADDR_L(n), |
| 886 | dwc3_trb_dma_offset(dep, &dep->trb_pool[0])); |
| 887 | dwc3_msm_write_reg(mdwc->base, GSI_DBL_ADDR_L(n), dbl_addr); |
| 888 | |
| 889 | dev_dbg(mdwc->dev, "Ring Base Addr %d = %x", n, |
| 890 | dwc3_msm_read_reg(mdwc->base, GSI_RING_BASE_ADDR_L(n))); |
| 891 | dev_dbg(mdwc->dev, "GSI DB Addr %d = %x", n, |
| 892 | dwc3_msm_read_reg(mdwc->base, GSI_DBL_ADDR_L(n))); |
| 893 | } |
| 894 | |
| 895 | /* |
| 896 | * Rings Doorbell for IN GSI Channel |
| 897 | * |
| 898 | * @usb_ep - pointer to usb_ep instance. |
| 899 | * @request - pointer to GSI request. This is used to pass in the |
| 900 | * address of the GSI doorbell obtained from IPA driver |
| 901 | */ |
| 902 | static void gsi_ring_in_db(struct usb_ep *ep, struct usb_gsi_request *request) |
| 903 | { |
| 904 | void __iomem *gsi_dbl_address_lsb; |
| 905 | void __iomem *gsi_dbl_address_msb; |
| 906 | dma_addr_t offset; |
| 907 | u64 dbl_addr = *((u64 *)request->buf_base_addr); |
| 908 | u32 dbl_lo_addr = (dbl_addr & 0xFFFFFFFF); |
| 909 | u32 dbl_hi_addr = (dbl_addr >> 32); |
| 910 | u32 num_trbs = (request->num_bufs * 2 + 2); |
| 911 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 912 | struct dwc3 *dwc = dep->dwc; |
| 913 | struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent); |
| 914 | |
| 915 | gsi_dbl_address_lsb = devm_ioremap_nocache(mdwc->dev, |
| 916 | dbl_lo_addr, sizeof(u32)); |
| 917 | if (!gsi_dbl_address_lsb) |
| 918 | dev_dbg(mdwc->dev, "Failed to get GSI DBL address LSB\n"); |
| 919 | |
| 920 | gsi_dbl_address_msb = devm_ioremap_nocache(mdwc->dev, |
| 921 | dbl_hi_addr, sizeof(u32)); |
| 922 | if (!gsi_dbl_address_msb) |
| 923 | dev_dbg(mdwc->dev, "Failed to get GSI DBL address MSB\n"); |
| 924 | |
| 925 | offset = dwc3_trb_dma_offset(dep, &dep->trb_pool[num_trbs-1]); |
| 926 | dev_dbg(mdwc->dev, "Writing link TRB addr: %pa to %p (%x)\n", |
| 927 | &offset, gsi_dbl_address_lsb, dbl_lo_addr); |
| 928 | |
| 929 | writel_relaxed(offset, gsi_dbl_address_lsb); |
| 930 | writel_relaxed(0, gsi_dbl_address_msb); |
| 931 | } |
| 932 | |
| 933 | /* |
| 934 | * Sets HWO bit for TRBs and performs UpdateXfer for OUT EP. |
| 935 | * |
| 936 | * @usb_ep - pointer to usb_ep instance. |
| 937 | * @request - pointer to GSI request. Used to determine num of TRBs for OUT EP. |
| 938 | * |
| 939 | * @return int - 0 on success |
| 940 | */ |
| 941 | static int gsi_updatexfer_for_ep(struct usb_ep *ep, |
| 942 | struct usb_gsi_request *request) |
| 943 | { |
| 944 | int i; |
| 945 | int ret; |
| 946 | u32 cmd; |
| 947 | int num_trbs = request->num_bufs + 1; |
| 948 | struct dwc3_trb *trb; |
| 949 | struct dwc3_gadget_ep_cmd_params params; |
| 950 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 951 | struct dwc3 *dwc = dep->dwc; |
| 952 | |
| 953 | for (i = 0; i < num_trbs - 1; i++) { |
| 954 | trb = &dep->trb_pool[i]; |
| 955 | trb->ctrl |= DWC3_TRB_CTRL_HWO; |
| 956 | } |
| 957 | |
| 958 | memset(¶ms, 0, sizeof(params)); |
| 959 | cmd = DWC3_DEPCMD_UPDATETRANSFER; |
| 960 | cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 961 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 962 | dep->flags |= DWC3_EP_BUSY; |
| 963 | if (ret < 0) |
| 964 | dev_dbg(dwc->dev, "UpdateXfr fail on GSI EP#%d\n", dep->number); |
| 965 | return ret; |
| 966 | } |
| 967 | |
| 968 | /* |
| 969 | * Perform EndXfer on particular GSI EP. |
| 970 | * |
| 971 | * @usb_ep - pointer to usb_ep instance. |
| 972 | */ |
| 973 | static void gsi_endxfer_for_ep(struct usb_ep *ep) |
| 974 | { |
| 975 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 976 | struct dwc3 *dwc = dep->dwc; |
| 977 | |
| 978 | dwc3_stop_active_transfer(dwc, dep->number, true); |
| 979 | } |
| 980 | |
| 981 | /* |
| 982 | * Allocates and configures TRBs for GSI EPs. |
| 983 | * |
| 984 | * @usb_ep - pointer to usb_ep instance. |
| 985 | * @request - pointer to GSI request. |
| 986 | * |
| 987 | * @return int - 0 on success |
| 988 | */ |
| 989 | static int gsi_prepare_trbs(struct usb_ep *ep, struct usb_gsi_request *req) |
| 990 | { |
| 991 | int i = 0; |
| 992 | dma_addr_t buffer_addr = req->dma; |
| 993 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 994 | struct dwc3 *dwc = dep->dwc; |
| 995 | struct dwc3_trb *trb; |
| 996 | int num_trbs = (dep->direction) ? (2 * (req->num_bufs) + 2) |
| 997 | : (req->num_bufs + 1); |
| 998 | |
| 999 | dep->trb_dma_pool = dma_pool_create(ep->name, dwc->dev, |
| 1000 | num_trbs * sizeof(struct dwc3_trb), |
| 1001 | num_trbs * sizeof(struct dwc3_trb), 0); |
| 1002 | if (!dep->trb_dma_pool) { |
| 1003 | dev_err(dep->dwc->dev, "failed to alloc trb dma pool for %s\n", |
| 1004 | dep->name); |
| 1005 | return -ENOMEM; |
| 1006 | } |
| 1007 | |
| 1008 | dep->num_trbs = num_trbs; |
| 1009 | |
| 1010 | dep->trb_pool = dma_pool_alloc(dep->trb_dma_pool, |
| 1011 | GFP_KERNEL, &dep->trb_pool_dma); |
| 1012 | if (!dep->trb_pool) { |
| 1013 | dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n", |
| 1014 | dep->name); |
| 1015 | return -ENOMEM; |
| 1016 | } |
| 1017 | |
| 1018 | /* IN direction */ |
| 1019 | if (dep->direction) { |
| 1020 | for (i = 0; i < num_trbs ; i++) { |
| 1021 | trb = &dep->trb_pool[i]; |
| 1022 | memset(trb, 0, sizeof(*trb)); |
| 1023 | /* Set up first n+1 TRBs for ZLPs */ |
| 1024 | if (i < (req->num_bufs + 1)) { |
| 1025 | trb->bpl = 0; |
| 1026 | trb->bph = 0; |
| 1027 | trb->size = 0; |
| 1028 | trb->ctrl = DWC3_TRBCTL_NORMAL |
| 1029 | | DWC3_TRB_CTRL_IOC; |
| 1030 | continue; |
| 1031 | } |
| 1032 | |
| 1033 | /* Setup n TRBs pointing to valid buffers */ |
| 1034 | trb->bpl = lower_32_bits(buffer_addr); |
| 1035 | trb->bph = 0; |
| 1036 | trb->size = 0; |
| 1037 | trb->ctrl = DWC3_TRBCTL_NORMAL |
| 1038 | | DWC3_TRB_CTRL_IOC; |
| 1039 | buffer_addr += req->buf_len; |
| 1040 | |
| 1041 | /* Set up the Link TRB at the end */ |
| 1042 | if (i == (num_trbs - 1)) { |
| 1043 | trb->bpl = dwc3_trb_dma_offset(dep, |
| 1044 | &dep->trb_pool[0]); |
| 1045 | trb->bph = (1 << 23) | (1 << 21) |
| 1046 | | (ep->ep_intr_num << 16); |
| 1047 | trb->size = 0; |
| 1048 | trb->ctrl = DWC3_TRBCTL_LINK_TRB |
| 1049 | | DWC3_TRB_CTRL_HWO; |
| 1050 | } |
| 1051 | } |
| 1052 | } else { /* OUT direction */ |
| 1053 | |
| 1054 | for (i = 0; i < num_trbs ; i++) { |
| 1055 | |
| 1056 | trb = &dep->trb_pool[i]; |
| 1057 | memset(trb, 0, sizeof(*trb)); |
| 1058 | trb->bpl = lower_32_bits(buffer_addr); |
| 1059 | trb->bph = 0; |
| 1060 | trb->size = req->buf_len; |
| 1061 | trb->ctrl = DWC3_TRBCTL_NORMAL | DWC3_TRB_CTRL_IOC |
| 1062 | | DWC3_TRB_CTRL_CSP |
| 1063 | | DWC3_TRB_CTRL_ISP_IMI; |
| 1064 | buffer_addr += req->buf_len; |
| 1065 | |
| 1066 | /* Set up the Link TRB at the end */ |
| 1067 | if (i == (num_trbs - 1)) { |
| 1068 | trb->bpl = dwc3_trb_dma_offset(dep, |
| 1069 | &dep->trb_pool[0]); |
| 1070 | trb->bph = (1 << 23) | (1 << 21) |
| 1071 | | (ep->ep_intr_num << 16); |
| 1072 | trb->size = 0; |
| 1073 | trb->ctrl = DWC3_TRBCTL_LINK_TRB |
| 1074 | | DWC3_TRB_CTRL_HWO; |
| 1075 | } |
| 1076 | } |
| 1077 | } |
| 1078 | return 0; |
| 1079 | } |
| 1080 | |
| 1081 | /* |
| 1082 | * Frees TRBs for GSI EPs. |
| 1083 | * |
| 1084 | * @usb_ep - pointer to usb_ep instance. |
| 1085 | * |
| 1086 | */ |
| 1087 | static void gsi_free_trbs(struct usb_ep *ep) |
| 1088 | { |
| 1089 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 1090 | |
| 1091 | if (dep->endpoint.ep_type == EP_TYPE_NORMAL) |
| 1092 | return; |
| 1093 | |
| 1094 | /* Free TRBs and TRB pool for EP */ |
| 1095 | if (dep->trb_dma_pool) { |
| 1096 | dma_pool_free(dep->trb_dma_pool, dep->trb_pool, |
| 1097 | dep->trb_pool_dma); |
| 1098 | dma_pool_destroy(dep->trb_dma_pool); |
| 1099 | dep->trb_pool = NULL; |
| 1100 | dep->trb_pool_dma = 0; |
| 1101 | dep->trb_dma_pool = NULL; |
| 1102 | } |
| 1103 | } |
| 1104 | /* |
| 1105 | * Configures GSI EPs. For GSI EPs we need to set interrupter numbers. |
| 1106 | * |
| 1107 | * @usb_ep - pointer to usb_ep instance. |
| 1108 | * @request - pointer to GSI request. |
| 1109 | */ |
| 1110 | static void gsi_configure_ep(struct usb_ep *ep, struct usb_gsi_request *request) |
| 1111 | { |
| 1112 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 1113 | struct dwc3 *dwc = dep->dwc; |
| 1114 | struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent); |
| 1115 | struct dwc3_gadget_ep_cmd_params params; |
| 1116 | const struct usb_endpoint_descriptor *desc = ep->desc; |
| 1117 | const struct usb_ss_ep_comp_descriptor *comp_desc = ep->comp_desc; |
| 1118 | u32 reg; |
| 1119 | |
| 1120 | memset(¶ms, 0x00, sizeof(params)); |
| 1121 | |
| 1122 | /* Configure GSI EP */ |
| 1123 | params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) |
| 1124 | | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)); |
| 1125 | |
| 1126 | /* Burst size is only needed in SuperSpeed mode */ |
| 1127 | if (dwc->gadget.speed == USB_SPEED_SUPER) { |
| 1128 | u32 burst = dep->endpoint.maxburst - 1; |
| 1129 | |
| 1130 | params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst); |
| 1131 | } |
| 1132 | |
| 1133 | if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) { |
| 1134 | params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE |
| 1135 | | DWC3_DEPCFG_STREAM_EVENT_EN; |
| 1136 | dep->stream_capable = true; |
| 1137 | } |
| 1138 | |
| 1139 | /* Set EP number */ |
| 1140 | params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); |
| 1141 | |
| 1142 | /* Set interrupter number for GSI endpoints */ |
| 1143 | params.param1 |= DWC3_DEPCFG_INT_NUM(ep->ep_intr_num); |
| 1144 | |
| 1145 | /* Enable XferInProgress and XferComplete Interrupts */ |
| 1146 | params.param1 |= DWC3_DEPCFG_XFER_COMPLETE_EN; |
| 1147 | params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; |
| 1148 | params.param1 |= DWC3_DEPCFG_FIFO_ERROR_EN; |
| 1149 | /* |
| 1150 | * We must use the lower 16 TX FIFOs even though |
| 1151 | * HW might have more |
| 1152 | */ |
| 1153 | /* Remove FIFO Number for GSI EP*/ |
| 1154 | if (dep->direction) |
| 1155 | params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); |
| 1156 | |
| 1157 | params.param0 |= DWC3_DEPCFG_ACTION_INIT; |
| 1158 | |
| 1159 | dev_dbg(mdwc->dev, "Set EP config to params = %x %x %x, for %s\n", |
| 1160 | params.param0, params.param1, params.param2, dep->name); |
| 1161 | |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 1162 | dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1163 | |
| 1164 | /* Set XferRsc Index for GSI EP */ |
| 1165 | if (!(dep->flags & DWC3_EP_ENABLED)) { |
| 1166 | memset(¶ms, 0x00, sizeof(params)); |
| 1167 | params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 1168 | dwc3_send_gadget_ep_cmd(dep, |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1169 | DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms); |
| 1170 | |
| 1171 | dep->endpoint.desc = desc; |
| 1172 | dep->comp_desc = comp_desc; |
| 1173 | dep->type = usb_endpoint_type(desc); |
| 1174 | dep->flags |= DWC3_EP_ENABLED; |
| 1175 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); |
| 1176 | reg |= DWC3_DALEPENA_EP(dep->number); |
| 1177 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); |
| 1178 | } |
| 1179 | |
| 1180 | } |
| 1181 | |
| 1182 | /* |
| 1183 | * Enables USB wrapper for GSI |
| 1184 | * |
| 1185 | * @usb_ep - pointer to usb_ep instance. |
| 1186 | */ |
| 1187 | static void gsi_enable(struct usb_ep *ep) |
| 1188 | { |
| 1189 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 1190 | struct dwc3 *dwc = dep->dwc; |
| 1191 | struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent); |
| 1192 | |
| 1193 | dwc3_msm_write_reg_field(mdwc->base, |
| 1194 | GSI_GENERAL_CFG_REG, GSI_CLK_EN_MASK, 1); |
| 1195 | dwc3_msm_write_reg_field(mdwc->base, |
| 1196 | GSI_GENERAL_CFG_REG, GSI_RESTART_DBL_PNTR_MASK, 1); |
| 1197 | dwc3_msm_write_reg_field(mdwc->base, |
| 1198 | GSI_GENERAL_CFG_REG, GSI_RESTART_DBL_PNTR_MASK, 0); |
| 1199 | dev_dbg(mdwc->dev, "%s: Enable GSI\n", __func__); |
| 1200 | dwc3_msm_write_reg_field(mdwc->base, |
| 1201 | GSI_GENERAL_CFG_REG, GSI_EN_MASK, 1); |
| 1202 | } |
| 1203 | |
| 1204 | /* |
| 1205 | * Block or allow doorbell towards GSI |
| 1206 | * |
| 1207 | * @usb_ep - pointer to usb_ep instance. |
| 1208 | * @request - pointer to GSI request. In this case num_bufs is used as a bool |
| 1209 | * to set or clear the doorbell bit |
| 1210 | */ |
| 1211 | static void gsi_set_clear_dbell(struct usb_ep *ep, |
| 1212 | bool block_db) |
| 1213 | { |
| 1214 | |
| 1215 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 1216 | struct dwc3 *dwc = dep->dwc; |
| 1217 | struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent); |
| 1218 | |
| 1219 | dwc3_msm_write_reg_field(mdwc->base, |
| 1220 | GSI_GENERAL_CFG_REG, BLOCK_GSI_WR_GO_MASK, block_db); |
| 1221 | } |
| 1222 | |
| 1223 | /* |
| 1224 | * Performs necessary checks before stopping GSI channels |
| 1225 | * |
| 1226 | * @usb_ep - pointer to usb_ep instance to access DWC3 regs |
| 1227 | */ |
| 1228 | static bool gsi_check_ready_to_suspend(struct usb_ep *ep, bool f_suspend) |
| 1229 | { |
| 1230 | u32 timeout = 1500; |
| 1231 | u32 reg = 0; |
| 1232 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 1233 | struct dwc3 *dwc = dep->dwc; |
| 1234 | struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent); |
| 1235 | |
| 1236 | while (dwc3_msm_read_reg_field(mdwc->base, |
| 1237 | GSI_IF_STS, GSI_WR_CTRL_STATE_MASK)) { |
| 1238 | if (!timeout--) { |
| 1239 | dev_err(mdwc->dev, |
| 1240 | "Unable to suspend GSI ch. WR_CTRL_STATE != 0\n"); |
| 1241 | return false; |
| 1242 | } |
| 1243 | } |
| 1244 | /* Check for U3 only if we are not handling Function Suspend */ |
| 1245 | if (!f_suspend) { |
| 1246 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
| 1247 | if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U3) { |
| 1248 | dev_err(mdwc->dev, "Unable to suspend GSI ch\n"); |
| 1249 | return false; |
| 1250 | } |
| 1251 | } |
| 1252 | |
| 1253 | return true; |
| 1254 | } |
| 1255 | |
| 1256 | |
| 1257 | /** |
| 1258 | * Performs GSI operations or GSI EP related operations. |
| 1259 | * |
| 1260 | * @usb_ep - pointer to usb_ep instance. |
| 1261 | * @op_data - pointer to opcode related data. |
| 1262 | * @op - GSI related or GSI EP related op code. |
| 1263 | * |
| 1264 | * @return int - 0 on success, negative on error. |
| 1265 | * Also returns XferRscIdx for GSI_EP_OP_GET_XFER_IDX. |
| 1266 | */ |
| 1267 | static int dwc3_msm_gsi_ep_op(struct usb_ep *ep, |
| 1268 | void *op_data, enum gsi_ep_op op) |
| 1269 | { |
| 1270 | u32 ret = 0; |
| 1271 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 1272 | struct dwc3 *dwc = dep->dwc; |
| 1273 | struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent); |
| 1274 | struct usb_gsi_request *request; |
| 1275 | struct gsi_channel_info *ch_info; |
| 1276 | bool block_db, f_suspend; |
Mayank Rana | 8432c36 | 2016-09-30 18:41:17 -0700 | [diff] [blame] | 1277 | unsigned long flags; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1278 | |
| 1279 | switch (op) { |
| 1280 | case GSI_EP_OP_PREPARE_TRBS: |
| 1281 | request = (struct usb_gsi_request *)op_data; |
| 1282 | dev_dbg(mdwc->dev, "EP_OP_PREPARE_TRBS for %s\n", ep->name); |
| 1283 | ret = gsi_prepare_trbs(ep, request); |
| 1284 | break; |
| 1285 | case GSI_EP_OP_FREE_TRBS: |
| 1286 | dev_dbg(mdwc->dev, "EP_OP_FREE_TRBS for %s\n", ep->name); |
| 1287 | gsi_free_trbs(ep); |
| 1288 | break; |
| 1289 | case GSI_EP_OP_CONFIG: |
| 1290 | request = (struct usb_gsi_request *)op_data; |
| 1291 | dev_dbg(mdwc->dev, "EP_OP_CONFIG for %s\n", ep->name); |
Mayank Rana | 8432c36 | 2016-09-30 18:41:17 -0700 | [diff] [blame] | 1292 | spin_lock_irqsave(&dwc->lock, flags); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1293 | gsi_configure_ep(ep, request); |
Mayank Rana | 8432c36 | 2016-09-30 18:41:17 -0700 | [diff] [blame] | 1294 | spin_unlock_irqrestore(&dwc->lock, flags); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1295 | break; |
| 1296 | case GSI_EP_OP_STARTXFER: |
| 1297 | dev_dbg(mdwc->dev, "EP_OP_STARTXFER for %s\n", ep->name); |
Mayank Rana | 8432c36 | 2016-09-30 18:41:17 -0700 | [diff] [blame] | 1298 | spin_lock_irqsave(&dwc->lock, flags); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1299 | ret = gsi_startxfer_for_ep(ep); |
Mayank Rana | 8432c36 | 2016-09-30 18:41:17 -0700 | [diff] [blame] | 1300 | spin_unlock_irqrestore(&dwc->lock, flags); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1301 | break; |
| 1302 | case GSI_EP_OP_GET_XFER_IDX: |
| 1303 | dev_dbg(mdwc->dev, "EP_OP_GET_XFER_IDX for %s\n", ep->name); |
| 1304 | ret = gsi_get_xfer_index(ep); |
| 1305 | break; |
| 1306 | case GSI_EP_OP_STORE_DBL_INFO: |
| 1307 | dev_dbg(mdwc->dev, "EP_OP_STORE_DBL_INFO\n"); |
| 1308 | gsi_store_ringbase_dbl_info(ep, *((u32 *)op_data)); |
| 1309 | break; |
| 1310 | case GSI_EP_OP_ENABLE_GSI: |
| 1311 | dev_dbg(mdwc->dev, "EP_OP_ENABLE_GSI\n"); |
| 1312 | gsi_enable(ep); |
| 1313 | break; |
| 1314 | case GSI_EP_OP_GET_CH_INFO: |
| 1315 | ch_info = (struct gsi_channel_info *)op_data; |
| 1316 | gsi_get_channel_info(ep, ch_info); |
| 1317 | break; |
| 1318 | case GSI_EP_OP_RING_IN_DB: |
| 1319 | request = (struct usb_gsi_request *)op_data; |
| 1320 | dev_dbg(mdwc->dev, "RING IN EP DB\n"); |
| 1321 | gsi_ring_in_db(ep, request); |
| 1322 | break; |
| 1323 | case GSI_EP_OP_UPDATEXFER: |
| 1324 | request = (struct usb_gsi_request *)op_data; |
| 1325 | dev_dbg(mdwc->dev, "EP_OP_UPDATEXFER\n"); |
Mayank Rana | 8432c36 | 2016-09-30 18:41:17 -0700 | [diff] [blame] | 1326 | spin_lock_irqsave(&dwc->lock, flags); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1327 | ret = gsi_updatexfer_for_ep(ep, request); |
Mayank Rana | 8432c36 | 2016-09-30 18:41:17 -0700 | [diff] [blame] | 1328 | spin_unlock_irqrestore(&dwc->lock, flags); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1329 | break; |
| 1330 | case GSI_EP_OP_ENDXFER: |
| 1331 | request = (struct usb_gsi_request *)op_data; |
| 1332 | dev_dbg(mdwc->dev, "EP_OP_ENDXFER for %s\n", ep->name); |
Mayank Rana | 8432c36 | 2016-09-30 18:41:17 -0700 | [diff] [blame] | 1333 | spin_lock_irqsave(&dwc->lock, flags); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1334 | gsi_endxfer_for_ep(ep); |
Mayank Rana | 8432c36 | 2016-09-30 18:41:17 -0700 | [diff] [blame] | 1335 | spin_unlock_irqrestore(&dwc->lock, flags); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1336 | break; |
| 1337 | case GSI_EP_OP_SET_CLR_BLOCK_DBL: |
| 1338 | block_db = *((bool *)op_data); |
| 1339 | dev_dbg(mdwc->dev, "EP_OP_SET_CLR_BLOCK_DBL %d\n", |
| 1340 | block_db); |
| 1341 | gsi_set_clear_dbell(ep, block_db); |
| 1342 | break; |
| 1343 | case GSI_EP_OP_CHECK_FOR_SUSPEND: |
| 1344 | dev_dbg(mdwc->dev, "EP_OP_CHECK_FOR_SUSPEND\n"); |
| 1345 | f_suspend = *((bool *)op_data); |
| 1346 | ret = gsi_check_ready_to_suspend(ep, f_suspend); |
| 1347 | break; |
| 1348 | case GSI_EP_OP_DISABLE: |
| 1349 | dev_dbg(mdwc->dev, "EP_OP_DISABLE\n"); |
| 1350 | ret = ep->ops->disable(ep); |
| 1351 | break; |
| 1352 | default: |
| 1353 | dev_err(mdwc->dev, "%s: Invalid opcode GSI EP\n", __func__); |
| 1354 | } |
| 1355 | |
| 1356 | return ret; |
| 1357 | } |
| 1358 | |
| 1359 | /** |
| 1360 | * Configure MSM endpoint. |
| 1361 | * This function do specific configurations |
| 1362 | * to an endpoint which need specific implementaion |
| 1363 | * in the MSM architecture. |
| 1364 | * |
| 1365 | * This function should be called by usb function/class |
| 1366 | * layer which need a support from the specific MSM HW |
| 1367 | * which wrap the USB3 core. (like GSI or DBM specific endpoints) |
| 1368 | * |
| 1369 | * @ep - a pointer to some usb_ep instance |
| 1370 | * |
| 1371 | * @return int - 0 on success, negetive on error. |
| 1372 | */ |
| 1373 | int msm_ep_config(struct usb_ep *ep) |
| 1374 | { |
| 1375 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 1376 | struct dwc3 *dwc = dep->dwc; |
| 1377 | struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent); |
| 1378 | struct usb_ep_ops *new_ep_ops; |
| 1379 | |
| 1380 | |
| 1381 | /* Save original ep ops for future restore*/ |
| 1382 | if (mdwc->original_ep_ops[dep->number]) { |
| 1383 | dev_err(mdwc->dev, |
| 1384 | "ep [%s,%d] already configured as msm endpoint\n", |
| 1385 | ep->name, dep->number); |
| 1386 | return -EPERM; |
| 1387 | } |
| 1388 | mdwc->original_ep_ops[dep->number] = ep->ops; |
| 1389 | |
| 1390 | /* Set new usb ops as we like */ |
| 1391 | new_ep_ops = kzalloc(sizeof(struct usb_ep_ops), GFP_ATOMIC); |
| 1392 | if (!new_ep_ops) |
| 1393 | return -ENOMEM; |
| 1394 | |
| 1395 | (*new_ep_ops) = (*ep->ops); |
| 1396 | new_ep_ops->queue = dwc3_msm_ep_queue; |
| 1397 | new_ep_ops->gsi_ep_op = dwc3_msm_gsi_ep_op; |
| 1398 | ep->ops = new_ep_ops; |
| 1399 | |
| 1400 | /* |
| 1401 | * Do HERE more usb endpoint configurations |
| 1402 | * which are specific to MSM. |
| 1403 | */ |
| 1404 | |
| 1405 | return 0; |
| 1406 | } |
| 1407 | EXPORT_SYMBOL(msm_ep_config); |
| 1408 | |
| 1409 | /** |
| 1410 | * Un-configure MSM endpoint. |
| 1411 | * Tear down configurations done in the |
| 1412 | * dwc3_msm_ep_config function. |
| 1413 | * |
| 1414 | * @ep - a pointer to some usb_ep instance |
| 1415 | * |
| 1416 | * @return int - 0 on success, negative on error. |
| 1417 | */ |
| 1418 | int msm_ep_unconfig(struct usb_ep *ep) |
| 1419 | { |
| 1420 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 1421 | struct dwc3 *dwc = dep->dwc; |
| 1422 | struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent); |
| 1423 | struct usb_ep_ops *old_ep_ops; |
| 1424 | |
| 1425 | /* Restore original ep ops */ |
| 1426 | if (!mdwc->original_ep_ops[dep->number]) { |
| 1427 | dev_err(mdwc->dev, |
| 1428 | "ep [%s,%d] was not configured as msm endpoint\n", |
| 1429 | ep->name, dep->number); |
| 1430 | return -EINVAL; |
| 1431 | } |
| 1432 | old_ep_ops = (struct usb_ep_ops *)ep->ops; |
| 1433 | ep->ops = mdwc->original_ep_ops[dep->number]; |
| 1434 | mdwc->original_ep_ops[dep->number] = NULL; |
| 1435 | kfree(old_ep_ops); |
| 1436 | |
| 1437 | /* |
| 1438 | * Do HERE more usb endpoint un-configurations |
| 1439 | * which are specific to MSM. |
| 1440 | */ |
| 1441 | |
| 1442 | return 0; |
| 1443 | } |
| 1444 | EXPORT_SYMBOL(msm_ep_unconfig); |
| 1445 | #endif /* (CONFIG_USB_DWC3_GADGET) || (CONFIG_USB_DWC3_DUAL_ROLE) */ |
| 1446 | |
| 1447 | static void dwc3_resume_work(struct work_struct *w); |
| 1448 | |
| 1449 | static void dwc3_restart_usb_work(struct work_struct *w) |
| 1450 | { |
| 1451 | struct dwc3_msm *mdwc = container_of(w, struct dwc3_msm, |
| 1452 | restart_usb_work); |
| 1453 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
| 1454 | unsigned int timeout = 50; |
| 1455 | |
| 1456 | dev_dbg(mdwc->dev, "%s\n", __func__); |
| 1457 | |
| 1458 | if (atomic_read(&dwc->in_lpm) || !dwc->is_drd) { |
| 1459 | dev_dbg(mdwc->dev, "%s failed!!!\n", __func__); |
| 1460 | return; |
| 1461 | } |
| 1462 | |
| 1463 | /* guard against concurrent VBUS handling */ |
| 1464 | mdwc->in_restart = true; |
| 1465 | |
| 1466 | if (!mdwc->vbus_active) { |
| 1467 | dev_dbg(mdwc->dev, "%s bailing out in disconnect\n", __func__); |
| 1468 | dwc->err_evt_seen = false; |
| 1469 | mdwc->in_restart = false; |
| 1470 | return; |
| 1471 | } |
| 1472 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1473 | /* Reset active USB connection */ |
| 1474 | dwc3_resume_work(&mdwc->resume_work); |
| 1475 | |
| 1476 | /* Make sure disconnect is processed before sending connect */ |
| 1477 | while (--timeout && !pm_runtime_suspended(mdwc->dev)) |
| 1478 | msleep(20); |
| 1479 | |
| 1480 | if (!timeout) { |
| 1481 | dev_dbg(mdwc->dev, |
| 1482 | "Not in LPM after disconnect, forcing suspend...\n"); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1483 | pm_runtime_suspend(mdwc->dev); |
| 1484 | } |
| 1485 | |
Vijayavardhan Vennapusa | 5e5680e | 2016-11-25 11:25:35 +0530 | [diff] [blame] | 1486 | mdwc->in_restart = false; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1487 | /* Force reconnect only if cable is still connected */ |
Vijayavardhan Vennapusa | 5e5680e | 2016-11-25 11:25:35 +0530 | [diff] [blame] | 1488 | if (mdwc->vbus_active) |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1489 | dwc3_resume_work(&mdwc->resume_work); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1490 | |
| 1491 | dwc->err_evt_seen = false; |
| 1492 | flush_delayed_work(&mdwc->sm_work); |
| 1493 | } |
| 1494 | |
| 1495 | /* |
| 1496 | * Check whether the DWC3 requires resetting the ep |
| 1497 | * after going to Low Power Mode (lpm) |
| 1498 | */ |
| 1499 | bool msm_dwc3_reset_ep_after_lpm(struct usb_gadget *gadget) |
| 1500 | { |
| 1501 | struct dwc3 *dwc = container_of(gadget, struct dwc3, gadget); |
| 1502 | struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent); |
| 1503 | |
| 1504 | return dbm_reset_ep_after_lpm(mdwc->dbm); |
| 1505 | } |
| 1506 | EXPORT_SYMBOL(msm_dwc3_reset_ep_after_lpm); |
| 1507 | |
| 1508 | /* |
| 1509 | * Config Global Distributed Switch Controller (GDSC) |
| 1510 | * to support controller power collapse |
| 1511 | */ |
| 1512 | static int dwc3_msm_config_gdsc(struct dwc3_msm *mdwc, int on) |
| 1513 | { |
| 1514 | int ret; |
| 1515 | |
| 1516 | if (IS_ERR_OR_NULL(mdwc->dwc3_gdsc)) |
| 1517 | return -EPERM; |
| 1518 | |
| 1519 | if (on) { |
| 1520 | ret = regulator_enable(mdwc->dwc3_gdsc); |
| 1521 | if (ret) { |
| 1522 | dev_err(mdwc->dev, "unable to enable usb3 gdsc\n"); |
| 1523 | return ret; |
| 1524 | } |
| 1525 | } else { |
| 1526 | ret = regulator_disable(mdwc->dwc3_gdsc); |
| 1527 | if (ret) { |
| 1528 | dev_err(mdwc->dev, "unable to disable usb3 gdsc\n"); |
| 1529 | return ret; |
| 1530 | } |
| 1531 | } |
| 1532 | |
| 1533 | return ret; |
| 1534 | } |
| 1535 | |
| 1536 | static int dwc3_msm_link_clk_reset(struct dwc3_msm *mdwc, bool assert) |
| 1537 | { |
| 1538 | int ret = 0; |
| 1539 | |
| 1540 | if (assert) { |
| 1541 | disable_irq(mdwc->pwr_event_irq); |
| 1542 | /* Using asynchronous block reset to the hardware */ |
| 1543 | dev_dbg(mdwc->dev, "block_reset ASSERT\n"); |
| 1544 | clk_disable_unprepare(mdwc->utmi_clk); |
| 1545 | clk_disable_unprepare(mdwc->sleep_clk); |
| 1546 | clk_disable_unprepare(mdwc->core_clk); |
| 1547 | clk_disable_unprepare(mdwc->iface_clk); |
Amit Nischal | 4d27821 | 2016-06-06 17:54:34 +0530 | [diff] [blame] | 1548 | ret = reset_control_assert(mdwc->core_reset); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1549 | if (ret) |
Amit Nischal | 4d27821 | 2016-06-06 17:54:34 +0530 | [diff] [blame] | 1550 | dev_err(mdwc->dev, "dwc3 core_reset assert failed\n"); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1551 | } else { |
| 1552 | dev_dbg(mdwc->dev, "block_reset DEASSERT\n"); |
Amit Nischal | 4d27821 | 2016-06-06 17:54:34 +0530 | [diff] [blame] | 1553 | ret = reset_control_deassert(mdwc->core_reset); |
| 1554 | if (ret) |
| 1555 | dev_err(mdwc->dev, "dwc3 core_reset deassert failed\n"); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1556 | ndelay(200); |
| 1557 | clk_prepare_enable(mdwc->iface_clk); |
| 1558 | clk_prepare_enable(mdwc->core_clk); |
| 1559 | clk_prepare_enable(mdwc->sleep_clk); |
| 1560 | clk_prepare_enable(mdwc->utmi_clk); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1561 | enable_irq(mdwc->pwr_event_irq); |
| 1562 | } |
| 1563 | |
| 1564 | return ret; |
| 1565 | } |
| 1566 | |
| 1567 | static void dwc3_msm_update_ref_clk(struct dwc3_msm *mdwc) |
| 1568 | { |
| 1569 | u32 guctl, gfladj = 0; |
| 1570 | |
| 1571 | guctl = dwc3_msm_read_reg(mdwc->base, DWC3_GUCTL); |
| 1572 | guctl &= ~DWC3_GUCTL_REFCLKPER; |
| 1573 | |
| 1574 | /* GFLADJ register is used starting with revision 2.50a */ |
| 1575 | if (dwc3_msm_read_reg(mdwc->base, DWC3_GSNPSID) >= DWC3_REVISION_250A) { |
| 1576 | gfladj = dwc3_msm_read_reg(mdwc->base, DWC3_GFLADJ); |
| 1577 | gfladj &= ~DWC3_GFLADJ_REFCLK_240MHZDECR_PLS1; |
| 1578 | gfladj &= ~DWC3_GFLADJ_REFCLK_240MHZ_DECR; |
| 1579 | gfladj &= ~DWC3_GFLADJ_REFCLK_LPM_SEL; |
| 1580 | gfladj &= ~DWC3_GFLADJ_REFCLK_FLADJ; |
| 1581 | } |
| 1582 | |
| 1583 | /* Refer to SNPS Databook Table 6-55 for calculations used */ |
| 1584 | switch (mdwc->utmi_clk_rate) { |
| 1585 | case 19200000: |
| 1586 | guctl |= 52 << __ffs(DWC3_GUCTL_REFCLKPER); |
| 1587 | gfladj |= 12 << __ffs(DWC3_GFLADJ_REFCLK_240MHZ_DECR); |
| 1588 | gfladj |= DWC3_GFLADJ_REFCLK_240MHZDECR_PLS1; |
| 1589 | gfladj |= DWC3_GFLADJ_REFCLK_LPM_SEL; |
| 1590 | gfladj |= 200 << __ffs(DWC3_GFLADJ_REFCLK_FLADJ); |
| 1591 | break; |
| 1592 | case 24000000: |
| 1593 | guctl |= 41 << __ffs(DWC3_GUCTL_REFCLKPER); |
| 1594 | gfladj |= 10 << __ffs(DWC3_GFLADJ_REFCLK_240MHZ_DECR); |
| 1595 | gfladj |= DWC3_GFLADJ_REFCLK_LPM_SEL; |
| 1596 | gfladj |= 2032 << __ffs(DWC3_GFLADJ_REFCLK_FLADJ); |
| 1597 | break; |
| 1598 | default: |
| 1599 | dev_warn(mdwc->dev, "Unsupported utmi_clk_rate: %u\n", |
| 1600 | mdwc->utmi_clk_rate); |
| 1601 | break; |
| 1602 | } |
| 1603 | |
| 1604 | dwc3_msm_write_reg(mdwc->base, DWC3_GUCTL, guctl); |
| 1605 | if (gfladj) |
| 1606 | dwc3_msm_write_reg(mdwc->base, DWC3_GFLADJ, gfladj); |
| 1607 | } |
| 1608 | |
| 1609 | /* Initialize QSCRATCH registers for HSPHY and SSPHY operation */ |
| 1610 | static void dwc3_msm_qscratch_reg_init(struct dwc3_msm *mdwc) |
| 1611 | { |
| 1612 | if (dwc3_msm_read_reg(mdwc->base, DWC3_GSNPSID) < DWC3_REVISION_250A) |
| 1613 | /* On older cores set XHCI_REV bit to specify revision 1.0 */ |
| 1614 | dwc3_msm_write_reg_field(mdwc->base, QSCRATCH_GENERAL_CFG, |
| 1615 | BIT(2), 1); |
| 1616 | |
| 1617 | /* |
| 1618 | * Enable master clock for RAMs to allow BAM to access RAMs when |
| 1619 | * RAM clock gating is enabled via DWC3's GCTL. Otherwise issues |
| 1620 | * are seen where RAM clocks get turned OFF in SS mode |
| 1621 | */ |
| 1622 | dwc3_msm_write_reg(mdwc->base, CGCTL_REG, |
| 1623 | dwc3_msm_read_reg(mdwc->base, CGCTL_REG) | 0x18); |
| 1624 | |
| 1625 | } |
| 1626 | |
Jack Pham | 4b8b4ae | 2016-08-09 11:36:34 -0700 | [diff] [blame] | 1627 | static void dwc3_msm_vbus_draw_work(struct work_struct *w) |
| 1628 | { |
| 1629 | struct dwc3_msm *mdwc = container_of(w, struct dwc3_msm, |
| 1630 | vbus_draw_work); |
| 1631 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
| 1632 | |
| 1633 | dwc3_msm_gadget_vbus_draw(mdwc, dwc->vbus_draw); |
| 1634 | } |
| 1635 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1636 | static void dwc3_msm_notify_event(struct dwc3 *dwc, unsigned int event) |
| 1637 | { |
| 1638 | struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent); |
Mayank Rana | f4918d3 | 2016-12-15 13:35:55 -0800 | [diff] [blame] | 1639 | struct dwc3_event_buffer *evt; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1640 | u32 reg; |
Mayank Rana | f4918d3 | 2016-12-15 13:35:55 -0800 | [diff] [blame] | 1641 | int i; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1642 | |
| 1643 | switch (event) { |
| 1644 | case DWC3_CONTROLLER_ERROR_EVENT: |
| 1645 | dev_info(mdwc->dev, |
| 1646 | "DWC3_CONTROLLER_ERROR_EVENT received, irq cnt %lu\n", |
| 1647 | dwc->irq_cnt); |
| 1648 | |
| 1649 | dwc3_gadget_disable_irq(dwc); |
| 1650 | |
| 1651 | /* prevent core from generating interrupts until recovery */ |
| 1652 | reg = dwc3_msm_read_reg(mdwc->base, DWC3_GCTL); |
| 1653 | reg |= DWC3_GCTL_CORESOFTRESET; |
| 1654 | dwc3_msm_write_reg(mdwc->base, DWC3_GCTL, reg); |
| 1655 | |
| 1656 | /* restart USB which performs full reset and reconnect */ |
| 1657 | schedule_work(&mdwc->restart_usb_work); |
| 1658 | break; |
| 1659 | case DWC3_CONTROLLER_RESET_EVENT: |
| 1660 | dev_dbg(mdwc->dev, "DWC3_CONTROLLER_RESET_EVENT received\n"); |
| 1661 | /* HS & SSPHYs get reset as part of core soft reset */ |
| 1662 | dwc3_msm_qscratch_reg_init(mdwc); |
| 1663 | break; |
| 1664 | case DWC3_CONTROLLER_POST_RESET_EVENT: |
| 1665 | dev_dbg(mdwc->dev, |
| 1666 | "DWC3_CONTROLLER_POST_RESET_EVENT received\n"); |
| 1667 | |
| 1668 | /* |
| 1669 | * Below sequence is used when controller is working without |
| 1670 | * having ssphy and only USB high speed is supported. |
| 1671 | */ |
| 1672 | if (dwc->maximum_speed == USB_SPEED_HIGH) { |
| 1673 | dwc3_msm_write_reg(mdwc->base, QSCRATCH_GENERAL_CFG, |
| 1674 | dwc3_msm_read_reg(mdwc->base, |
| 1675 | QSCRATCH_GENERAL_CFG) |
| 1676 | | PIPE_UTMI_CLK_DIS); |
| 1677 | |
| 1678 | usleep_range(2, 5); |
| 1679 | |
| 1680 | |
| 1681 | dwc3_msm_write_reg(mdwc->base, QSCRATCH_GENERAL_CFG, |
| 1682 | dwc3_msm_read_reg(mdwc->base, |
| 1683 | QSCRATCH_GENERAL_CFG) |
| 1684 | | PIPE_UTMI_CLK_SEL |
| 1685 | | PIPE3_PHYSTATUS_SW); |
| 1686 | |
| 1687 | usleep_range(2, 5); |
| 1688 | |
| 1689 | dwc3_msm_write_reg(mdwc->base, QSCRATCH_GENERAL_CFG, |
| 1690 | dwc3_msm_read_reg(mdwc->base, |
| 1691 | QSCRATCH_GENERAL_CFG) |
| 1692 | & ~PIPE_UTMI_CLK_DIS); |
| 1693 | } |
| 1694 | |
| 1695 | dwc3_msm_update_ref_clk(mdwc); |
| 1696 | dwc->tx_fifo_size = mdwc->tx_fifo_size; |
| 1697 | break; |
| 1698 | case DWC3_CONTROLLER_CONNDONE_EVENT: |
| 1699 | dev_dbg(mdwc->dev, "DWC3_CONTROLLER_CONNDONE_EVENT received\n"); |
| 1700 | /* |
| 1701 | * Add power event if the dbm indicates coming out of L1 by |
| 1702 | * interrupt |
| 1703 | */ |
| 1704 | if (mdwc->dbm && dbm_l1_lpm_interrupt(mdwc->dbm)) |
| 1705 | dwc3_msm_write_reg_field(mdwc->base, |
| 1706 | PWR_EVNT_IRQ_MASK_REG, |
| 1707 | PWR_EVNT_LPM_OUT_L1_MASK, 1); |
| 1708 | |
| 1709 | atomic_set(&dwc->in_lpm, 0); |
| 1710 | break; |
| 1711 | case DWC3_CONTROLLER_NOTIFY_OTG_EVENT: |
| 1712 | dev_dbg(mdwc->dev, "DWC3_CONTROLLER_NOTIFY_OTG_EVENT received\n"); |
| 1713 | if (dwc->enable_bus_suspend) { |
| 1714 | mdwc->suspend = dwc->b_suspend; |
| 1715 | queue_work(mdwc->dwc3_wq, &mdwc->resume_work); |
| 1716 | } |
| 1717 | break; |
| 1718 | case DWC3_CONTROLLER_SET_CURRENT_DRAW_EVENT: |
| 1719 | dev_dbg(mdwc->dev, "DWC3_CONTROLLER_SET_CURRENT_DRAW_EVENT received\n"); |
Jack Pham | 4b8b4ae | 2016-08-09 11:36:34 -0700 | [diff] [blame] | 1720 | schedule_work(&mdwc->vbus_draw_work); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1721 | break; |
| 1722 | case DWC3_CONTROLLER_RESTART_USB_SESSION: |
| 1723 | dev_dbg(mdwc->dev, "DWC3_CONTROLLER_RESTART_USB_SESSION received\n"); |
Hemant Kumar | 4387417 | 2016-08-25 16:17:48 -0700 | [diff] [blame] | 1724 | schedule_work(&mdwc->restart_usb_work); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1725 | break; |
Mayank Rana | f4918d3 | 2016-12-15 13:35:55 -0800 | [diff] [blame] | 1726 | case DWC3_GSI_EVT_BUF_ALLOC: |
| 1727 | dev_dbg(mdwc->dev, "DWC3_GSI_EVT_BUF_ALLOC\n"); |
| 1728 | |
| 1729 | if (!mdwc->num_gsi_event_buffers) |
| 1730 | break; |
| 1731 | |
| 1732 | mdwc->gsi_ev_buff = devm_kzalloc(dwc->dev, |
| 1733 | sizeof(*dwc->ev_buf) * mdwc->num_gsi_event_buffers, |
| 1734 | GFP_KERNEL); |
| 1735 | if (!mdwc->gsi_ev_buff) { |
| 1736 | dev_err(dwc->dev, "can't allocate gsi_ev_buff\n"); |
| 1737 | break; |
| 1738 | } |
| 1739 | |
| 1740 | for (i = 0; i < mdwc->num_gsi_event_buffers; i++) { |
| 1741 | |
| 1742 | evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); |
| 1743 | if (!evt) |
| 1744 | break; |
| 1745 | evt->dwc = dwc; |
| 1746 | evt->length = DWC3_EVENT_BUFFERS_SIZE; |
| 1747 | evt->buf = dma_alloc_coherent(dwc->dev, |
| 1748 | DWC3_EVENT_BUFFERS_SIZE, |
| 1749 | &evt->dma, GFP_KERNEL); |
| 1750 | if (!evt->buf) { |
| 1751 | dev_err(dwc->dev, |
| 1752 | "can't allocate gsi_evt_buf(%d)\n", i); |
| 1753 | break; |
| 1754 | } |
| 1755 | mdwc->gsi_ev_buff[i] = evt; |
| 1756 | } |
| 1757 | break; |
| 1758 | case DWC3_GSI_EVT_BUF_SETUP: |
| 1759 | dev_dbg(mdwc->dev, "DWC3_GSI_EVT_BUF_SETUP\n"); |
| 1760 | for (i = 0; i < mdwc->num_gsi_event_buffers; i++) { |
| 1761 | evt = mdwc->gsi_ev_buff[i]; |
| 1762 | dev_dbg(mdwc->dev, "Evt buf %p dma %08llx length %d\n", |
| 1763 | evt->buf, (unsigned long long) evt->dma, |
| 1764 | evt->length); |
| 1765 | memset(evt->buf, 0, evt->length); |
| 1766 | evt->lpos = 0; |
| 1767 | /* |
| 1768 | * Primary event buffer is programmed with registers |
| 1769 | * DWC3_GEVNT*(0). Hence use DWC3_GEVNT*(i+1) to |
| 1770 | * program USB GSI related event buffer with DWC3 |
| 1771 | * controller. |
| 1772 | */ |
| 1773 | dwc3_writel(dwc->regs, DWC3_GEVNTADRLO((i+1)), |
| 1774 | lower_32_bits(evt->dma)); |
| 1775 | dwc3_writel(dwc->regs, DWC3_GEVNTADRHI((i+1)), |
| 1776 | DWC3_GEVNTADRHI_EVNTADRHI_GSI_EN( |
| 1777 | DWC3_GEVENT_TYPE_GSI) | |
| 1778 | DWC3_GEVNTADRHI_EVNTADRHI_GSI_IDX((i+1))); |
| 1779 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ((i+1)), |
| 1780 | DWC3_GEVNTCOUNT_EVNTINTRPTMASK | |
| 1781 | ((evt->length) & 0xffff)); |
| 1782 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT((i+1)), 0); |
| 1783 | } |
| 1784 | break; |
| 1785 | case DWC3_GSI_EVT_BUF_CLEANUP: |
| 1786 | dev_dbg(mdwc->dev, "DWC3_GSI_EVT_BUF_CLEANUP\n"); |
| 1787 | for (i = 0; i < mdwc->num_gsi_event_buffers; i++) { |
| 1788 | evt = mdwc->gsi_ev_buff[i]; |
| 1789 | evt->lpos = 0; |
| 1790 | /* |
| 1791 | * Primary event buffer is programmed with registers |
| 1792 | * DWC3_GEVNT*(0). Hence use DWC3_GEVNT*(i+1) to |
| 1793 | * program USB GSI related event buffer with DWC3 |
| 1794 | * controller. |
| 1795 | */ |
| 1796 | dwc3_writel(dwc->regs, DWC3_GEVNTADRLO((i+1)), 0); |
| 1797 | dwc3_writel(dwc->regs, DWC3_GEVNTADRHI((i+1)), 0); |
| 1798 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ((i+1)), |
| 1799 | DWC3_GEVNTSIZ_INTMASK | |
| 1800 | DWC3_GEVNTSIZ_SIZE((i+1))); |
| 1801 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT((i+1)), 0); |
| 1802 | } |
| 1803 | break; |
| 1804 | case DWC3_GSI_EVT_BUF_FREE: |
| 1805 | dev_dbg(mdwc->dev, "DWC3_GSI_EVT_BUF_FREE\n"); |
| 1806 | for (i = 0; i < mdwc->num_gsi_event_buffers; i++) { |
| 1807 | evt = mdwc->gsi_ev_buff[i]; |
| 1808 | if (evt) |
| 1809 | dma_free_coherent(dwc->dev, evt->length, |
| 1810 | evt->buf, evt->dma); |
| 1811 | } |
| 1812 | break; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1813 | default: |
| 1814 | dev_dbg(mdwc->dev, "unknown dwc3 event\n"); |
| 1815 | break; |
| 1816 | } |
| 1817 | } |
| 1818 | |
| 1819 | static void dwc3_msm_block_reset(struct dwc3_msm *mdwc, bool core_reset) |
| 1820 | { |
| 1821 | int ret = 0; |
| 1822 | |
| 1823 | if (core_reset) { |
| 1824 | ret = dwc3_msm_link_clk_reset(mdwc, 1); |
| 1825 | if (ret) |
| 1826 | return; |
| 1827 | |
| 1828 | usleep_range(1000, 1200); |
| 1829 | ret = dwc3_msm_link_clk_reset(mdwc, 0); |
| 1830 | if (ret) |
| 1831 | return; |
| 1832 | |
| 1833 | usleep_range(10000, 12000); |
| 1834 | } |
| 1835 | |
| 1836 | if (mdwc->dbm) { |
| 1837 | /* Reset the DBM */ |
| 1838 | dbm_soft_reset(mdwc->dbm, 1); |
| 1839 | usleep_range(1000, 1200); |
| 1840 | dbm_soft_reset(mdwc->dbm, 0); |
| 1841 | |
| 1842 | /*enable DBM*/ |
| 1843 | dwc3_msm_write_reg_field(mdwc->base, QSCRATCH_GENERAL_CFG, |
| 1844 | DBM_EN_MASK, 0x1); |
| 1845 | dbm_enable(mdwc->dbm); |
| 1846 | } |
| 1847 | } |
| 1848 | |
| 1849 | static void dwc3_msm_power_collapse_por(struct dwc3_msm *mdwc) |
| 1850 | { |
| 1851 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
| 1852 | u32 val; |
| 1853 | |
| 1854 | /* Configure AHB2PHY for one wait state read/write */ |
| 1855 | if (mdwc->ahb2phy_base) { |
| 1856 | clk_prepare_enable(mdwc->cfg_ahb_clk); |
| 1857 | val = readl_relaxed(mdwc->ahb2phy_base + |
| 1858 | PERIPH_SS_AHB2PHY_TOP_CFG); |
| 1859 | if (val != ONE_READ_WRITE_WAIT) { |
| 1860 | writel_relaxed(ONE_READ_WRITE_WAIT, |
| 1861 | mdwc->ahb2phy_base + PERIPH_SS_AHB2PHY_TOP_CFG); |
| 1862 | /* complete above write before configuring USB PHY. */ |
| 1863 | mb(); |
| 1864 | } |
| 1865 | clk_disable_unprepare(mdwc->cfg_ahb_clk); |
| 1866 | } |
| 1867 | |
| 1868 | if (!mdwc->init) { |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1869 | dwc3_core_pre_init(dwc); |
| 1870 | mdwc->init = true; |
| 1871 | } |
| 1872 | |
| 1873 | dwc3_core_init(dwc); |
| 1874 | /* Re-configure event buffers */ |
| 1875 | dwc3_event_buffers_setup(dwc); |
| 1876 | } |
| 1877 | |
| 1878 | static int dwc3_msm_prepare_suspend(struct dwc3_msm *mdwc) |
| 1879 | { |
| 1880 | unsigned long timeout; |
| 1881 | u32 reg = 0; |
| 1882 | |
| 1883 | if ((mdwc->in_host_mode || mdwc->vbus_active) |
Vijayavardhan Vennapusa | 8cf91a6 | 2016-09-01 12:05:50 +0530 | [diff] [blame] | 1884 | && dwc3_msm_is_superspeed(mdwc) && !mdwc->in_restart) { |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1885 | if (!atomic_read(&mdwc->in_p3)) { |
| 1886 | dev_err(mdwc->dev, "Not in P3,aborting LPM sequence\n"); |
| 1887 | return -EBUSY; |
| 1888 | } |
| 1889 | } |
| 1890 | |
| 1891 | /* Clear previous L2 events */ |
| 1892 | dwc3_msm_write_reg(mdwc->base, PWR_EVNT_IRQ_STAT_REG, |
| 1893 | PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK); |
| 1894 | |
| 1895 | /* Prepare HSPHY for suspend */ |
| 1896 | reg = dwc3_msm_read_reg(mdwc->base, DWC3_GUSB2PHYCFG(0)); |
| 1897 | dwc3_msm_write_reg(mdwc->base, DWC3_GUSB2PHYCFG(0), |
| 1898 | reg | DWC3_GUSB2PHYCFG_ENBLSLPM | DWC3_GUSB2PHYCFG_SUSPHY); |
| 1899 | |
| 1900 | /* Wait for PHY to go into L2 */ |
| 1901 | timeout = jiffies + msecs_to_jiffies(5); |
| 1902 | while (!time_after(jiffies, timeout)) { |
| 1903 | reg = dwc3_msm_read_reg(mdwc->base, PWR_EVNT_IRQ_STAT_REG); |
| 1904 | if (reg & PWR_EVNT_LPM_IN_L2_MASK) |
| 1905 | break; |
| 1906 | } |
| 1907 | if (!(reg & PWR_EVNT_LPM_IN_L2_MASK)) |
| 1908 | dev_err(mdwc->dev, "could not transition HS PHY to L2\n"); |
| 1909 | |
| 1910 | /* Clear L2 event bit */ |
| 1911 | dwc3_msm_write_reg(mdwc->base, PWR_EVNT_IRQ_STAT_REG, |
| 1912 | PWR_EVNT_LPM_IN_L2_MASK); |
| 1913 | |
| 1914 | return 0; |
| 1915 | } |
| 1916 | |
| 1917 | static void dwc3_msm_bus_vote_w(struct work_struct *w) |
| 1918 | { |
| 1919 | struct dwc3_msm *mdwc = container_of(w, struct dwc3_msm, bus_vote_w); |
| 1920 | int ret; |
| 1921 | |
| 1922 | ret = msm_bus_scale_client_update_request(mdwc->bus_perf_client, |
| 1923 | mdwc->bus_vote); |
| 1924 | if (ret) |
| 1925 | dev_err(mdwc->dev, "Failed to reset bus bw vote %d\n", ret); |
| 1926 | } |
| 1927 | |
| 1928 | static void dwc3_set_phy_speed_flags(struct dwc3_msm *mdwc) |
| 1929 | { |
| 1930 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
| 1931 | int i, num_ports; |
| 1932 | u32 reg; |
| 1933 | |
| 1934 | mdwc->hs_phy->flags &= ~(PHY_HSFS_MODE | PHY_LS_MODE); |
| 1935 | if (mdwc->in_host_mode) { |
| 1936 | reg = dwc3_msm_read_reg(mdwc->base, USB3_HCSPARAMS1); |
| 1937 | num_ports = HCS_MAX_PORTS(reg); |
| 1938 | for (i = 0; i < num_ports; i++) { |
| 1939 | reg = dwc3_msm_read_reg(mdwc->base, |
| 1940 | USB3_PORTSC + i*0x10); |
| 1941 | if (reg & PORT_PE) { |
| 1942 | if (DEV_HIGHSPEED(reg) || DEV_FULLSPEED(reg)) |
| 1943 | mdwc->hs_phy->flags |= PHY_HSFS_MODE; |
| 1944 | else if (DEV_LOWSPEED(reg)) |
| 1945 | mdwc->hs_phy->flags |= PHY_LS_MODE; |
| 1946 | } |
| 1947 | } |
| 1948 | } else { |
| 1949 | if (dwc->gadget.speed == USB_SPEED_HIGH || |
| 1950 | dwc->gadget.speed == USB_SPEED_FULL) |
| 1951 | mdwc->hs_phy->flags |= PHY_HSFS_MODE; |
| 1952 | else if (dwc->gadget.speed == USB_SPEED_LOW) |
| 1953 | mdwc->hs_phy->flags |= PHY_LS_MODE; |
| 1954 | } |
| 1955 | } |
| 1956 | |
| 1957 | |
| 1958 | static int dwc3_msm_suspend(struct dwc3_msm *mdwc) |
| 1959 | { |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 1960 | int ret; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1961 | bool can_suspend_ssphy; |
| 1962 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 1963 | struct dwc3_event_buffer *evt; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1964 | |
| 1965 | if (atomic_read(&dwc->in_lpm)) { |
| 1966 | dev_dbg(mdwc->dev, "%s: Already suspended\n", __func__); |
| 1967 | return 0; |
| 1968 | } |
| 1969 | |
| 1970 | if (!mdwc->in_host_mode) { |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 1971 | evt = dwc->ev_buf; |
| 1972 | if ((evt->flags & DWC3_EVENT_PENDING)) { |
| 1973 | dev_dbg(mdwc->dev, |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1974 | "%s: %d device events pending, abort suspend\n", |
| 1975 | __func__, evt->count / 4); |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 1976 | return -EBUSY; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1977 | } |
| 1978 | } |
| 1979 | |
| 1980 | if (!mdwc->vbus_active && dwc->is_drd && |
| 1981 | mdwc->otg_state == OTG_STATE_B_PERIPHERAL) { |
| 1982 | /* |
| 1983 | * In some cases, the pm_runtime_suspend may be called by |
| 1984 | * usb_bam when there is pending lpm flag. However, if this is |
| 1985 | * done when cable was disconnected and otg state has not |
| 1986 | * yet changed to IDLE, then it means OTG state machine |
| 1987 | * is running and we race against it. So cancel LPM for now, |
| 1988 | * and OTG state machine will go for LPM later, after completing |
| 1989 | * transition to IDLE state. |
| 1990 | */ |
| 1991 | dev_dbg(mdwc->dev, |
| 1992 | "%s: cable disconnected while not in idle otg state\n", |
| 1993 | __func__); |
| 1994 | return -EBUSY; |
| 1995 | } |
| 1996 | |
| 1997 | /* |
| 1998 | * Check if device is not in CONFIGURED state |
| 1999 | * then check controller state of L2 and break |
| 2000 | * LPM sequence. Check this for device bus suspend case. |
| 2001 | */ |
| 2002 | if ((dwc->is_drd && mdwc->otg_state == OTG_STATE_B_SUSPEND) && |
| 2003 | (dwc->gadget.state != USB_STATE_CONFIGURED)) { |
| 2004 | pr_err("%s(): Trying to go in LPM with state:%d\n", |
| 2005 | __func__, dwc->gadget.state); |
| 2006 | pr_err("%s(): LPM is not performed.\n", __func__); |
| 2007 | return -EBUSY; |
| 2008 | } |
| 2009 | |
| 2010 | ret = dwc3_msm_prepare_suspend(mdwc); |
| 2011 | if (ret) |
| 2012 | return ret; |
| 2013 | |
| 2014 | /* Initialize variables here */ |
| 2015 | can_suspend_ssphy = !(mdwc->in_host_mode && |
| 2016 | dwc3_msm_is_host_superspeed(mdwc)); |
| 2017 | |
| 2018 | /* Disable core irq */ |
| 2019 | if (dwc->irq) |
| 2020 | disable_irq(dwc->irq); |
| 2021 | |
| 2022 | /* disable power event irq, hs and ss phy irq is used as wake up src */ |
| 2023 | disable_irq(mdwc->pwr_event_irq); |
| 2024 | |
| 2025 | dwc3_set_phy_speed_flags(mdwc); |
| 2026 | /* Suspend HS PHY */ |
| 2027 | usb_phy_set_suspend(mdwc->hs_phy, 1); |
| 2028 | |
| 2029 | /* Suspend SS PHY */ |
Hemant Kumar | de1df69 | 2016-04-26 19:36:48 -0700 | [diff] [blame] | 2030 | if (dwc->maximum_speed == USB_SPEED_SUPER && can_suspend_ssphy) { |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2031 | /* indicate phy about SS mode */ |
| 2032 | if (dwc3_msm_is_superspeed(mdwc)) |
| 2033 | mdwc->ss_phy->flags |= DEVICE_IN_SS_MODE; |
| 2034 | usb_phy_set_suspend(mdwc->ss_phy, 1); |
| 2035 | mdwc->lpm_flags |= MDWC3_SS_PHY_SUSPEND; |
| 2036 | } |
| 2037 | |
| 2038 | /* make sure above writes are completed before turning off clocks */ |
| 2039 | wmb(); |
| 2040 | |
| 2041 | /* Disable clocks */ |
| 2042 | if (mdwc->bus_aggr_clk) |
| 2043 | clk_disable_unprepare(mdwc->bus_aggr_clk); |
| 2044 | clk_disable_unprepare(mdwc->utmi_clk); |
| 2045 | |
Hemant Kumar | 633dc33 | 2016-08-10 13:41:05 -0700 | [diff] [blame] | 2046 | /* Memory core: OFF, Memory periphery: OFF */ |
| 2047 | if (!mdwc->in_host_mode && !mdwc->vbus_active) { |
| 2048 | clk_set_flags(mdwc->core_clk, CLKFLAG_NORETAIN_MEM); |
| 2049 | clk_set_flags(mdwc->core_clk, CLKFLAG_NORETAIN_PERIPH); |
| 2050 | } |
| 2051 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2052 | clk_set_rate(mdwc->core_clk, 19200000); |
| 2053 | clk_disable_unprepare(mdwc->core_clk); |
Vijayavardhan Vennapusa | 934d9cd | 2016-11-30 13:10:01 +0530 | [diff] [blame] | 2054 | if (mdwc->noc_aggr_clk) |
| 2055 | clk_disable_unprepare(mdwc->noc_aggr_clk); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2056 | /* |
| 2057 | * Disable iface_clk only after core_clk as core_clk has FSM |
| 2058 | * depedency on iface_clk. Hence iface_clk should be turned off |
| 2059 | * after core_clk is turned off. |
| 2060 | */ |
| 2061 | clk_disable_unprepare(mdwc->iface_clk); |
| 2062 | /* USB PHY no more requires TCXO */ |
| 2063 | clk_disable_unprepare(mdwc->xo_clk); |
| 2064 | |
| 2065 | /* Perform controller power collapse */ |
| 2066 | if (!mdwc->in_host_mode && !mdwc->vbus_active) { |
| 2067 | mdwc->lpm_flags |= MDWC3_POWER_COLLAPSE; |
| 2068 | dev_dbg(mdwc->dev, "%s: power collapse\n", __func__); |
| 2069 | dwc3_msm_config_gdsc(mdwc, 0); |
| 2070 | clk_disable_unprepare(mdwc->sleep_clk); |
| 2071 | } |
| 2072 | |
| 2073 | /* Remove bus voting */ |
| 2074 | if (mdwc->bus_perf_client) { |
| 2075 | mdwc->bus_vote = 0; |
| 2076 | schedule_work(&mdwc->bus_vote_w); |
| 2077 | } |
| 2078 | |
| 2079 | /* |
| 2080 | * release wakeup source with timeout to defer system suspend to |
| 2081 | * handle case where on USB cable disconnect, SUSPEND and DISCONNECT |
| 2082 | * event is received. |
| 2083 | */ |
| 2084 | if (mdwc->lpm_to_suspend_delay) { |
| 2085 | dev_dbg(mdwc->dev, "defer suspend with %d(msecs)\n", |
| 2086 | mdwc->lpm_to_suspend_delay); |
| 2087 | pm_wakeup_event(mdwc->dev, mdwc->lpm_to_suspend_delay); |
| 2088 | } else { |
| 2089 | pm_relax(mdwc->dev); |
| 2090 | } |
| 2091 | |
| 2092 | atomic_set(&dwc->in_lpm, 1); |
| 2093 | |
| 2094 | /* |
| 2095 | * with DCP or during cable disconnect, we dont require wakeup |
| 2096 | * using HS_PHY_IRQ or SS_PHY_IRQ. Hence enable wakeup only in |
| 2097 | * case of host bus suspend and device bus suspend. |
| 2098 | */ |
| 2099 | if (mdwc->vbus_active || mdwc->in_host_mode) { |
| 2100 | enable_irq_wake(mdwc->hs_phy_irq); |
| 2101 | enable_irq(mdwc->hs_phy_irq); |
| 2102 | if (mdwc->ss_phy_irq) { |
| 2103 | enable_irq_wake(mdwc->ss_phy_irq); |
| 2104 | enable_irq(mdwc->ss_phy_irq); |
| 2105 | } |
| 2106 | /* |
| 2107 | * Enable power event irq during bus suspend in host mode for |
| 2108 | * mapping MPM pin for DP so that wakeup can happen in system |
| 2109 | * suspend. |
| 2110 | */ |
| 2111 | if (mdwc->in_host_mode) { |
| 2112 | enable_irq(mdwc->pwr_event_irq); |
| 2113 | enable_irq_wake(mdwc->pwr_event_irq); |
| 2114 | } |
| 2115 | mdwc->lpm_flags |= MDWC3_ASYNC_IRQ_WAKE_CAPABILITY; |
| 2116 | } |
| 2117 | |
| 2118 | dev_info(mdwc->dev, "DWC3 in low power mode\n"); |
| 2119 | return 0; |
| 2120 | } |
| 2121 | |
| 2122 | static int dwc3_msm_resume(struct dwc3_msm *mdwc) |
| 2123 | { |
| 2124 | int ret; |
Hemant Kumar | 8e4c2f2 | 2017-01-24 18:13:07 -0800 | [diff] [blame] | 2125 | long core_clk_rate; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2126 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
| 2127 | |
| 2128 | dev_dbg(mdwc->dev, "%s: exiting lpm\n", __func__); |
| 2129 | |
| 2130 | if (!atomic_read(&dwc->in_lpm)) { |
| 2131 | dev_dbg(mdwc->dev, "%s: Already resumed\n", __func__); |
| 2132 | return 0; |
| 2133 | } |
| 2134 | |
| 2135 | pm_stay_awake(mdwc->dev); |
| 2136 | |
| 2137 | /* Enable bus voting */ |
| 2138 | if (mdwc->bus_perf_client) { |
| 2139 | mdwc->bus_vote = 1; |
| 2140 | schedule_work(&mdwc->bus_vote_w); |
| 2141 | } |
| 2142 | |
| 2143 | /* Vote for TCXO while waking up USB HSPHY */ |
| 2144 | ret = clk_prepare_enable(mdwc->xo_clk); |
| 2145 | if (ret) |
| 2146 | dev_err(mdwc->dev, "%s failed to vote TCXO buffer%d\n", |
| 2147 | __func__, ret); |
| 2148 | |
| 2149 | /* Restore controller power collapse */ |
| 2150 | if (mdwc->lpm_flags & MDWC3_POWER_COLLAPSE) { |
| 2151 | dev_dbg(mdwc->dev, "%s: exit power collapse\n", __func__); |
| 2152 | dwc3_msm_config_gdsc(mdwc, 1); |
Amit Nischal | 4d27821 | 2016-06-06 17:54:34 +0530 | [diff] [blame] | 2153 | ret = reset_control_assert(mdwc->core_reset); |
| 2154 | if (ret) |
| 2155 | dev_err(mdwc->dev, "%s:core_reset assert failed\n", |
| 2156 | __func__); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2157 | /* HW requires a short delay for reset to take place properly */ |
| 2158 | usleep_range(1000, 1200); |
Amit Nischal | 4d27821 | 2016-06-06 17:54:34 +0530 | [diff] [blame] | 2159 | ret = reset_control_deassert(mdwc->core_reset); |
| 2160 | if (ret) |
| 2161 | dev_err(mdwc->dev, "%s:core_reset deassert failed\n", |
| 2162 | __func__); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2163 | clk_prepare_enable(mdwc->sleep_clk); |
| 2164 | } |
| 2165 | |
| 2166 | /* |
| 2167 | * Enable clocks |
| 2168 | * Turned ON iface_clk before core_clk due to FSM depedency. |
| 2169 | */ |
| 2170 | clk_prepare_enable(mdwc->iface_clk); |
Vijayavardhan Vennapusa | 934d9cd | 2016-11-30 13:10:01 +0530 | [diff] [blame] | 2171 | if (mdwc->noc_aggr_clk) |
| 2172 | clk_prepare_enable(mdwc->noc_aggr_clk); |
Hemant Kumar | 8e4c2f2 | 2017-01-24 18:13:07 -0800 | [diff] [blame] | 2173 | |
| 2174 | core_clk_rate = mdwc->core_clk_rate; |
| 2175 | if (mdwc->in_host_mode && mdwc->max_rh_port_speed == USB_SPEED_HIGH) { |
| 2176 | core_clk_rate = mdwc->core_clk_rate_hs; |
| 2177 | dev_dbg(mdwc->dev, "%s: set hs core clk rate %ld\n", __func__, |
| 2178 | core_clk_rate); |
| 2179 | } |
| 2180 | |
| 2181 | clk_set_rate(mdwc->core_clk, core_clk_rate); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2182 | clk_prepare_enable(mdwc->core_clk); |
Hemant Kumar | 5fa3893 | 2016-10-27 11:58:37 -0700 | [diff] [blame] | 2183 | |
| 2184 | /* set Memory core: ON, Memory periphery: ON */ |
| 2185 | clk_set_flags(mdwc->core_clk, CLKFLAG_RETAIN_MEM); |
| 2186 | clk_set_flags(mdwc->core_clk, CLKFLAG_RETAIN_PERIPH); |
| 2187 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2188 | clk_prepare_enable(mdwc->utmi_clk); |
| 2189 | if (mdwc->bus_aggr_clk) |
| 2190 | clk_prepare_enable(mdwc->bus_aggr_clk); |
| 2191 | |
| 2192 | /* Resume SS PHY */ |
Hemant Kumar | de1df69 | 2016-04-26 19:36:48 -0700 | [diff] [blame] | 2193 | if (dwc->maximum_speed == USB_SPEED_SUPER && |
| 2194 | mdwc->lpm_flags & MDWC3_SS_PHY_SUSPEND) { |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2195 | mdwc->ss_phy->flags &= ~(PHY_LANE_A | PHY_LANE_B); |
| 2196 | if (mdwc->typec_orientation == ORIENTATION_CC1) |
| 2197 | mdwc->ss_phy->flags |= PHY_LANE_A; |
| 2198 | if (mdwc->typec_orientation == ORIENTATION_CC2) |
| 2199 | mdwc->ss_phy->flags |= PHY_LANE_B; |
| 2200 | usb_phy_set_suspend(mdwc->ss_phy, 0); |
| 2201 | mdwc->ss_phy->flags &= ~DEVICE_IN_SS_MODE; |
| 2202 | mdwc->lpm_flags &= ~MDWC3_SS_PHY_SUSPEND; |
| 2203 | } |
| 2204 | |
| 2205 | mdwc->hs_phy->flags &= ~(PHY_HSFS_MODE | PHY_LS_MODE); |
| 2206 | /* Resume HS PHY */ |
| 2207 | usb_phy_set_suspend(mdwc->hs_phy, 0); |
| 2208 | |
| 2209 | /* Recover from controller power collapse */ |
| 2210 | if (mdwc->lpm_flags & MDWC3_POWER_COLLAPSE) { |
| 2211 | u32 tmp; |
| 2212 | |
| 2213 | dev_dbg(mdwc->dev, "%s: exit power collapse\n", __func__); |
| 2214 | |
| 2215 | dwc3_msm_power_collapse_por(mdwc); |
| 2216 | |
| 2217 | /* Get initial P3 status and enable IN_P3 event */ |
| 2218 | tmp = dwc3_msm_read_reg_field(mdwc->base, |
| 2219 | DWC3_GDBGLTSSM, DWC3_GDBGLTSSM_LINKSTATE_MASK); |
| 2220 | atomic_set(&mdwc->in_p3, tmp == DWC3_LINK_STATE_U3); |
| 2221 | dwc3_msm_write_reg_field(mdwc->base, PWR_EVNT_IRQ_MASK_REG, |
| 2222 | PWR_EVNT_POWERDOWN_IN_P3_MASK, 1); |
| 2223 | |
| 2224 | mdwc->lpm_flags &= ~MDWC3_POWER_COLLAPSE; |
| 2225 | } |
| 2226 | |
| 2227 | atomic_set(&dwc->in_lpm, 0); |
| 2228 | |
| 2229 | /* Disable HSPHY auto suspend */ |
| 2230 | dwc3_msm_write_reg(mdwc->base, DWC3_GUSB2PHYCFG(0), |
| 2231 | dwc3_msm_read_reg(mdwc->base, DWC3_GUSB2PHYCFG(0)) & |
| 2232 | ~(DWC3_GUSB2PHYCFG_ENBLSLPM | |
| 2233 | DWC3_GUSB2PHYCFG_SUSPHY)); |
| 2234 | |
| 2235 | /* Disable wakeup capable for HS_PHY IRQ & SS_PHY_IRQ if enabled */ |
| 2236 | if (mdwc->lpm_flags & MDWC3_ASYNC_IRQ_WAKE_CAPABILITY) { |
| 2237 | disable_irq_wake(mdwc->hs_phy_irq); |
| 2238 | disable_irq_nosync(mdwc->hs_phy_irq); |
| 2239 | if (mdwc->ss_phy_irq) { |
| 2240 | disable_irq_wake(mdwc->ss_phy_irq); |
| 2241 | disable_irq_nosync(mdwc->ss_phy_irq); |
| 2242 | } |
| 2243 | if (mdwc->in_host_mode) { |
| 2244 | disable_irq_wake(mdwc->pwr_event_irq); |
| 2245 | disable_irq(mdwc->pwr_event_irq); |
| 2246 | } |
| 2247 | mdwc->lpm_flags &= ~MDWC3_ASYNC_IRQ_WAKE_CAPABILITY; |
| 2248 | } |
| 2249 | |
| 2250 | dev_info(mdwc->dev, "DWC3 exited from low power mode\n"); |
| 2251 | |
| 2252 | /* enable power evt irq for IN P3 detection */ |
| 2253 | enable_irq(mdwc->pwr_event_irq); |
| 2254 | |
| 2255 | /* Enable core irq */ |
| 2256 | if (dwc->irq) |
| 2257 | enable_irq(dwc->irq); |
| 2258 | |
| 2259 | /* |
| 2260 | * Handle other power events that could not have been handled during |
| 2261 | * Low Power Mode |
| 2262 | */ |
| 2263 | dwc3_pwr_event_handler(mdwc); |
| 2264 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2265 | return 0; |
| 2266 | } |
| 2267 | |
| 2268 | /** |
| 2269 | * dwc3_ext_event_notify - callback to handle events from external transceiver |
| 2270 | * |
| 2271 | * Returns 0 on success |
| 2272 | */ |
| 2273 | static void dwc3_ext_event_notify(struct dwc3_msm *mdwc) |
| 2274 | { |
| 2275 | /* Flush processing any pending events before handling new ones */ |
| 2276 | flush_delayed_work(&mdwc->sm_work); |
| 2277 | |
| 2278 | if (mdwc->id_state == DWC3_ID_FLOAT) { |
| 2279 | dev_dbg(mdwc->dev, "XCVR: ID set\n"); |
| 2280 | set_bit(ID, &mdwc->inputs); |
| 2281 | } else { |
| 2282 | dev_dbg(mdwc->dev, "XCVR: ID clear\n"); |
| 2283 | clear_bit(ID, &mdwc->inputs); |
| 2284 | } |
| 2285 | |
| 2286 | if (mdwc->vbus_active && !mdwc->in_restart) { |
| 2287 | dev_dbg(mdwc->dev, "XCVR: BSV set\n"); |
| 2288 | set_bit(B_SESS_VLD, &mdwc->inputs); |
| 2289 | } else { |
| 2290 | dev_dbg(mdwc->dev, "XCVR: BSV clear\n"); |
| 2291 | clear_bit(B_SESS_VLD, &mdwc->inputs); |
| 2292 | } |
| 2293 | |
| 2294 | if (mdwc->suspend) { |
| 2295 | dev_dbg(mdwc->dev, "XCVR: SUSP set\n"); |
| 2296 | set_bit(B_SUSPEND, &mdwc->inputs); |
| 2297 | } else { |
| 2298 | dev_dbg(mdwc->dev, "XCVR: SUSP clear\n"); |
| 2299 | clear_bit(B_SUSPEND, &mdwc->inputs); |
| 2300 | } |
| 2301 | |
| 2302 | schedule_delayed_work(&mdwc->sm_work, 0); |
| 2303 | } |
| 2304 | |
| 2305 | static void dwc3_resume_work(struct work_struct *w) |
| 2306 | { |
| 2307 | struct dwc3_msm *mdwc = container_of(w, struct dwc3_msm, resume_work); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2308 | |
| 2309 | dev_dbg(mdwc->dev, "%s: dwc3 resume work\n", __func__); |
| 2310 | |
| 2311 | /* |
| 2312 | * exit LPM first to meet resume timeline from device side. |
| 2313 | * resume_pending flag would prevent calling |
| 2314 | * dwc3_msm_resume() in case we are here due to system |
| 2315 | * wide resume without usb cable connected. This flag is set |
| 2316 | * only in case of power event irq in lpm. |
| 2317 | */ |
| 2318 | if (mdwc->resume_pending) { |
| 2319 | dwc3_msm_resume(mdwc); |
| 2320 | mdwc->resume_pending = false; |
| 2321 | } |
| 2322 | |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 2323 | if (atomic_read(&mdwc->pm_suspended)) |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2324 | /* let pm resume kick in resume work later */ |
| 2325 | return; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2326 | dwc3_ext_event_notify(mdwc); |
| 2327 | } |
| 2328 | |
| 2329 | static void dwc3_pwr_event_handler(struct dwc3_msm *mdwc) |
| 2330 | { |
| 2331 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
| 2332 | u32 irq_stat, irq_clear = 0; |
| 2333 | |
| 2334 | irq_stat = dwc3_msm_read_reg(mdwc->base, PWR_EVNT_IRQ_STAT_REG); |
| 2335 | dev_dbg(mdwc->dev, "%s irq_stat=%X\n", __func__, irq_stat); |
| 2336 | |
| 2337 | /* Check for P3 events */ |
| 2338 | if ((irq_stat & PWR_EVNT_POWERDOWN_OUT_P3_MASK) && |
| 2339 | (irq_stat & PWR_EVNT_POWERDOWN_IN_P3_MASK)) { |
| 2340 | /* Can't tell if entered or exit P3, so check LINKSTATE */ |
| 2341 | u32 ls = dwc3_msm_read_reg_field(mdwc->base, |
| 2342 | DWC3_GDBGLTSSM, DWC3_GDBGLTSSM_LINKSTATE_MASK); |
| 2343 | dev_dbg(mdwc->dev, "%s link state = 0x%04x\n", __func__, ls); |
| 2344 | atomic_set(&mdwc->in_p3, ls == DWC3_LINK_STATE_U3); |
| 2345 | |
| 2346 | irq_stat &= ~(PWR_EVNT_POWERDOWN_OUT_P3_MASK | |
| 2347 | PWR_EVNT_POWERDOWN_IN_P3_MASK); |
| 2348 | irq_clear |= (PWR_EVNT_POWERDOWN_OUT_P3_MASK | |
| 2349 | PWR_EVNT_POWERDOWN_IN_P3_MASK); |
| 2350 | } else if (irq_stat & PWR_EVNT_POWERDOWN_OUT_P3_MASK) { |
| 2351 | atomic_set(&mdwc->in_p3, 0); |
| 2352 | irq_stat &= ~PWR_EVNT_POWERDOWN_OUT_P3_MASK; |
| 2353 | irq_clear |= PWR_EVNT_POWERDOWN_OUT_P3_MASK; |
| 2354 | } else if (irq_stat & PWR_EVNT_POWERDOWN_IN_P3_MASK) { |
| 2355 | atomic_set(&mdwc->in_p3, 1); |
| 2356 | irq_stat &= ~PWR_EVNT_POWERDOWN_IN_P3_MASK; |
| 2357 | irq_clear |= PWR_EVNT_POWERDOWN_IN_P3_MASK; |
| 2358 | } |
| 2359 | |
| 2360 | /* Clear L2 exit */ |
| 2361 | if (irq_stat & PWR_EVNT_LPM_OUT_L2_MASK) { |
| 2362 | irq_stat &= ~PWR_EVNT_LPM_OUT_L2_MASK; |
| 2363 | irq_stat |= PWR_EVNT_LPM_OUT_L2_MASK; |
| 2364 | } |
| 2365 | |
| 2366 | /* Handle exit from L1 events */ |
| 2367 | if (irq_stat & PWR_EVNT_LPM_OUT_L1_MASK) { |
| 2368 | dev_dbg(mdwc->dev, "%s: handling PWR_EVNT_LPM_OUT_L1_MASK\n", |
| 2369 | __func__); |
| 2370 | if (usb_gadget_wakeup(&dwc->gadget)) |
| 2371 | dev_err(mdwc->dev, "%s failed to take dwc out of L1\n", |
| 2372 | __func__); |
| 2373 | irq_stat &= ~PWR_EVNT_LPM_OUT_L1_MASK; |
| 2374 | irq_clear |= PWR_EVNT_LPM_OUT_L1_MASK; |
| 2375 | } |
| 2376 | |
| 2377 | /* Unhandled events */ |
| 2378 | if (irq_stat) |
| 2379 | dev_dbg(mdwc->dev, "%s: unexpected PWR_EVNT, irq_stat=%X\n", |
| 2380 | __func__, irq_stat); |
| 2381 | |
| 2382 | dwc3_msm_write_reg(mdwc->base, PWR_EVNT_IRQ_STAT_REG, irq_clear); |
| 2383 | } |
| 2384 | |
| 2385 | static irqreturn_t msm_dwc3_pwr_irq_thread(int irq, void *_mdwc) |
| 2386 | { |
| 2387 | struct dwc3_msm *mdwc = _mdwc; |
| 2388 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
| 2389 | |
| 2390 | dev_dbg(mdwc->dev, "%s\n", __func__); |
| 2391 | |
| 2392 | if (atomic_read(&dwc->in_lpm)) |
| 2393 | dwc3_resume_work(&mdwc->resume_work); |
| 2394 | else |
| 2395 | dwc3_pwr_event_handler(mdwc); |
| 2396 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2397 | return IRQ_HANDLED; |
| 2398 | } |
| 2399 | |
| 2400 | static irqreturn_t msm_dwc3_pwr_irq(int irq, void *data) |
| 2401 | { |
| 2402 | struct dwc3_msm *mdwc = data; |
| 2403 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
| 2404 | |
| 2405 | dwc->t_pwr_evt_irq = ktime_get(); |
| 2406 | dev_dbg(mdwc->dev, "%s received\n", __func__); |
| 2407 | /* |
| 2408 | * When in Low Power Mode, can't read PWR_EVNT_IRQ_STAT_REG to acertain |
| 2409 | * which interrupts have been triggered, as the clocks are disabled. |
| 2410 | * Resume controller by waking up pwr event irq thread.After re-enabling |
| 2411 | * clocks, dwc3_msm_resume will call dwc3_pwr_event_handler to handle |
| 2412 | * all other power events. |
| 2413 | */ |
| 2414 | if (atomic_read(&dwc->in_lpm)) { |
| 2415 | /* set this to call dwc3_msm_resume() */ |
| 2416 | mdwc->resume_pending = true; |
| 2417 | return IRQ_WAKE_THREAD; |
| 2418 | } |
| 2419 | |
| 2420 | dwc3_pwr_event_handler(mdwc); |
| 2421 | return IRQ_HANDLED; |
| 2422 | } |
| 2423 | |
| 2424 | static int dwc3_cpu_notifier_cb(struct notifier_block *nfb, |
| 2425 | unsigned long action, void *hcpu) |
| 2426 | { |
| 2427 | uint32_t cpu = (uintptr_t)hcpu; |
| 2428 | struct dwc3_msm *mdwc = |
| 2429 | container_of(nfb, struct dwc3_msm, dwc3_cpu_notifier); |
| 2430 | |
| 2431 | if (cpu == cpu_to_affin && action == CPU_ONLINE) { |
| 2432 | pr_debug("%s: cpu online:%u irq:%d\n", __func__, |
| 2433 | cpu_to_affin, mdwc->irq_to_affin); |
| 2434 | irq_set_affinity(mdwc->irq_to_affin, get_cpu_mask(cpu)); |
| 2435 | } |
| 2436 | |
| 2437 | return NOTIFY_OK; |
| 2438 | } |
| 2439 | |
| 2440 | static void dwc3_otg_sm_work(struct work_struct *w); |
| 2441 | |
| 2442 | static int dwc3_msm_get_clk_gdsc(struct dwc3_msm *mdwc) |
| 2443 | { |
| 2444 | int ret; |
| 2445 | |
| 2446 | mdwc->dwc3_gdsc = devm_regulator_get(mdwc->dev, "USB3_GDSC"); |
| 2447 | if (IS_ERR(mdwc->dwc3_gdsc)) |
| 2448 | mdwc->dwc3_gdsc = NULL; |
| 2449 | |
| 2450 | mdwc->xo_clk = devm_clk_get(mdwc->dev, "xo"); |
| 2451 | if (IS_ERR(mdwc->xo_clk)) { |
| 2452 | dev_err(mdwc->dev, "%s unable to get TCXO buffer handle\n", |
| 2453 | __func__); |
| 2454 | ret = PTR_ERR(mdwc->xo_clk); |
| 2455 | return ret; |
| 2456 | } |
| 2457 | clk_set_rate(mdwc->xo_clk, 19200000); |
| 2458 | |
| 2459 | mdwc->iface_clk = devm_clk_get(mdwc->dev, "iface_clk"); |
| 2460 | if (IS_ERR(mdwc->iface_clk)) { |
| 2461 | dev_err(mdwc->dev, "failed to get iface_clk\n"); |
| 2462 | ret = PTR_ERR(mdwc->iface_clk); |
| 2463 | return ret; |
| 2464 | } |
| 2465 | |
| 2466 | /* |
| 2467 | * DWC3 Core requires its CORE CLK (aka master / bus clk) to |
| 2468 | * run at 125Mhz in SSUSB mode and >60MHZ for HSUSB mode. |
| 2469 | * On newer platform it can run at 150MHz as well. |
| 2470 | */ |
| 2471 | mdwc->core_clk = devm_clk_get(mdwc->dev, "core_clk"); |
| 2472 | if (IS_ERR(mdwc->core_clk)) { |
| 2473 | dev_err(mdwc->dev, "failed to get core_clk\n"); |
| 2474 | ret = PTR_ERR(mdwc->core_clk); |
| 2475 | return ret; |
| 2476 | } |
| 2477 | |
Amit Nischal | 4d27821 | 2016-06-06 17:54:34 +0530 | [diff] [blame] | 2478 | mdwc->core_reset = devm_reset_control_get(mdwc->dev, "core_reset"); |
| 2479 | if (IS_ERR(mdwc->core_reset)) { |
| 2480 | dev_err(mdwc->dev, "failed to get core_reset\n"); |
| 2481 | return PTR_ERR(mdwc->core_reset); |
| 2482 | } |
| 2483 | |
Vijayavardhan Vennapusa | 3e668f3 | 2016-01-08 15:58:35 +0530 | [diff] [blame] | 2484 | if (!of_property_read_u32(mdwc->dev->of_node, "qcom,core-clk-rate", |
| 2485 | (u32 *)&mdwc->core_clk_rate)) { |
| 2486 | mdwc->core_clk_rate = clk_round_rate(mdwc->core_clk, |
| 2487 | mdwc->core_clk_rate); |
| 2488 | } else { |
| 2489 | /* |
| 2490 | * Get Max supported clk frequency for USB Core CLK and request |
| 2491 | * to set the same. |
| 2492 | */ |
| 2493 | mdwc->core_clk_rate = clk_round_rate(mdwc->core_clk, LONG_MAX); |
| 2494 | } |
| 2495 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2496 | if (IS_ERR_VALUE(mdwc->core_clk_rate)) { |
| 2497 | dev_err(mdwc->dev, "fail to get core clk max freq.\n"); |
| 2498 | } else { |
Vijayavardhan Vennapusa | 3e668f3 | 2016-01-08 15:58:35 +0530 | [diff] [blame] | 2499 | dev_dbg(mdwc->dev, "USB core frequency = %ld\n", |
| 2500 | mdwc->core_clk_rate); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2501 | ret = clk_set_rate(mdwc->core_clk, mdwc->core_clk_rate); |
| 2502 | if (ret) |
| 2503 | dev_err(mdwc->dev, "fail to set core_clk freq:%d\n", |
| 2504 | ret); |
| 2505 | } |
| 2506 | |
Hemant Kumar | 8e4c2f2 | 2017-01-24 18:13:07 -0800 | [diff] [blame] | 2507 | if (of_property_read_u32(mdwc->dev->of_node, "qcom,core-clk-rate-hs", |
| 2508 | (u32 *)&mdwc->core_clk_rate_hs)) { |
| 2509 | dev_dbg(mdwc->dev, "USB core-clk-rate-hs is not present\n"); |
| 2510 | mdwc->core_clk_rate_hs = mdwc->core_clk_rate; |
| 2511 | } |
| 2512 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2513 | mdwc->sleep_clk = devm_clk_get(mdwc->dev, "sleep_clk"); |
| 2514 | if (IS_ERR(mdwc->sleep_clk)) { |
| 2515 | dev_err(mdwc->dev, "failed to get sleep_clk\n"); |
| 2516 | ret = PTR_ERR(mdwc->sleep_clk); |
| 2517 | return ret; |
| 2518 | } |
| 2519 | |
| 2520 | clk_set_rate(mdwc->sleep_clk, 32000); |
| 2521 | mdwc->utmi_clk_rate = 19200000; |
| 2522 | mdwc->utmi_clk = devm_clk_get(mdwc->dev, "utmi_clk"); |
| 2523 | if (IS_ERR(mdwc->utmi_clk)) { |
| 2524 | dev_err(mdwc->dev, "failed to get utmi_clk\n"); |
| 2525 | ret = PTR_ERR(mdwc->utmi_clk); |
| 2526 | return ret; |
| 2527 | } |
| 2528 | |
| 2529 | clk_set_rate(mdwc->utmi_clk, mdwc->utmi_clk_rate); |
| 2530 | mdwc->bus_aggr_clk = devm_clk_get(mdwc->dev, "bus_aggr_clk"); |
| 2531 | if (IS_ERR(mdwc->bus_aggr_clk)) |
| 2532 | mdwc->bus_aggr_clk = NULL; |
| 2533 | |
Vijayavardhan Vennapusa | 934d9cd | 2016-11-30 13:10:01 +0530 | [diff] [blame] | 2534 | mdwc->noc_aggr_clk = devm_clk_get(mdwc->dev, "noc_aggr_clk"); |
| 2535 | if (IS_ERR(mdwc->noc_aggr_clk)) |
| 2536 | mdwc->noc_aggr_clk = NULL; |
| 2537 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2538 | if (of_property_match_string(mdwc->dev->of_node, |
| 2539 | "clock-names", "cfg_ahb_clk") >= 0) { |
| 2540 | mdwc->cfg_ahb_clk = devm_clk_get(mdwc->dev, "cfg_ahb_clk"); |
| 2541 | if (IS_ERR(mdwc->cfg_ahb_clk)) { |
| 2542 | ret = PTR_ERR(mdwc->cfg_ahb_clk); |
| 2543 | mdwc->cfg_ahb_clk = NULL; |
| 2544 | if (ret != -EPROBE_DEFER) |
| 2545 | dev_err(mdwc->dev, |
| 2546 | "failed to get cfg_ahb_clk ret %d\n", |
| 2547 | ret); |
| 2548 | return ret; |
| 2549 | } |
| 2550 | } |
| 2551 | |
| 2552 | return 0; |
| 2553 | } |
| 2554 | |
| 2555 | static int dwc3_msm_id_notifier(struct notifier_block *nb, |
| 2556 | unsigned long event, void *ptr) |
| 2557 | { |
| 2558 | struct dwc3_msm *mdwc = container_of(nb, struct dwc3_msm, id_nb); |
Hemant Kumar | de1df69 | 2016-04-26 19:36:48 -0700 | [diff] [blame] | 2559 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2560 | struct extcon_dev *edev = ptr; |
| 2561 | enum dwc3_id_state id; |
| 2562 | int cc_state; |
Hemant Kumar | de1df69 | 2016-04-26 19:36:48 -0700 | [diff] [blame] | 2563 | int speed; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2564 | |
| 2565 | if (!edev) { |
| 2566 | dev_err(mdwc->dev, "%s: edev null\n", __func__); |
| 2567 | goto done; |
| 2568 | } |
| 2569 | |
| 2570 | id = event ? DWC3_ID_GROUND : DWC3_ID_FLOAT; |
| 2571 | |
| 2572 | dev_dbg(mdwc->dev, "host:%ld (id:%d) event received\n", event, id); |
| 2573 | |
| 2574 | cc_state = extcon_get_cable_state_(edev, EXTCON_USB_CC); |
| 2575 | if (cc_state < 0) |
| 2576 | mdwc->typec_orientation = ORIENTATION_NONE; |
| 2577 | else |
| 2578 | mdwc->typec_orientation = |
| 2579 | cc_state ? ORIENTATION_CC2 : ORIENTATION_CC1; |
| 2580 | |
Hemant Kumar | de1df69 | 2016-04-26 19:36:48 -0700 | [diff] [blame] | 2581 | dev_dbg(mdwc->dev, "cc_state:%d", mdwc->typec_orientation); |
| 2582 | |
| 2583 | speed = extcon_get_cable_state_(edev, EXTCON_USB_SPEED); |
| 2584 | dwc->maximum_speed = (speed == 0) ? USB_SPEED_HIGH : USB_SPEED_SUPER; |
Vamsi Krishna Samavedam | 86ed20b | 2017-01-31 13:55:38 -0800 | [diff] [blame^] | 2585 | if (dwc->maximum_speed > dwc->max_hw_supp_speed) |
| 2586 | dwc->maximum_speed = dwc->max_hw_supp_speed; |
Hemant Kumar | de1df69 | 2016-04-26 19:36:48 -0700 | [diff] [blame] | 2587 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2588 | if (mdwc->id_state != id) { |
| 2589 | mdwc->id_state = id; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2590 | queue_work(mdwc->dwc3_wq, &mdwc->resume_work); |
| 2591 | } |
| 2592 | |
| 2593 | done: |
| 2594 | return NOTIFY_DONE; |
| 2595 | } |
| 2596 | |
| 2597 | static int dwc3_msm_vbus_notifier(struct notifier_block *nb, |
| 2598 | unsigned long event, void *ptr) |
| 2599 | { |
| 2600 | struct dwc3_msm *mdwc = container_of(nb, struct dwc3_msm, vbus_nb); |
| 2601 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
| 2602 | struct extcon_dev *edev = ptr; |
| 2603 | int cc_state; |
Hemant Kumar | de1df69 | 2016-04-26 19:36:48 -0700 | [diff] [blame] | 2604 | int speed; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2605 | |
| 2606 | if (!edev) { |
| 2607 | dev_err(mdwc->dev, "%s: edev null\n", __func__); |
| 2608 | goto done; |
| 2609 | } |
| 2610 | |
| 2611 | dev_dbg(mdwc->dev, "vbus:%ld event received\n", event); |
| 2612 | |
| 2613 | if (mdwc->vbus_active == event) |
| 2614 | return NOTIFY_DONE; |
| 2615 | |
| 2616 | cc_state = extcon_get_cable_state_(edev, EXTCON_USB_CC); |
| 2617 | if (cc_state < 0) |
| 2618 | mdwc->typec_orientation = ORIENTATION_NONE; |
| 2619 | else |
| 2620 | mdwc->typec_orientation = |
| 2621 | cc_state ? ORIENTATION_CC2 : ORIENTATION_CC1; |
| 2622 | |
Hemant Kumar | de1df69 | 2016-04-26 19:36:48 -0700 | [diff] [blame] | 2623 | dev_dbg(mdwc->dev, "cc_state:%d", mdwc->typec_orientation); |
| 2624 | |
| 2625 | speed = extcon_get_cable_state_(edev, EXTCON_USB_SPEED); |
| 2626 | dwc->maximum_speed = (speed == 0) ? USB_SPEED_HIGH : USB_SPEED_SUPER; |
Vamsi Krishna Samavedam | 86ed20b | 2017-01-31 13:55:38 -0800 | [diff] [blame^] | 2627 | if (dwc->maximum_speed > dwc->max_hw_supp_speed) |
| 2628 | dwc->maximum_speed = dwc->max_hw_supp_speed; |
Hemant Kumar | de1df69 | 2016-04-26 19:36:48 -0700 | [diff] [blame] | 2629 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2630 | mdwc->vbus_active = event; |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 2631 | if (dwc->is_drd && !mdwc->in_restart) |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2632 | queue_work(mdwc->dwc3_wq, &mdwc->resume_work); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2633 | done: |
| 2634 | return NOTIFY_DONE; |
| 2635 | } |
| 2636 | |
| 2637 | static int dwc3_msm_extcon_register(struct dwc3_msm *mdwc) |
| 2638 | { |
| 2639 | struct device_node *node = mdwc->dev->of_node; |
| 2640 | struct extcon_dev *edev; |
| 2641 | int ret = 0; |
| 2642 | |
| 2643 | if (!of_property_read_bool(node, "extcon")) |
| 2644 | return 0; |
| 2645 | |
| 2646 | edev = extcon_get_edev_by_phandle(mdwc->dev, 0); |
| 2647 | if (IS_ERR(edev) && PTR_ERR(edev) != -ENODEV) |
| 2648 | return PTR_ERR(edev); |
| 2649 | |
| 2650 | if (!IS_ERR(edev)) { |
| 2651 | mdwc->extcon_vbus = edev; |
| 2652 | mdwc->vbus_nb.notifier_call = dwc3_msm_vbus_notifier; |
| 2653 | ret = extcon_register_notifier(edev, EXTCON_USB, |
| 2654 | &mdwc->vbus_nb); |
| 2655 | if (ret < 0) { |
| 2656 | dev_err(mdwc->dev, "failed to register notifier for USB\n"); |
| 2657 | return ret; |
| 2658 | } |
| 2659 | } |
| 2660 | |
| 2661 | /* if a second phandle was provided, use it to get a separate edev */ |
| 2662 | if (of_count_phandle_with_args(node, "extcon", NULL) > 1) { |
| 2663 | edev = extcon_get_edev_by_phandle(mdwc->dev, 1); |
| 2664 | if (IS_ERR(edev) && PTR_ERR(edev) != -ENODEV) { |
| 2665 | ret = PTR_ERR(edev); |
| 2666 | goto err; |
| 2667 | } |
| 2668 | } |
| 2669 | |
| 2670 | if (!IS_ERR(edev)) { |
| 2671 | mdwc->extcon_id = edev; |
| 2672 | mdwc->id_nb.notifier_call = dwc3_msm_id_notifier; |
| 2673 | ret = extcon_register_notifier(edev, EXTCON_USB_HOST, |
| 2674 | &mdwc->id_nb); |
| 2675 | if (ret < 0) { |
| 2676 | dev_err(mdwc->dev, "failed to register notifier for USB-HOST\n"); |
| 2677 | goto err; |
| 2678 | } |
| 2679 | } |
| 2680 | |
| 2681 | return 0; |
| 2682 | err: |
| 2683 | if (mdwc->extcon_vbus) |
| 2684 | extcon_unregister_notifier(mdwc->extcon_vbus, EXTCON_USB, |
| 2685 | &mdwc->vbus_nb); |
| 2686 | return ret; |
| 2687 | } |
| 2688 | |
| 2689 | static ssize_t mode_show(struct device *dev, struct device_attribute *attr, |
| 2690 | char *buf) |
| 2691 | { |
| 2692 | struct dwc3_msm *mdwc = dev_get_drvdata(dev); |
| 2693 | |
| 2694 | if (mdwc->vbus_active) |
| 2695 | return snprintf(buf, PAGE_SIZE, "peripheral\n"); |
| 2696 | if (mdwc->id_state == DWC3_ID_GROUND) |
| 2697 | return snprintf(buf, PAGE_SIZE, "host\n"); |
| 2698 | |
| 2699 | return snprintf(buf, PAGE_SIZE, "none\n"); |
| 2700 | } |
| 2701 | |
| 2702 | static ssize_t mode_store(struct device *dev, struct device_attribute *attr, |
| 2703 | const char *buf, size_t count) |
| 2704 | { |
| 2705 | struct dwc3_msm *mdwc = dev_get_drvdata(dev); |
| 2706 | |
| 2707 | if (sysfs_streq(buf, "peripheral")) { |
| 2708 | mdwc->vbus_active = true; |
| 2709 | mdwc->id_state = DWC3_ID_FLOAT; |
| 2710 | } else if (sysfs_streq(buf, "host")) { |
| 2711 | mdwc->vbus_active = false; |
| 2712 | mdwc->id_state = DWC3_ID_GROUND; |
| 2713 | } else { |
| 2714 | mdwc->vbus_active = false; |
| 2715 | mdwc->id_state = DWC3_ID_FLOAT; |
| 2716 | } |
| 2717 | |
| 2718 | dwc3_ext_event_notify(mdwc); |
| 2719 | |
| 2720 | return count; |
| 2721 | } |
| 2722 | |
| 2723 | static DEVICE_ATTR_RW(mode); |
| 2724 | |
| 2725 | static int dwc3_msm_probe(struct platform_device *pdev) |
| 2726 | { |
| 2727 | struct device_node *node = pdev->dev.of_node, *dwc3_node; |
| 2728 | struct device *dev = &pdev->dev; |
| 2729 | struct dwc3_msm *mdwc; |
| 2730 | struct dwc3 *dwc; |
| 2731 | struct resource *res; |
| 2732 | void __iomem *tcsr; |
| 2733 | bool host_mode; |
| 2734 | int ret = 0; |
| 2735 | int ext_hub_reset_gpio; |
| 2736 | u32 val; |
| 2737 | |
| 2738 | mdwc = devm_kzalloc(&pdev->dev, sizeof(*mdwc), GFP_KERNEL); |
| 2739 | if (!mdwc) |
| 2740 | return -ENOMEM; |
| 2741 | |
| 2742 | if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64))) { |
| 2743 | dev_err(&pdev->dev, "setting DMA mask to 64 failed.\n"); |
| 2744 | if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32))) { |
| 2745 | dev_err(&pdev->dev, "setting DMA mask to 32 failed.\n"); |
| 2746 | return -EOPNOTSUPP; |
| 2747 | } |
| 2748 | } |
| 2749 | |
| 2750 | platform_set_drvdata(pdev, mdwc); |
| 2751 | mdwc->dev = &pdev->dev; |
| 2752 | |
| 2753 | INIT_LIST_HEAD(&mdwc->req_complete_list); |
| 2754 | INIT_WORK(&mdwc->resume_work, dwc3_resume_work); |
| 2755 | INIT_WORK(&mdwc->restart_usb_work, dwc3_restart_usb_work); |
| 2756 | INIT_WORK(&mdwc->bus_vote_w, dwc3_msm_bus_vote_w); |
Jack Pham | 4b8b4ae | 2016-08-09 11:36:34 -0700 | [diff] [blame] | 2757 | INIT_WORK(&mdwc->vbus_draw_work, dwc3_msm_vbus_draw_work); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2758 | INIT_DELAYED_WORK(&mdwc->sm_work, dwc3_otg_sm_work); |
| 2759 | |
| 2760 | mdwc->dwc3_wq = alloc_ordered_workqueue("dwc3_wq", 0); |
| 2761 | if (!mdwc->dwc3_wq) { |
| 2762 | pr_err("%s: Unable to create workqueue dwc3_wq\n", __func__); |
| 2763 | return -ENOMEM; |
| 2764 | } |
| 2765 | |
| 2766 | /* Get all clks and gdsc reference */ |
| 2767 | ret = dwc3_msm_get_clk_gdsc(mdwc); |
| 2768 | if (ret) { |
| 2769 | dev_err(&pdev->dev, "error getting clock or gdsc.\n"); |
| 2770 | return ret; |
| 2771 | } |
| 2772 | |
| 2773 | mdwc->id_state = DWC3_ID_FLOAT; |
| 2774 | set_bit(ID, &mdwc->inputs); |
| 2775 | |
| 2776 | mdwc->charging_disabled = of_property_read_bool(node, |
| 2777 | "qcom,charging-disabled"); |
| 2778 | |
| 2779 | ret = of_property_read_u32(node, "qcom,lpm-to-suspend-delay-ms", |
| 2780 | &mdwc->lpm_to_suspend_delay); |
| 2781 | if (ret) { |
| 2782 | dev_dbg(&pdev->dev, "setting lpm_to_suspend_delay to zero.\n"); |
| 2783 | mdwc->lpm_to_suspend_delay = 0; |
| 2784 | } |
| 2785 | |
| 2786 | /* |
| 2787 | * DWC3 has separate IRQ line for OTG events (ID/BSV) and for |
| 2788 | * DP and DM linestate transitions during low power mode. |
| 2789 | */ |
| 2790 | mdwc->hs_phy_irq = platform_get_irq_byname(pdev, "hs_phy_irq"); |
| 2791 | if (mdwc->hs_phy_irq < 0) { |
| 2792 | dev_err(&pdev->dev, "pget_irq for hs_phy_irq failed\n"); |
| 2793 | ret = -EINVAL; |
| 2794 | goto err; |
| 2795 | } else { |
| 2796 | irq_set_status_flags(mdwc->hs_phy_irq, IRQ_NOAUTOEN); |
| 2797 | ret = devm_request_threaded_irq(&pdev->dev, mdwc->hs_phy_irq, |
| 2798 | msm_dwc3_pwr_irq, |
| 2799 | msm_dwc3_pwr_irq_thread, |
| 2800 | IRQF_TRIGGER_RISING | IRQF_EARLY_RESUME |
| 2801 | | IRQF_ONESHOT, "hs_phy_irq", mdwc); |
| 2802 | if (ret) { |
| 2803 | dev_err(&pdev->dev, "irqreq hs_phy_irq failed: %d\n", |
| 2804 | ret); |
| 2805 | goto err; |
| 2806 | } |
| 2807 | } |
| 2808 | |
| 2809 | mdwc->ss_phy_irq = platform_get_irq_byname(pdev, "ss_phy_irq"); |
| 2810 | if (mdwc->ss_phy_irq < 0) { |
| 2811 | dev_dbg(&pdev->dev, "pget_irq for ss_phy_irq failed\n"); |
| 2812 | } else { |
| 2813 | irq_set_status_flags(mdwc->ss_phy_irq, IRQ_NOAUTOEN); |
| 2814 | ret = devm_request_threaded_irq(&pdev->dev, mdwc->ss_phy_irq, |
| 2815 | msm_dwc3_pwr_irq, |
| 2816 | msm_dwc3_pwr_irq_thread, |
| 2817 | IRQF_TRIGGER_RISING | IRQF_EARLY_RESUME |
| 2818 | | IRQF_ONESHOT, "ss_phy_irq", mdwc); |
| 2819 | if (ret) { |
| 2820 | dev_err(&pdev->dev, "irqreq ss_phy_irq failed: %d\n", |
| 2821 | ret); |
| 2822 | goto err; |
| 2823 | } |
| 2824 | } |
| 2825 | |
| 2826 | mdwc->pwr_event_irq = platform_get_irq_byname(pdev, "pwr_event_irq"); |
| 2827 | if (mdwc->pwr_event_irq < 0) { |
| 2828 | dev_err(&pdev->dev, "pget_irq for pwr_event_irq failed\n"); |
| 2829 | ret = -EINVAL; |
| 2830 | goto err; |
| 2831 | } else { |
| 2832 | /* will be enabled in dwc3_msm_resume() */ |
| 2833 | irq_set_status_flags(mdwc->pwr_event_irq, IRQ_NOAUTOEN); |
| 2834 | ret = devm_request_threaded_irq(&pdev->dev, mdwc->pwr_event_irq, |
| 2835 | msm_dwc3_pwr_irq, |
| 2836 | msm_dwc3_pwr_irq_thread, |
| 2837 | IRQF_TRIGGER_RISING | IRQF_EARLY_RESUME, |
| 2838 | "msm_dwc3", mdwc); |
| 2839 | if (ret) { |
| 2840 | dev_err(&pdev->dev, "irqreq pwr_event_irq failed: %d\n", |
| 2841 | ret); |
| 2842 | goto err; |
| 2843 | } |
| 2844 | } |
| 2845 | |
| 2846 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tcsr_base"); |
| 2847 | if (!res) { |
| 2848 | dev_dbg(&pdev->dev, "missing TCSR memory resource\n"); |
| 2849 | } else { |
| 2850 | tcsr = devm_ioremap_nocache(&pdev->dev, res->start, |
| 2851 | resource_size(res)); |
| 2852 | if (IS_ERR_OR_NULL(tcsr)) { |
| 2853 | dev_dbg(&pdev->dev, "tcsr ioremap failed\n"); |
| 2854 | } else { |
| 2855 | /* Enable USB3 on the primary USB port. */ |
| 2856 | writel_relaxed(0x1, tcsr); |
| 2857 | /* |
| 2858 | * Ensure that TCSR write is completed before |
| 2859 | * USB registers initialization. |
| 2860 | */ |
| 2861 | mb(); |
| 2862 | } |
| 2863 | } |
| 2864 | |
| 2865 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core_base"); |
| 2866 | if (!res) { |
| 2867 | dev_err(&pdev->dev, "missing memory base resource\n"); |
| 2868 | ret = -ENODEV; |
| 2869 | goto err; |
| 2870 | } |
| 2871 | |
| 2872 | mdwc->base = devm_ioremap_nocache(&pdev->dev, res->start, |
| 2873 | resource_size(res)); |
| 2874 | if (!mdwc->base) { |
| 2875 | dev_err(&pdev->dev, "ioremap failed\n"); |
| 2876 | ret = -ENODEV; |
| 2877 | goto err; |
| 2878 | } |
| 2879 | |
| 2880 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
| 2881 | "ahb2phy_base"); |
| 2882 | if (res) { |
| 2883 | mdwc->ahb2phy_base = devm_ioremap_nocache(&pdev->dev, |
| 2884 | res->start, resource_size(res)); |
| 2885 | if (IS_ERR_OR_NULL(mdwc->ahb2phy_base)) { |
| 2886 | dev_err(dev, "couldn't find ahb2phy_base addr.\n"); |
| 2887 | mdwc->ahb2phy_base = NULL; |
| 2888 | } else { |
| 2889 | /* |
| 2890 | * On some targets cfg_ahb_clk depends upon usb gdsc |
| 2891 | * regulator. If cfg_ahb_clk is enabled without |
| 2892 | * turning on usb gdsc regulator clk is stuck off. |
| 2893 | */ |
| 2894 | dwc3_msm_config_gdsc(mdwc, 1); |
| 2895 | clk_prepare_enable(mdwc->cfg_ahb_clk); |
| 2896 | /* Configure AHB2PHY for one wait state read/write*/ |
| 2897 | val = readl_relaxed(mdwc->ahb2phy_base + |
| 2898 | PERIPH_SS_AHB2PHY_TOP_CFG); |
| 2899 | if (val != ONE_READ_WRITE_WAIT) { |
| 2900 | writel_relaxed(ONE_READ_WRITE_WAIT, |
| 2901 | mdwc->ahb2phy_base + |
| 2902 | PERIPH_SS_AHB2PHY_TOP_CFG); |
| 2903 | /* complete above write before using USB PHY */ |
| 2904 | mb(); |
| 2905 | } |
| 2906 | clk_disable_unprepare(mdwc->cfg_ahb_clk); |
| 2907 | dwc3_msm_config_gdsc(mdwc, 0); |
| 2908 | } |
| 2909 | } |
| 2910 | |
| 2911 | if (of_get_property(pdev->dev.of_node, "qcom,usb-dbm", NULL)) { |
| 2912 | mdwc->dbm = usb_get_dbm_by_phandle(&pdev->dev, "qcom,usb-dbm"); |
| 2913 | if (IS_ERR(mdwc->dbm)) { |
| 2914 | dev_err(&pdev->dev, "unable to get dbm device\n"); |
| 2915 | ret = -EPROBE_DEFER; |
| 2916 | goto err; |
| 2917 | } |
| 2918 | /* |
| 2919 | * Add power event if the dbm indicates coming out of L1 |
| 2920 | * by interrupt |
| 2921 | */ |
| 2922 | if (dbm_l1_lpm_interrupt(mdwc->dbm)) { |
| 2923 | if (!mdwc->pwr_event_irq) { |
| 2924 | dev_err(&pdev->dev, |
| 2925 | "need pwr_event_irq exiting L1\n"); |
| 2926 | ret = -EINVAL; |
| 2927 | goto err; |
| 2928 | } |
| 2929 | } |
| 2930 | } |
| 2931 | |
| 2932 | ext_hub_reset_gpio = of_get_named_gpio(node, |
| 2933 | "qcom,ext-hub-reset-gpio", 0); |
| 2934 | |
| 2935 | if (gpio_is_valid(ext_hub_reset_gpio) |
| 2936 | && (!devm_gpio_request(&pdev->dev, ext_hub_reset_gpio, |
| 2937 | "qcom,ext-hub-reset-gpio"))) { |
| 2938 | /* reset external hub */ |
| 2939 | gpio_direction_output(ext_hub_reset_gpio, 1); |
| 2940 | /* |
| 2941 | * Hub reset should be asserted for minimum 5microsec |
| 2942 | * before deasserting. |
| 2943 | */ |
| 2944 | usleep_range(5, 1000); |
| 2945 | gpio_direction_output(ext_hub_reset_gpio, 0); |
| 2946 | } |
| 2947 | |
| 2948 | if (of_property_read_u32(node, "qcom,dwc-usb3-msm-tx-fifo-size", |
| 2949 | &mdwc->tx_fifo_size)) |
| 2950 | dev_err(&pdev->dev, |
| 2951 | "unable to read platform data tx fifo size\n"); |
| 2952 | |
| 2953 | mdwc->disable_host_mode_pm = of_property_read_bool(node, |
| 2954 | "qcom,disable-host-mode-pm"); |
| 2955 | |
| 2956 | dwc3_set_notifier(&dwc3_msm_notify_event); |
| 2957 | |
| 2958 | /* Assumes dwc3 is the first DT child of dwc3-msm */ |
| 2959 | dwc3_node = of_get_next_available_child(node, NULL); |
| 2960 | if (!dwc3_node) { |
| 2961 | dev_err(&pdev->dev, "failed to find dwc3 child\n"); |
| 2962 | ret = -ENODEV; |
| 2963 | goto err; |
| 2964 | } |
| 2965 | |
| 2966 | ret = of_platform_populate(node, NULL, NULL, &pdev->dev); |
| 2967 | if (ret) { |
| 2968 | dev_err(&pdev->dev, |
| 2969 | "failed to add create dwc3 core\n"); |
| 2970 | of_node_put(dwc3_node); |
| 2971 | goto err; |
| 2972 | } |
| 2973 | |
| 2974 | mdwc->dwc3 = of_find_device_by_node(dwc3_node); |
| 2975 | of_node_put(dwc3_node); |
| 2976 | if (!mdwc->dwc3) { |
| 2977 | dev_err(&pdev->dev, "failed to get dwc3 platform device\n"); |
| 2978 | goto put_dwc3; |
| 2979 | } |
| 2980 | |
| 2981 | mdwc->hs_phy = devm_usb_get_phy_by_phandle(&mdwc->dwc3->dev, |
| 2982 | "usb-phy", 0); |
| 2983 | if (IS_ERR(mdwc->hs_phy)) { |
| 2984 | dev_err(&pdev->dev, "unable to get hsphy device\n"); |
| 2985 | ret = PTR_ERR(mdwc->hs_phy); |
| 2986 | goto put_dwc3; |
| 2987 | } |
| 2988 | mdwc->ss_phy = devm_usb_get_phy_by_phandle(&mdwc->dwc3->dev, |
| 2989 | "usb-phy", 1); |
| 2990 | if (IS_ERR(mdwc->ss_phy)) { |
| 2991 | dev_err(&pdev->dev, "unable to get ssphy device\n"); |
| 2992 | ret = PTR_ERR(mdwc->ss_phy); |
| 2993 | goto put_dwc3; |
| 2994 | } |
| 2995 | |
| 2996 | mdwc->bus_scale_table = msm_bus_cl_get_pdata(pdev); |
| 2997 | if (mdwc->bus_scale_table) { |
| 2998 | mdwc->bus_perf_client = |
| 2999 | msm_bus_scale_register_client(mdwc->bus_scale_table); |
| 3000 | } |
| 3001 | |
| 3002 | dwc = platform_get_drvdata(mdwc->dwc3); |
| 3003 | if (!dwc) { |
| 3004 | dev_err(&pdev->dev, "Failed to get dwc3 device\n"); |
| 3005 | goto put_dwc3; |
| 3006 | } |
| 3007 | |
| 3008 | mdwc->irq_to_affin = platform_get_irq(mdwc->dwc3, 0); |
| 3009 | mdwc->dwc3_cpu_notifier.notifier_call = dwc3_cpu_notifier_cb; |
| 3010 | |
| 3011 | if (cpu_to_affin) |
| 3012 | register_cpu_notifier(&mdwc->dwc3_cpu_notifier); |
| 3013 | |
Mayank Rana | f4918d3 | 2016-12-15 13:35:55 -0800 | [diff] [blame] | 3014 | ret = of_property_read_u32(node, "qcom,num-gsi-evt-buffs", |
| 3015 | &mdwc->num_gsi_event_buffers); |
| 3016 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3017 | /* |
| 3018 | * Clocks and regulators will not be turned on until the first time |
| 3019 | * runtime PM resume is called. This is to allow for booting up with |
| 3020 | * charger already connected so as not to disturb PHY line states. |
| 3021 | */ |
| 3022 | mdwc->lpm_flags = MDWC3_POWER_COLLAPSE | MDWC3_SS_PHY_SUSPEND; |
| 3023 | atomic_set(&dwc->in_lpm, 1); |
| 3024 | pm_runtime_set_suspended(mdwc->dev); |
| 3025 | pm_runtime_set_autosuspend_delay(mdwc->dev, 1000); |
| 3026 | pm_runtime_use_autosuspend(mdwc->dev); |
| 3027 | pm_runtime_enable(mdwc->dev); |
| 3028 | device_init_wakeup(mdwc->dev, 1); |
| 3029 | |
| 3030 | if (of_property_read_bool(node, "qcom,disable-dev-mode-pm")) |
| 3031 | pm_runtime_get_noresume(mdwc->dev); |
| 3032 | |
| 3033 | ret = dwc3_msm_extcon_register(mdwc); |
| 3034 | if (ret) |
| 3035 | goto put_dwc3; |
| 3036 | |
| 3037 | /* Update initial VBUS/ID state from extcon */ |
| 3038 | if (mdwc->extcon_vbus && extcon_get_cable_state_(mdwc->extcon_vbus, |
| 3039 | EXTCON_USB)) |
| 3040 | dwc3_msm_vbus_notifier(&mdwc->vbus_nb, true, mdwc->extcon_vbus); |
| 3041 | if (mdwc->extcon_id && extcon_get_cable_state_(mdwc->extcon_id, |
| 3042 | EXTCON_USB_HOST)) |
| 3043 | dwc3_msm_id_notifier(&mdwc->id_nb, true, mdwc->extcon_id); |
| 3044 | |
| 3045 | device_create_file(&pdev->dev, &dev_attr_mode); |
| 3046 | |
| 3047 | schedule_delayed_work(&mdwc->sm_work, 0); |
| 3048 | |
| 3049 | host_mode = usb_get_dr_mode(&mdwc->dwc3->dev) == USB_DR_MODE_HOST; |
| 3050 | if (!dwc->is_drd && host_mode) { |
| 3051 | dev_dbg(&pdev->dev, "DWC3 in host only mode\n"); |
| 3052 | mdwc->id_state = DWC3_ID_GROUND; |
| 3053 | dwc3_ext_event_notify(mdwc); |
| 3054 | } |
| 3055 | |
| 3056 | return 0; |
| 3057 | |
| 3058 | put_dwc3: |
| 3059 | platform_device_put(mdwc->dwc3); |
| 3060 | if (mdwc->bus_perf_client) |
| 3061 | msm_bus_scale_unregister_client(mdwc->bus_perf_client); |
| 3062 | err: |
| 3063 | return ret; |
| 3064 | } |
| 3065 | |
| 3066 | static int dwc3_msm_remove_children(struct device *dev, void *data) |
| 3067 | { |
| 3068 | device_unregister(dev); |
| 3069 | return 0; |
| 3070 | } |
| 3071 | |
| 3072 | static int dwc3_msm_remove(struct platform_device *pdev) |
| 3073 | { |
| 3074 | struct dwc3_msm *mdwc = platform_get_drvdata(pdev); |
| 3075 | int ret_pm; |
| 3076 | |
| 3077 | device_remove_file(&pdev->dev, &dev_attr_mode); |
| 3078 | |
| 3079 | if (cpu_to_affin) |
| 3080 | unregister_cpu_notifier(&mdwc->dwc3_cpu_notifier); |
| 3081 | |
| 3082 | /* |
| 3083 | * In case of system suspend, pm_runtime_get_sync fails. |
| 3084 | * Hence turn ON the clocks manually. |
| 3085 | */ |
| 3086 | ret_pm = pm_runtime_get_sync(mdwc->dev); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3087 | if (ret_pm < 0) { |
| 3088 | dev_err(mdwc->dev, |
| 3089 | "pm_runtime_get_sync failed with %d\n", ret_pm); |
Vijayavardhan Vennapusa | 934d9cd | 2016-11-30 13:10:01 +0530 | [diff] [blame] | 3090 | if (mdwc->noc_aggr_clk) |
| 3091 | clk_prepare_enable(mdwc->noc_aggr_clk); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3092 | clk_prepare_enable(mdwc->utmi_clk); |
| 3093 | clk_prepare_enable(mdwc->core_clk); |
| 3094 | clk_prepare_enable(mdwc->iface_clk); |
| 3095 | clk_prepare_enable(mdwc->sleep_clk); |
| 3096 | if (mdwc->bus_aggr_clk) |
| 3097 | clk_prepare_enable(mdwc->bus_aggr_clk); |
| 3098 | clk_prepare_enable(mdwc->xo_clk); |
| 3099 | } |
| 3100 | |
| 3101 | cancel_delayed_work_sync(&mdwc->sm_work); |
| 3102 | |
| 3103 | if (mdwc->hs_phy) |
| 3104 | mdwc->hs_phy->flags &= ~PHY_HOST_MODE; |
| 3105 | platform_device_put(mdwc->dwc3); |
| 3106 | device_for_each_child(&pdev->dev, NULL, dwc3_msm_remove_children); |
| 3107 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3108 | pm_runtime_disable(mdwc->dev); |
| 3109 | pm_runtime_barrier(mdwc->dev); |
| 3110 | pm_runtime_put_sync(mdwc->dev); |
| 3111 | pm_runtime_set_suspended(mdwc->dev); |
| 3112 | device_wakeup_disable(mdwc->dev); |
| 3113 | |
| 3114 | if (mdwc->bus_perf_client) |
| 3115 | msm_bus_scale_unregister_client(mdwc->bus_perf_client); |
| 3116 | |
| 3117 | if (!IS_ERR_OR_NULL(mdwc->vbus_reg)) |
| 3118 | regulator_disable(mdwc->vbus_reg); |
| 3119 | |
| 3120 | disable_irq(mdwc->hs_phy_irq); |
| 3121 | if (mdwc->ss_phy_irq) |
| 3122 | disable_irq(mdwc->ss_phy_irq); |
| 3123 | disable_irq(mdwc->pwr_event_irq); |
| 3124 | |
| 3125 | clk_disable_unprepare(mdwc->utmi_clk); |
| 3126 | clk_set_rate(mdwc->core_clk, 19200000); |
| 3127 | clk_disable_unprepare(mdwc->core_clk); |
| 3128 | clk_disable_unprepare(mdwc->iface_clk); |
| 3129 | clk_disable_unprepare(mdwc->sleep_clk); |
| 3130 | clk_disable_unprepare(mdwc->xo_clk); |
| 3131 | clk_put(mdwc->xo_clk); |
| 3132 | |
| 3133 | dwc3_msm_config_gdsc(mdwc, 0); |
| 3134 | |
| 3135 | return 0; |
| 3136 | } |
| 3137 | |
Jack Pham | 4d4e934 | 2016-12-07 19:25:02 -0800 | [diff] [blame] | 3138 | static int dwc3_msm_host_notifier(struct notifier_block *nb, |
| 3139 | unsigned long event, void *ptr) |
| 3140 | { |
| 3141 | struct dwc3_msm *mdwc = container_of(nb, struct dwc3_msm, host_nb); |
| 3142 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
| 3143 | struct usb_device *udev = ptr; |
| 3144 | union power_supply_propval pval; |
| 3145 | unsigned int max_power; |
| 3146 | |
| 3147 | if (event != USB_DEVICE_ADD && event != USB_DEVICE_REMOVE) |
| 3148 | return NOTIFY_DONE; |
| 3149 | |
| 3150 | if (!mdwc->usb_psy) { |
| 3151 | mdwc->usb_psy = power_supply_get_by_name("usb"); |
| 3152 | if (!mdwc->usb_psy) |
| 3153 | return NOTIFY_DONE; |
| 3154 | } |
| 3155 | |
| 3156 | /* |
| 3157 | * For direct-attach devices, new udev is direct child of root hub |
| 3158 | * i.e. dwc -> xhci -> root_hub -> udev |
| 3159 | * root_hub's udev->parent==NULL, so traverse struct device hierarchy |
| 3160 | */ |
| 3161 | if (udev->parent && !udev->parent->parent && |
| 3162 | udev->dev.parent->parent == &dwc->xhci->dev) { |
| 3163 | if (event == USB_DEVICE_ADD && udev->actconfig) { |
Hemant Kumar | 8e4c2f2 | 2017-01-24 18:13:07 -0800 | [diff] [blame] | 3164 | if (!dwc3_msm_is_ss_rhport_connected(mdwc)) { |
| 3165 | /* |
| 3166 | * Core clock rate can be reduced only if root |
| 3167 | * hub SS port is not enabled/connected. |
| 3168 | */ |
| 3169 | clk_set_rate(mdwc->core_clk, |
| 3170 | mdwc->core_clk_rate_hs); |
| 3171 | dev_dbg(mdwc->dev, |
| 3172 | "set hs core clk rate %ld\n", |
| 3173 | mdwc->core_clk_rate_hs); |
| 3174 | mdwc->max_rh_port_speed = USB_SPEED_HIGH; |
| 3175 | } else { |
| 3176 | mdwc->max_rh_port_speed = USB_SPEED_SUPER; |
| 3177 | } |
| 3178 | |
Jack Pham | 4d4e934 | 2016-12-07 19:25:02 -0800 | [diff] [blame] | 3179 | if (udev->speed >= USB_SPEED_SUPER) |
| 3180 | max_power = udev->actconfig->desc.bMaxPower * 8; |
| 3181 | else |
| 3182 | max_power = udev->actconfig->desc.bMaxPower * 2; |
| 3183 | dev_dbg(mdwc->dev, "%s configured bMaxPower:%d (mA)\n", |
| 3184 | dev_name(&udev->dev), max_power); |
| 3185 | |
| 3186 | /* inform PMIC of max power so it can optimize boost */ |
| 3187 | pval.intval = max_power * 1000; |
| 3188 | power_supply_set_property(mdwc->usb_psy, |
| 3189 | POWER_SUPPLY_PROP_BOOST_CURRENT, &pval); |
| 3190 | } else { |
| 3191 | pval.intval = 0; |
| 3192 | power_supply_set_property(mdwc->usb_psy, |
| 3193 | POWER_SUPPLY_PROP_BOOST_CURRENT, &pval); |
Hemant Kumar | 8e4c2f2 | 2017-01-24 18:13:07 -0800 | [diff] [blame] | 3194 | mdwc->max_rh_port_speed = USB_SPEED_UNKNOWN; |
Jack Pham | 4d4e934 | 2016-12-07 19:25:02 -0800 | [diff] [blame] | 3195 | } |
| 3196 | } |
| 3197 | |
| 3198 | return NOTIFY_DONE; |
| 3199 | } |
| 3200 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3201 | #define VBUS_REG_CHECK_DELAY (msecs_to_jiffies(1000)) |
| 3202 | |
| 3203 | /** |
| 3204 | * dwc3_otg_start_host - helper function for starting/stoping the host |
| 3205 | * controller driver. |
| 3206 | * |
| 3207 | * @mdwc: Pointer to the dwc3_msm structure. |
| 3208 | * @on: start / stop the host controller driver. |
| 3209 | * |
| 3210 | * Returns 0 on success otherwise negative errno. |
| 3211 | */ |
| 3212 | static int dwc3_otg_start_host(struct dwc3_msm *mdwc, int on) |
| 3213 | { |
| 3214 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
| 3215 | int ret = 0; |
| 3216 | |
| 3217 | if (!dwc->xhci) |
| 3218 | return -EINVAL; |
| 3219 | |
| 3220 | /* |
| 3221 | * The vbus_reg pointer could have multiple values |
| 3222 | * NULL: regulator_get() hasn't been called, or was previously deferred |
| 3223 | * IS_ERR: regulator could not be obtained, so skip using it |
| 3224 | * Valid pointer otherwise |
| 3225 | */ |
| 3226 | if (!mdwc->vbus_reg) { |
| 3227 | mdwc->vbus_reg = devm_regulator_get_optional(mdwc->dev, |
| 3228 | "vbus_dwc3"); |
| 3229 | if (IS_ERR(mdwc->vbus_reg) && |
| 3230 | PTR_ERR(mdwc->vbus_reg) == -EPROBE_DEFER) { |
| 3231 | /* regulators may not be ready, so retry again later */ |
| 3232 | mdwc->vbus_reg = NULL; |
| 3233 | return -EPROBE_DEFER; |
| 3234 | } |
| 3235 | } |
| 3236 | |
| 3237 | if (on) { |
| 3238 | dev_dbg(mdwc->dev, "%s: turn on host\n", __func__); |
| 3239 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3240 | mdwc->hs_phy->flags |= PHY_HOST_MODE; |
Hemant Kumar | de1df69 | 2016-04-26 19:36:48 -0700 | [diff] [blame] | 3241 | if (dwc->maximum_speed == USB_SPEED_SUPER) |
| 3242 | mdwc->ss_phy->flags |= PHY_HOST_MODE; |
| 3243 | |
| 3244 | pm_runtime_get_sync(mdwc->dev); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3245 | usb_phy_notify_connect(mdwc->hs_phy, USB_SPEED_HIGH); |
| 3246 | if (!IS_ERR(mdwc->vbus_reg)) |
| 3247 | ret = regulator_enable(mdwc->vbus_reg); |
| 3248 | if (ret) { |
| 3249 | dev_err(mdwc->dev, "unable to enable vbus_reg\n"); |
| 3250 | mdwc->hs_phy->flags &= ~PHY_HOST_MODE; |
| 3251 | mdwc->ss_phy->flags &= ~PHY_HOST_MODE; |
| 3252 | pm_runtime_put_sync(mdwc->dev); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3253 | return ret; |
| 3254 | } |
| 3255 | |
| 3256 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST); |
| 3257 | |
Jack Pham | 4d4e934 | 2016-12-07 19:25:02 -0800 | [diff] [blame] | 3258 | mdwc->host_nb.notifier_call = dwc3_msm_host_notifier; |
| 3259 | usb_register_notify(&mdwc->host_nb); |
| 3260 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3261 | /* |
| 3262 | * FIXME If micro A cable is disconnected during system suspend, |
| 3263 | * xhci platform device will be removed before runtime pm is |
| 3264 | * enabled for xhci device. Due to this, disable_depth becomes |
| 3265 | * greater than one and runtimepm is not enabled for next microA |
| 3266 | * connect. Fix this by calling pm_runtime_init for xhci device. |
| 3267 | */ |
| 3268 | pm_runtime_init(&dwc->xhci->dev); |
| 3269 | ret = platform_device_add(dwc->xhci); |
| 3270 | if (ret) { |
| 3271 | dev_err(mdwc->dev, |
| 3272 | "%s: failed to add XHCI pdev ret=%d\n", |
| 3273 | __func__, ret); |
| 3274 | if (!IS_ERR(mdwc->vbus_reg)) |
| 3275 | regulator_disable(mdwc->vbus_reg); |
| 3276 | mdwc->hs_phy->flags &= ~PHY_HOST_MODE; |
| 3277 | mdwc->ss_phy->flags &= ~PHY_HOST_MODE; |
| 3278 | pm_runtime_put_sync(mdwc->dev); |
Jack Pham | 4d4e934 | 2016-12-07 19:25:02 -0800 | [diff] [blame] | 3279 | usb_unregister_notify(&mdwc->host_nb); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3280 | return ret; |
| 3281 | } |
| 3282 | |
| 3283 | /* |
| 3284 | * In some cases it is observed that USB PHY is not going into |
| 3285 | * suspend with host mode suspend functionality. Hence disable |
| 3286 | * XHCI's runtime PM here if disable_host_mode_pm is set. |
| 3287 | */ |
| 3288 | if (mdwc->disable_host_mode_pm) |
| 3289 | pm_runtime_disable(&dwc->xhci->dev); |
| 3290 | |
| 3291 | mdwc->in_host_mode = true; |
| 3292 | dwc3_usb3_phy_suspend(dwc, true); |
| 3293 | |
| 3294 | /* xHCI should have incremented child count as necessary */ |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3295 | pm_runtime_mark_last_busy(mdwc->dev); |
| 3296 | pm_runtime_put_sync_autosuspend(mdwc->dev); |
| 3297 | } else { |
| 3298 | dev_dbg(mdwc->dev, "%s: turn off host\n", __func__); |
| 3299 | |
| 3300 | if (!IS_ERR(mdwc->vbus_reg)) |
| 3301 | ret = regulator_disable(mdwc->vbus_reg); |
| 3302 | if (ret) { |
| 3303 | dev_err(mdwc->dev, "unable to disable vbus_reg\n"); |
| 3304 | return ret; |
| 3305 | } |
| 3306 | |
| 3307 | pm_runtime_get_sync(mdwc->dev); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3308 | usb_phy_notify_disconnect(mdwc->hs_phy, USB_SPEED_HIGH); |
| 3309 | mdwc->hs_phy->flags &= ~PHY_HOST_MODE; |
| 3310 | mdwc->ss_phy->flags &= ~PHY_HOST_MODE; |
| 3311 | platform_device_del(dwc->xhci); |
Jack Pham | 4d4e934 | 2016-12-07 19:25:02 -0800 | [diff] [blame] | 3312 | usb_unregister_notify(&mdwc->host_nb); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3313 | |
| 3314 | /* |
| 3315 | * Perform USB hardware RESET (both core reset and DBM reset) |
| 3316 | * when moving from host to peripheral. This is required for |
| 3317 | * peripheral mode to work. |
| 3318 | */ |
| 3319 | dwc3_msm_block_reset(mdwc, true); |
| 3320 | |
| 3321 | dwc3_usb3_phy_suspend(dwc, false); |
| 3322 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); |
| 3323 | |
| 3324 | mdwc->in_host_mode = false; |
| 3325 | |
| 3326 | /* re-init core and OTG registers as block reset clears these */ |
| 3327 | dwc3_post_host_reset_core_init(dwc); |
| 3328 | pm_runtime_mark_last_busy(mdwc->dev); |
| 3329 | pm_runtime_put_sync_autosuspend(mdwc->dev); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3330 | } |
| 3331 | |
| 3332 | return 0; |
| 3333 | } |
| 3334 | |
| 3335 | static void dwc3_override_vbus_status(struct dwc3_msm *mdwc, bool vbus_present) |
| 3336 | { |
| 3337 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
| 3338 | |
| 3339 | /* Update OTG VBUS Valid from HSPHY to controller */ |
| 3340 | dwc3_msm_write_readback(mdwc->base, HS_PHY_CTRL_REG, |
| 3341 | vbus_present ? UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL : |
| 3342 | UTMI_OTG_VBUS_VALID, |
| 3343 | vbus_present ? UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL : 0); |
| 3344 | |
| 3345 | /* Update only if Super Speed is supported */ |
| 3346 | if (dwc->maximum_speed == USB_SPEED_SUPER) { |
| 3347 | /* Update VBUS Valid from SSPHY to controller */ |
| 3348 | dwc3_msm_write_readback(mdwc->base, SS_PHY_CTRL_REG, |
| 3349 | LANE0_PWR_PRESENT, |
| 3350 | vbus_present ? LANE0_PWR_PRESENT : 0); |
| 3351 | } |
| 3352 | } |
| 3353 | |
| 3354 | /** |
| 3355 | * dwc3_otg_start_peripheral - bind/unbind the peripheral controller. |
| 3356 | * |
| 3357 | * @mdwc: Pointer to the dwc3_msm structure. |
| 3358 | * @on: Turn ON/OFF the gadget. |
| 3359 | * |
| 3360 | * Returns 0 on success otherwise negative errno. |
| 3361 | */ |
| 3362 | static int dwc3_otg_start_peripheral(struct dwc3_msm *mdwc, int on) |
| 3363 | { |
| 3364 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
| 3365 | |
| 3366 | pm_runtime_get_sync(mdwc->dev); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3367 | |
| 3368 | if (on) { |
| 3369 | dev_dbg(mdwc->dev, "%s: turn on gadget %s\n", |
| 3370 | __func__, dwc->gadget.name); |
| 3371 | |
| 3372 | dwc3_override_vbus_status(mdwc, true); |
| 3373 | usb_phy_notify_connect(mdwc->hs_phy, USB_SPEED_HIGH); |
| 3374 | usb_phy_notify_connect(mdwc->ss_phy, USB_SPEED_SUPER); |
| 3375 | |
| 3376 | /* |
| 3377 | * Core reset is not required during start peripheral. Only |
| 3378 | * DBM reset is required, hence perform only DBM reset here. |
| 3379 | */ |
| 3380 | dwc3_msm_block_reset(mdwc, false); |
| 3381 | |
| 3382 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); |
| 3383 | usb_gadget_vbus_connect(&dwc->gadget); |
| 3384 | } else { |
| 3385 | dev_dbg(mdwc->dev, "%s: turn off gadget %s\n", |
| 3386 | __func__, dwc->gadget.name); |
| 3387 | usb_gadget_vbus_disconnect(&dwc->gadget); |
| 3388 | usb_phy_notify_disconnect(mdwc->hs_phy, USB_SPEED_HIGH); |
| 3389 | usb_phy_notify_disconnect(mdwc->ss_phy, USB_SPEED_SUPER); |
| 3390 | dwc3_override_vbus_status(mdwc, false); |
| 3391 | dwc3_usb3_phy_suspend(dwc, false); |
| 3392 | } |
| 3393 | |
| 3394 | pm_runtime_put_sync(mdwc->dev); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3395 | |
| 3396 | return 0; |
| 3397 | } |
| 3398 | |
| 3399 | static int dwc3_msm_gadget_vbus_draw(struct dwc3_msm *mdwc, unsigned int mA) |
| 3400 | { |
Jack Pham | 8caff35 | 2016-08-19 16:33:55 -0700 | [diff] [blame] | 3401 | union power_supply_propval pval = {0}; |
Jack Pham | d72bafe | 2016-08-09 11:07:22 -0700 | [diff] [blame] | 3402 | int ret; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3403 | |
| 3404 | if (mdwc->charging_disabled) |
| 3405 | return 0; |
| 3406 | |
| 3407 | if (mdwc->max_power == mA) |
| 3408 | return 0; |
| 3409 | |
| 3410 | if (!mdwc->usb_psy) { |
| 3411 | mdwc->usb_psy = power_supply_get_by_name("usb"); |
| 3412 | if (!mdwc->usb_psy) { |
| 3413 | dev_warn(mdwc->dev, "Could not get usb power_supply\n"); |
| 3414 | return -ENODEV; |
| 3415 | } |
| 3416 | } |
| 3417 | |
Jack Pham | 8caff35 | 2016-08-19 16:33:55 -0700 | [diff] [blame] | 3418 | power_supply_get_property(mdwc->usb_psy, POWER_SUPPLY_PROP_TYPE, &pval); |
| 3419 | if (pval.intval != POWER_SUPPLY_TYPE_USB) |
| 3420 | return 0; |
| 3421 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3422 | dev_info(mdwc->dev, "Avail curr from USB = %u\n", mA); |
| 3423 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3424 | /* Set max current limit in uA */ |
Jack Pham | 8caff35 | 2016-08-19 16:33:55 -0700 | [diff] [blame] | 3425 | pval.intval = 1000 * mA; |
Jack Pham | d72bafe | 2016-08-09 11:07:22 -0700 | [diff] [blame] | 3426 | ret = power_supply_set_property(mdwc->usb_psy, |
| 3427 | POWER_SUPPLY_PROP_CURRENT_MAX, &pval); |
| 3428 | if (ret) { |
| 3429 | dev_dbg(mdwc->dev, "power supply error when setting property\n"); |
| 3430 | return ret; |
| 3431 | } |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3432 | |
| 3433 | mdwc->max_power = mA; |
| 3434 | return 0; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3435 | } |
| 3436 | |
| 3437 | |
| 3438 | /** |
| 3439 | * dwc3_otg_sm_work - workqueue function. |
| 3440 | * |
| 3441 | * @w: Pointer to the dwc3 otg workqueue |
| 3442 | * |
| 3443 | * NOTE: After any change in otg_state, we must reschdule the state machine. |
| 3444 | */ |
| 3445 | static void dwc3_otg_sm_work(struct work_struct *w) |
| 3446 | { |
| 3447 | struct dwc3_msm *mdwc = container_of(w, struct dwc3_msm, sm_work.work); |
| 3448 | struct dwc3 *dwc = NULL; |
| 3449 | bool work = 0; |
| 3450 | int ret = 0; |
| 3451 | unsigned long delay = 0; |
| 3452 | const char *state; |
| 3453 | |
| 3454 | if (mdwc->dwc3) |
| 3455 | dwc = platform_get_drvdata(mdwc->dwc3); |
| 3456 | |
| 3457 | if (!dwc) { |
| 3458 | dev_err(mdwc->dev, "dwc is NULL.\n"); |
| 3459 | return; |
| 3460 | } |
| 3461 | |
| 3462 | state = usb_otg_state_string(mdwc->otg_state); |
| 3463 | dev_dbg(mdwc->dev, "%s state\n", state); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3464 | |
| 3465 | /* Check OTG state */ |
| 3466 | switch (mdwc->otg_state) { |
| 3467 | case OTG_STATE_UNDEFINED: |
| 3468 | /* Do nothing if no cable connected */ |
| 3469 | if (test_bit(ID, &mdwc->inputs) && |
| 3470 | !test_bit(B_SESS_VLD, &mdwc->inputs)) |
| 3471 | break; |
| 3472 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3473 | mdwc->otg_state = OTG_STATE_B_IDLE; |
| 3474 | /* fall-through */ |
| 3475 | case OTG_STATE_B_IDLE: |
| 3476 | if (!test_bit(ID, &mdwc->inputs)) { |
| 3477 | dev_dbg(mdwc->dev, "!id\n"); |
| 3478 | mdwc->otg_state = OTG_STATE_A_IDLE; |
| 3479 | work = 1; |
| 3480 | } else if (test_bit(B_SESS_VLD, &mdwc->inputs)) { |
| 3481 | dev_dbg(mdwc->dev, "b_sess_vld\n"); |
| 3482 | /* |
| 3483 | * Increment pm usage count upon cable connect. Count |
| 3484 | * is decremented in OTG_STATE_B_PERIPHERAL state on |
| 3485 | * cable disconnect or in bus suspend. |
| 3486 | */ |
| 3487 | pm_runtime_get_sync(mdwc->dev); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3488 | dwc3_otg_start_peripheral(mdwc, 1); |
| 3489 | mdwc->otg_state = OTG_STATE_B_PERIPHERAL; |
| 3490 | work = 1; |
| 3491 | } else { |
| 3492 | dwc3_msm_gadget_vbus_draw(mdwc, 0); |
| 3493 | dev_dbg(mdwc->dev, "Cable disconnected\n"); |
| 3494 | } |
| 3495 | break; |
| 3496 | |
| 3497 | case OTG_STATE_B_PERIPHERAL: |
| 3498 | if (!test_bit(B_SESS_VLD, &mdwc->inputs) || |
| 3499 | !test_bit(ID, &mdwc->inputs)) { |
| 3500 | dev_dbg(mdwc->dev, "!id || !bsv\n"); |
| 3501 | mdwc->otg_state = OTG_STATE_B_IDLE; |
| 3502 | dwc3_otg_start_peripheral(mdwc, 0); |
| 3503 | /* |
| 3504 | * Decrement pm usage count upon cable disconnect |
| 3505 | * which was incremented upon cable connect in |
| 3506 | * OTG_STATE_B_IDLE state |
| 3507 | */ |
| 3508 | pm_runtime_put_sync(mdwc->dev); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3509 | work = 1; |
| 3510 | } else if (test_bit(B_SUSPEND, &mdwc->inputs) && |
| 3511 | test_bit(B_SESS_VLD, &mdwc->inputs)) { |
| 3512 | dev_dbg(mdwc->dev, "BPER bsv && susp\n"); |
| 3513 | mdwc->otg_state = OTG_STATE_B_SUSPEND; |
| 3514 | /* |
| 3515 | * Decrement pm usage count upon bus suspend. |
| 3516 | * Count was incremented either upon cable |
| 3517 | * connect in OTG_STATE_B_IDLE or host |
| 3518 | * initiated resume after bus suspend in |
| 3519 | * OTG_STATE_B_SUSPEND state |
| 3520 | */ |
| 3521 | pm_runtime_mark_last_busy(mdwc->dev); |
| 3522 | pm_runtime_put_autosuspend(mdwc->dev); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3523 | } |
| 3524 | break; |
| 3525 | |
| 3526 | case OTG_STATE_B_SUSPEND: |
| 3527 | if (!test_bit(B_SESS_VLD, &mdwc->inputs)) { |
| 3528 | dev_dbg(mdwc->dev, "BSUSP: !bsv\n"); |
| 3529 | mdwc->otg_state = OTG_STATE_B_IDLE; |
| 3530 | dwc3_otg_start_peripheral(mdwc, 0); |
| 3531 | } else if (!test_bit(B_SUSPEND, &mdwc->inputs)) { |
| 3532 | dev_dbg(mdwc->dev, "BSUSP !susp\n"); |
| 3533 | mdwc->otg_state = OTG_STATE_B_PERIPHERAL; |
| 3534 | /* |
| 3535 | * Increment pm usage count upon host |
| 3536 | * initiated resume. Count was decremented |
| 3537 | * upon bus suspend in |
| 3538 | * OTG_STATE_B_PERIPHERAL state. |
| 3539 | */ |
| 3540 | pm_runtime_get_sync(mdwc->dev); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3541 | } |
| 3542 | break; |
| 3543 | |
| 3544 | case OTG_STATE_A_IDLE: |
| 3545 | /* Switch to A-Device*/ |
| 3546 | if (test_bit(ID, &mdwc->inputs)) { |
| 3547 | dev_dbg(mdwc->dev, "id\n"); |
| 3548 | mdwc->otg_state = OTG_STATE_B_IDLE; |
| 3549 | mdwc->vbus_retry_count = 0; |
| 3550 | work = 1; |
| 3551 | } else { |
| 3552 | mdwc->otg_state = OTG_STATE_A_HOST; |
| 3553 | ret = dwc3_otg_start_host(mdwc, 1); |
| 3554 | if ((ret == -EPROBE_DEFER) && |
| 3555 | mdwc->vbus_retry_count < 3) { |
| 3556 | /* |
| 3557 | * Get regulator failed as regulator driver is |
| 3558 | * not up yet. Will try to start host after 1sec |
| 3559 | */ |
| 3560 | mdwc->otg_state = OTG_STATE_A_IDLE; |
| 3561 | dev_dbg(mdwc->dev, "Unable to get vbus regulator. Retrying...\n"); |
| 3562 | delay = VBUS_REG_CHECK_DELAY; |
| 3563 | work = 1; |
| 3564 | mdwc->vbus_retry_count++; |
| 3565 | } else if (ret) { |
| 3566 | dev_err(mdwc->dev, "unable to start host\n"); |
| 3567 | mdwc->otg_state = OTG_STATE_A_IDLE; |
| 3568 | goto ret; |
| 3569 | } |
| 3570 | } |
| 3571 | break; |
| 3572 | |
| 3573 | case OTG_STATE_A_HOST: |
| 3574 | if (test_bit(ID, &mdwc->inputs)) { |
| 3575 | dev_dbg(mdwc->dev, "id\n"); |
| 3576 | dwc3_otg_start_host(mdwc, 0); |
| 3577 | mdwc->otg_state = OTG_STATE_B_IDLE; |
| 3578 | mdwc->vbus_retry_count = 0; |
| 3579 | work = 1; |
| 3580 | } else { |
| 3581 | dev_dbg(mdwc->dev, "still in a_host state. Resuming root hub.\n"); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3582 | if (dwc) |
| 3583 | pm_runtime_resume(&dwc->xhci->dev); |
| 3584 | } |
| 3585 | break; |
| 3586 | |
| 3587 | default: |
| 3588 | dev_err(mdwc->dev, "%s: invalid otg-state\n", __func__); |
| 3589 | |
| 3590 | } |
| 3591 | |
| 3592 | if (work) |
| 3593 | schedule_delayed_work(&mdwc->sm_work, delay); |
| 3594 | |
| 3595 | ret: |
| 3596 | return; |
| 3597 | } |
| 3598 | |
| 3599 | #ifdef CONFIG_PM_SLEEP |
| 3600 | static int dwc3_msm_pm_suspend(struct device *dev) |
| 3601 | { |
| 3602 | int ret = 0; |
| 3603 | struct dwc3_msm *mdwc = dev_get_drvdata(dev); |
| 3604 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
| 3605 | |
| 3606 | dev_dbg(dev, "dwc3-msm PM suspend\n"); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3607 | |
| 3608 | flush_workqueue(mdwc->dwc3_wq); |
| 3609 | if (!atomic_read(&dwc->in_lpm)) { |
| 3610 | dev_err(mdwc->dev, "Abort PM suspend!! (USB is outside LPM)\n"); |
| 3611 | return -EBUSY; |
| 3612 | } |
| 3613 | |
| 3614 | ret = dwc3_msm_suspend(mdwc); |
| 3615 | if (!ret) |
| 3616 | atomic_set(&mdwc->pm_suspended, 1); |
| 3617 | |
| 3618 | return ret; |
| 3619 | } |
| 3620 | |
| 3621 | static int dwc3_msm_pm_resume(struct device *dev) |
| 3622 | { |
| 3623 | struct dwc3_msm *mdwc = dev_get_drvdata(dev); |
| 3624 | |
| 3625 | dev_dbg(dev, "dwc3-msm PM resume\n"); |
| 3626 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3627 | /* flush to avoid race in read/write of pm_suspended */ |
| 3628 | flush_workqueue(mdwc->dwc3_wq); |
| 3629 | atomic_set(&mdwc->pm_suspended, 0); |
| 3630 | |
| 3631 | /* kick in otg state machine */ |
| 3632 | queue_work(mdwc->dwc3_wq, &mdwc->resume_work); |
| 3633 | |
| 3634 | return 0; |
| 3635 | } |
| 3636 | #endif |
| 3637 | |
| 3638 | #ifdef CONFIG_PM |
| 3639 | static int dwc3_msm_runtime_idle(struct device *dev) |
| 3640 | { |
| 3641 | dev_dbg(dev, "DWC3-msm runtime idle\n"); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3642 | |
| 3643 | return 0; |
| 3644 | } |
| 3645 | |
| 3646 | static int dwc3_msm_runtime_suspend(struct device *dev) |
| 3647 | { |
| 3648 | struct dwc3_msm *mdwc = dev_get_drvdata(dev); |
| 3649 | |
| 3650 | dev_dbg(dev, "DWC3-msm runtime suspend\n"); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3651 | |
| 3652 | return dwc3_msm_suspend(mdwc); |
| 3653 | } |
| 3654 | |
| 3655 | static int dwc3_msm_runtime_resume(struct device *dev) |
| 3656 | { |
| 3657 | struct dwc3_msm *mdwc = dev_get_drvdata(dev); |
| 3658 | |
| 3659 | dev_dbg(dev, "DWC3-msm runtime resume\n"); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3660 | |
| 3661 | return dwc3_msm_resume(mdwc); |
| 3662 | } |
| 3663 | #endif |
| 3664 | |
| 3665 | static const struct dev_pm_ops dwc3_msm_dev_pm_ops = { |
| 3666 | SET_SYSTEM_SLEEP_PM_OPS(dwc3_msm_pm_suspend, dwc3_msm_pm_resume) |
| 3667 | SET_RUNTIME_PM_OPS(dwc3_msm_runtime_suspend, dwc3_msm_runtime_resume, |
| 3668 | dwc3_msm_runtime_idle) |
| 3669 | }; |
| 3670 | |
| 3671 | static const struct of_device_id of_dwc3_matach[] = { |
| 3672 | { |
| 3673 | .compatible = "qcom,dwc-usb3-msm", |
| 3674 | }, |
| 3675 | { }, |
| 3676 | }; |
| 3677 | MODULE_DEVICE_TABLE(of, of_dwc3_matach); |
| 3678 | |
| 3679 | static struct platform_driver dwc3_msm_driver = { |
| 3680 | .probe = dwc3_msm_probe, |
| 3681 | .remove = dwc3_msm_remove, |
| 3682 | .driver = { |
| 3683 | .name = "msm-dwc3", |
| 3684 | .pm = &dwc3_msm_dev_pm_ops, |
| 3685 | .of_match_table = of_dwc3_matach, |
| 3686 | }, |
| 3687 | }; |
| 3688 | |
| 3689 | MODULE_LICENSE("GPL v2"); |
| 3690 | MODULE_DESCRIPTION("DesignWare USB3 MSM Glue Layer"); |
| 3691 | |
| 3692 | static int dwc3_msm_init(void) |
| 3693 | { |
| 3694 | return platform_driver_register(&dwc3_msm_driver); |
| 3695 | } |
| 3696 | module_init(dwc3_msm_init); |
| 3697 | |
| 3698 | static void __exit dwc3_msm_exit(void) |
| 3699 | { |
| 3700 | platform_driver_unregister(&dwc3_msm_driver); |
| 3701 | } |
| 3702 | module_exit(dwc3_msm_exit); |