Sahitya Tummala | 87231ce | 2016-04-12 13:24:51 +0530 | [diff] [blame^] | 1 | /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | #ifndef LINUX_MMC_CQ_HCI_H |
| 13 | #define LINUX_MMC_CQ_HCI_H |
| 14 | #include <linux/mmc/core.h> |
| 15 | |
| 16 | /* registers */ |
| 17 | /* version */ |
| 18 | #define CQVER 0x00 |
| 19 | /* capabilities */ |
| 20 | #define CQCAP 0x04 |
| 21 | /* configuration */ |
| 22 | #define CQCFG 0x08 |
| 23 | #define CQ_DCMD 0x00001000 |
| 24 | #define CQ_TASK_DESC_SZ 0x00000100 |
| 25 | #define CQ_ENABLE 0x00000001 |
| 26 | |
| 27 | /* control */ |
| 28 | #define CQCTL 0x0C |
| 29 | #define CLEAR_ALL_TASKS 0x00000100 |
| 30 | #define HALT 0x00000001 |
| 31 | |
| 32 | /* interrupt status */ |
| 33 | #define CQIS 0x10 |
| 34 | #define CQIS_HAC (1 << 0) |
| 35 | #define CQIS_TCC (1 << 1) |
| 36 | #define CQIS_RED (1 << 2) |
| 37 | #define CQIS_TCL (1 << 3) |
| 38 | |
| 39 | /* interrupt status enable */ |
| 40 | #define CQISTE 0x14 |
| 41 | |
| 42 | /* interrupt signal enable */ |
| 43 | #define CQISGE 0x18 |
| 44 | |
| 45 | /* interrupt coalescing */ |
| 46 | #define CQIC 0x1C |
| 47 | #define CQIC_ENABLE (1 << 31) |
| 48 | #define CQIC_RESET (1 << 16) |
| 49 | #define CQIC_ICCTHWEN (1 << 15) |
| 50 | #define CQIC_ICCTH(x) ((x & 0x1F) << 8) |
| 51 | #define CQIC_ICTOVALWEN (1 << 7) |
| 52 | #define CQIC_ICTOVAL(x) (x & 0x7F) |
| 53 | |
| 54 | /* task list base address */ |
| 55 | #define CQTDLBA 0x20 |
| 56 | |
| 57 | /* task list base address upper */ |
| 58 | #define CQTDLBAU 0x24 |
| 59 | |
| 60 | /* door-bell */ |
| 61 | #define CQTDBR 0x28 |
| 62 | |
| 63 | /* task completion notification */ |
| 64 | #define CQTCN 0x2C |
| 65 | |
| 66 | /* device queue status */ |
| 67 | #define CQDQS 0x30 |
| 68 | |
| 69 | /* device pending tasks */ |
| 70 | #define CQDPT 0x34 |
| 71 | |
| 72 | /* task clear */ |
| 73 | #define CQTCLR 0x38 |
| 74 | |
| 75 | /* send status config 1 */ |
| 76 | #define CQSSC1 0x40 |
| 77 | /* |
| 78 | * Value n means CQE would send CMD13 during the transfer of data block |
| 79 | * BLOCK_CNT-n |
| 80 | */ |
Asutosh Das | 5b81f13 | 2015-10-06 09:53:33 +0530 | [diff] [blame] | 81 | #define SEND_QSR_INTERVAL 0x70001 |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 82 | |
| 83 | /* send status config 2 */ |
| 84 | #define CQSSC2 0x44 |
| 85 | |
| 86 | /* response for dcmd */ |
| 87 | #define CQCRDCT 0x48 |
| 88 | |
| 89 | /* response mode error mask */ |
| 90 | #define CQRMEM 0x50 |
Dov Levenglick | 2b67830 | 2015-07-01 14:24:20 +0300 | [diff] [blame] | 91 | #define CQ_EXCEPTION (1 << 6) |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 92 | |
| 93 | /* task error info */ |
| 94 | #define CQTERRI 0x54 |
| 95 | |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 96 | /* CQTERRI bit fields */ |
| 97 | #define CQ_RMECI 0x1F |
| 98 | #define CQ_RMETI (0x1F << 8) |
| 99 | #define CQ_RMEFV (1 << 15) |
| 100 | #define CQ_DTECI (0x3F << 16) |
| 101 | #define CQ_DTETI (0x1F << 24) |
| 102 | #define CQ_DTEFV (1 << 31) |
| 103 | |
| 104 | #define GET_CMD_ERR_TAG(__r__) ((__r__ & CQ_RMETI) >> 8) |
| 105 | #define GET_DAT_ERR_TAG(__r__) ((__r__ & CQ_DTETI) >> 24) |
| 106 | |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 107 | /* command response index */ |
| 108 | #define CQCRI 0x58 |
| 109 | |
| 110 | /* command response argument */ |
| 111 | #define CQCRA 0x5C |
| 112 | |
| 113 | #define CQ_INT_ALL 0xF |
| 114 | #define CQIC_DEFAULT_ICCTH 31 |
| 115 | #define CQIC_DEFAULT_ICTOVAL 1 |
| 116 | |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 117 | /* attribute fields */ |
| 118 | #define VALID(x) ((x & 1) << 0) |
| 119 | #define END(x) ((x & 1) << 1) |
| 120 | #define INT(x) ((x & 1) << 2) |
| 121 | #define ACT(x) ((x & 0x7) << 3) |
| 122 | |
| 123 | /* data command task descriptor fields */ |
| 124 | #define FORCED_PROG(x) ((x & 1) << 6) |
| 125 | #define CONTEXT(x) ((x & 0xF) << 7) |
| 126 | #define DATA_TAG(x) ((x & 1) << 11) |
| 127 | #define DATA_DIR(x) ((x & 1) << 12) |
| 128 | #define PRIORITY(x) ((x & 1) << 13) |
| 129 | #define QBAR(x) ((x & 1) << 14) |
| 130 | #define REL_WRITE(x) ((x & 1) << 15) |
| 131 | #define BLK_COUNT(x) ((x & 0xFFFF) << 16) |
| 132 | #define BLK_ADDR(x) ((x & 0xFFFFFFFF) << 32) |
| 133 | |
| 134 | /* direct command task descriptor fields */ |
| 135 | #define CMD_INDEX(x) ((x & 0x3F) << 16) |
| 136 | #define CMD_TIMING(x) ((x & 1) << 22) |
| 137 | #define RESP_TYPE(x) ((x & 0x3) << 23) |
| 138 | |
| 139 | /* transfer descriptor fields */ |
| 140 | #define DAT_LENGTH(x) ((x & 0xFFFF) << 16) |
| 141 | #define DAT_ADDR_LO(x) ((x & 0xFFFFFFFF) << 32) |
| 142 | #define DAT_ADDR_HI(x) ((x & 0xFFFFFFFF) << 0) |
| 143 | |
Asutosh Das | c0ed9c4 | 2015-05-29 15:39:37 +0530 | [diff] [blame] | 144 | #define CQ_VENDOR_CFG 0x100 |
| 145 | #define CMDQ_SEND_STATUS_TRIGGER (1 << 31) |
| 146 | |
Venkat Gopalakrishnan | e77c64d | 2015-09-28 18:53:18 -0700 | [diff] [blame] | 147 | struct task_history { |
| 148 | u64 task; |
| 149 | bool is_dcmd; |
| 150 | }; |
| 151 | |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 152 | struct cmdq_host { |
| 153 | const struct cmdq_host_ops *ops; |
| 154 | void __iomem *mmio; |
| 155 | struct mmc_host *mmc; |
| 156 | |
| 157 | /* 64 bit DMA */ |
| 158 | bool dma64; |
| 159 | int num_slots; |
| 160 | |
| 161 | u32 dcmd_slot; |
| 162 | u32 caps; |
| 163 | #define CMDQ_TASK_DESC_SZ_128 0x1 |
| 164 | |
| 165 | u32 quirks; |
| 166 | #define CMDQ_QUIRK_SHORT_TXFR_DESC_SZ 0x1 |
| 167 | #define CMDQ_QUIRK_NO_DCMD 0x2 |
| 168 | |
| 169 | bool enabled; |
| 170 | bool halted; |
| 171 | bool init_done; |
| 172 | |
| 173 | u8 *desc_base; |
| 174 | |
| 175 | /* total descriptor size */ |
| 176 | u8 slot_sz; |
| 177 | |
| 178 | /* 64/128 bit depends on CQCFG */ |
| 179 | u8 task_desc_len; |
| 180 | |
| 181 | /* 64 bit on 32-bit arch, 128 bit on 64-bit */ |
| 182 | u8 link_desc_len; |
| 183 | |
| 184 | u8 *trans_desc_base; |
| 185 | /* same length as transfer descriptor */ |
| 186 | u8 trans_desc_len; |
| 187 | |
| 188 | dma_addr_t desc_dma_base; |
| 189 | dma_addr_t trans_desc_dma_base; |
| 190 | |
Venkat Gopalakrishnan | e77c64d | 2015-09-28 18:53:18 -0700 | [diff] [blame] | 191 | struct task_history *thist; |
| 192 | u8 thist_idx; |
| 193 | |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 194 | struct completion halt_comp; |
| 195 | struct mmc_request **mrq_slot; |
| 196 | void *private; |
| 197 | }; |
| 198 | |
| 199 | struct cmdq_host_ops { |
Sahitya Tummala | 87231ce | 2016-04-12 13:24:51 +0530 | [diff] [blame^] | 200 | void (*set_transfer_params)(struct mmc_host *mmc); |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 201 | void (*set_data_timeout)(struct mmc_host *mmc, u32 val); |
| 202 | void (*clear_set_irqs)(struct mmc_host *mmc, bool clear); |
| 203 | void (*set_block_size)(struct mmc_host *mmc); |
| 204 | void (*dump_vendor_regs)(struct mmc_host *mmc); |
| 205 | void (*write_l)(struct cmdq_host *host, u32 val, int reg); |
| 206 | u32 (*read_l)(struct cmdq_host *host, int reg); |
| 207 | void (*clear_set_dumpregs)(struct mmc_host *mmc, bool set); |
Ritesh Harjani | 6b2ea57 | 2015-07-15 13:23:05 +0530 | [diff] [blame] | 208 | void (*enhanced_strobe_mask)(struct mmc_host *mmc, bool set); |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 209 | int (*reset)(struct mmc_host *mmc); |
Konstantin Dorfman | fa32107 | 2015-05-31 10:10:13 +0300 | [diff] [blame] | 210 | void (*post_cqe_halt)(struct mmc_host *mmc); |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 211 | }; |
| 212 | |
| 213 | static inline void cmdq_writel(struct cmdq_host *host, u32 val, int reg) |
| 214 | { |
Ritesh Harjani | ee93d26 | 2015-12-30 15:53:49 +0530 | [diff] [blame] | 215 | if (unlikely(host->ops && host->ops->write_l)) |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 216 | host->ops->write_l(host, val, reg); |
| 217 | else |
| 218 | writel_relaxed(val, host->mmio + reg); |
| 219 | } |
| 220 | |
| 221 | static inline u32 cmdq_readl(struct cmdq_host *host, int reg) |
| 222 | { |
Ritesh Harjani | ee93d26 | 2015-12-30 15:53:49 +0530 | [diff] [blame] | 223 | if (unlikely(host->ops && host->ops->read_l)) |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 224 | return host->ops->read_l(host, reg); |
| 225 | else |
| 226 | return readl_relaxed(host->mmio + reg); |
| 227 | } |
| 228 | |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 229 | extern irqreturn_t cmdq_irq(struct mmc_host *mmc, int err); |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 230 | extern int cmdq_init(struct cmdq_host *cq_host, struct mmc_host *mmc, |
| 231 | bool dma64); |
| 232 | extern struct cmdq_host *cmdq_pltfm_init(struct platform_device *pdev); |
| 233 | #endif |