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Russell King9e2697f2007-12-14 13:30:14 +00001/*
2 * linux/arch/arm/mach-pxa/cpu-pxa.c
3 *
4 * Copyright (C) 2002,2003 Intrinsyc Software
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 * History:
21 * 31-Jul-2002 : Initial version [FB]
22 * 29-Jan-2003 : added PXA255 support [FB]
23 * 20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.)
24 *
25 * Note:
26 * This driver may change the memory bus clock rate, but will not do any
27 * platform specific access timing changes... for example if you have flash
28 * memory connected to CS0, you will need to register a platform specific
29 * notifier which will adjust the memory access strobes to maintain a
30 * minimum strobe width.
31 *
32 */
33
34#include <linux/kernel.h>
35#include <linux/module.h>
36#include <linux/sched.h>
37#include <linux/init.h>
38#include <linux/cpufreq.h>
39
40#include <asm/hardware.h>
41#include <asm/arch/pxa-regs.h>
Russell King8785a8f2008-01-14 17:02:33 +000042#include <asm/arch/pxa2xx-regs.h>
Russell King9e2697f2007-12-14 13:30:14 +000043
44#ifdef DEBUG
45static unsigned int freq_debug;
46MODULE_PARM(freq_debug, "i");
47MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0");
48#else
49#define freq_debug 0
50#endif
51
52typedef struct {
53 unsigned int khz;
54 unsigned int membus;
55 unsigned int cccr;
56 unsigned int div2;
57} pxa_freqs_t;
58
59/* Define the refresh period in mSec for the SDRAM and the number of rows */
60#define SDRAM_TREF 64 /* standard 64ms SDRAM */
61#define SDRAM_ROWS 4096 /* 64MB=8192 32MB=4096 */
62#define MDREFR_DRI(x) (((x) * SDRAM_TREF) / (SDRAM_ROWS * 32))
63
64#define CCLKCFG_TURBO 0x1
65#define CCLKCFG_FCS 0x2
66#define PXA25x_MIN_FREQ 99500
67#define PXA25x_MAX_FREQ 398100
68#define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2)
69#define MDREFR_DRI_MASK 0xFFF
70
71
72/* Use the run mode frequencies for the CPUFREQ_POLICY_PERFORMANCE policy */
73static pxa_freqs_t pxa255_run_freqs[] =
74{
75 /* CPU MEMBUS CCCR DIV2*/
76 { 99500, 99500, 0x121, 1}, /* run= 99, turbo= 99, PXbus=50, SDRAM=50 */
77 {132700, 132700, 0x123, 1}, /* run=133, turbo=133, PXbus=66, SDRAM=66 */
78 {199100, 99500, 0x141, 0}, /* run=199, turbo=199, PXbus=99, SDRAM=99 */
79 {265400, 132700, 0x143, 1}, /* run=265, turbo=265, PXbus=133, SDRAM=66 */
80 {331800, 165900, 0x145, 1}, /* run=331, turbo=331, PXbus=166, SDRAM=83 */
81 {398100, 99500, 0x161, 0}, /* run=398, turbo=398, PXbus=196, SDRAM=99 */
82 {0,}
83};
84#define NUM_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs)
85
86static struct cpufreq_frequency_table pxa255_run_freq_table[NUM_RUN_FREQS+1];
87
88/* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */
89static pxa_freqs_t pxa255_turbo_freqs[] =
90{
91 /* CPU MEMBUS CCCR DIV2*/
92 { 99500, 99500, 0x121, 1}, /* run=99, turbo= 99, PXbus=50, SDRAM=50 */
93 {199100, 99500, 0x221, 0}, /* run=99, turbo=199, PXbus=50, SDRAM=99 */
94 {298500, 99500, 0x321, 0}, /* run=99, turbo=287, PXbus=50, SDRAM=99 */
95 {298600, 99500, 0x1c1, 0}, /* run=199, turbo=287, PXbus=99, SDRAM=99 */
96 {398100, 99500, 0x241, 0}, /* run=199, turbo=398, PXbus=99, SDRAM=99 */
97 {0,}
98};
99#define NUM_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs)
100
101static struct cpufreq_frequency_table pxa255_turbo_freq_table[NUM_TURBO_FREQS+1];
102
103extern unsigned get_clk_frequency_khz(int info);
104
105/* find a valid frequency point */
106static int pxa_verify_policy(struct cpufreq_policy *policy)
107{
108 struct cpufreq_frequency_table *pxa_freqs_table;
109 int ret;
110
111 if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
112 pxa_freqs_table = pxa255_run_freq_table;
113 } else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) {
114 pxa_freqs_table = pxa255_turbo_freq_table;
115 } else {
116 printk("CPU PXA: Unknown policy found. "
117 "Using CPUFREQ_POLICY_PERFORMANCE\n");
118 pxa_freqs_table = pxa255_run_freq_table;
119 }
120
121 ret = cpufreq_frequency_table_verify(policy, pxa_freqs_table);
122
123 if (freq_debug)
124 pr_debug("Verified CPU policy: %dKhz min to %dKhz max\n",
125 policy->min, policy->max);
126
127 return ret;
128}
129
130static int pxa_set_target(struct cpufreq_policy *policy,
131 unsigned int target_freq,
132 unsigned int relation)
133{
134 struct cpufreq_frequency_table *pxa_freqs_table;
135 pxa_freqs_t *pxa_freq_settings;
136 struct cpufreq_freqs freqs;
137 int idx;
138 unsigned long flags;
139 unsigned int unused, preset_mdrefr, postset_mdrefr;
140 void *ramstart = phys_to_virt(0xa0000000);
141
142 /* Get the current policy */
143 if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
144 pxa_freq_settings = pxa255_run_freqs;
145 pxa_freqs_table = pxa255_run_freq_table;
146 } else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) {
147 pxa_freq_settings = pxa255_turbo_freqs;
148 pxa_freqs_table = pxa255_turbo_freq_table;
149 } else {
150 printk("CPU PXA: Unknown policy found. "
151 "Using CPUFREQ_POLICY_PERFORMANCE\n");
152 pxa_freq_settings = pxa255_run_freqs;
153 pxa_freqs_table = pxa255_run_freq_table;
154 }
155
156 /* Lookup the next frequency */
157 if (cpufreq_frequency_table_target(policy, pxa_freqs_table,
158 target_freq, relation, &idx)) {
159 return -EINVAL;
160 }
161
162 freqs.old = policy->cur;
163 freqs.new = pxa_freq_settings[idx].khz;
164 freqs.cpu = policy->cpu;
165
166 if (freq_debug)
167 pr_debug(KERN_INFO "Changing CPU frequency to %d Mhz, (SDRAM %d Mhz)\n",
168 freqs.new / 1000, (pxa_freq_settings[idx].div2) ?
169 (pxa_freq_settings[idx].membus / 2000) :
170 (pxa_freq_settings[idx].membus / 1000));
171
172 /*
173 * Tell everyone what we're about to do...
174 * you should add a notify client with any platform specific
175 * Vcc changing capability
176 */
177 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
178
179 /* Calculate the next MDREFR. If we're slowing down the SDRAM clock
180 * we need to preset the smaller DRI before the change. If we're speeding
181 * up we need to set the larger DRI value after the change.
182 */
183 preset_mdrefr = postset_mdrefr = MDREFR;
184 if ((MDREFR & MDREFR_DRI_MASK) > MDREFR_DRI(pxa_freq_settings[idx].membus)) {
185 preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK) |
186 MDREFR_DRI(pxa_freq_settings[idx].membus);
187 }
188 postset_mdrefr = (postset_mdrefr & ~MDREFR_DRI_MASK) |
189 MDREFR_DRI(pxa_freq_settings[idx].membus);
190
191 /* If we're dividing the memory clock by two for the SDRAM clock, this
192 * must be set prior to the change. Clearing the divide must be done
193 * after the change.
194 */
195 if (pxa_freq_settings[idx].div2) {
196 preset_mdrefr |= MDREFR_DB2_MASK;
197 postset_mdrefr |= MDREFR_DB2_MASK;
198 } else {
199 postset_mdrefr &= ~MDREFR_DB2_MASK;
200 }
201
202 local_irq_save(flags);
203
204 /* Set new the CCCR */
205 CCCR = pxa_freq_settings[idx].cccr;
206
207 asm volatile(" \n\
208 ldr r4, [%1] /* load MDREFR */ \n\
209 b 2f \n\
210 .align 5 \n\
2111: \n\
212 str %4, [%1] /* preset the MDREFR */ \n\
213 mcr p14, 0, %2, c6, c0, 0 /* set CCLKCFG[FCS] */ \n\
214 str %5, [%1] /* postset the MDREFR */ \n\
215 \n\
216 b 3f \n\
2172: b 1b \n\
2183: nop \n\
219 "
220 : "=&r" (unused)
221 : "r" (&MDREFR), "r" (CCLKCFG_TURBO|CCLKCFG_FCS), "r" (ramstart),
222 "r" (preset_mdrefr), "r" (postset_mdrefr)
223 : "r4", "r5");
224 local_irq_restore(flags);
225
226 /*
227 * Tell everyone what we've just done...
228 * you should add a notify client with any platform specific
229 * SDRAM refresh timer adjustments
230 */
231 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
232
233 return 0;
234}
235
236static int pxa_cpufreq_init(struct cpufreq_policy *policy)
237{
238 int i;
239
240 /* set default policy and cpuinfo */
241 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
242 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
243 policy->cpuinfo.max_freq = PXA25x_MAX_FREQ;
244 policy->cpuinfo.min_freq = PXA25x_MIN_FREQ;
245 policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
246 policy->cur = get_clk_frequency_khz(0); /* current freq */
247 policy->min = policy->max = policy->cur;
248
249 /* Generate the run cpufreq_frequency_table struct */
250 for (i = 0; i < NUM_RUN_FREQS; i++) {
251 pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz;
252 pxa255_run_freq_table[i].index = i;
253 }
254
255 pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END;
256 /* Generate the turbo cpufreq_frequency_table struct */
257 for (i = 0; i < NUM_TURBO_FREQS; i++) {
258 pxa255_turbo_freq_table[i].frequency = pxa255_turbo_freqs[i].khz;
259 pxa255_turbo_freq_table[i].index = i;
260 }
261 pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END;
262
263 printk(KERN_INFO "PXA CPU frequency change support initialized\n");
264
265 return 0;
266}
267
268static struct cpufreq_driver pxa_cpufreq_driver = {
269 .verify = pxa_verify_policy,
270 .target = pxa_set_target,
271 .init = pxa_cpufreq_init,
272 .name = "PXA25x",
273};
274
275static int __init pxa_cpu_init(void)
276{
277 int ret = -ENODEV;
278 if (cpu_is_pxa25x())
279 ret = cpufreq_register_driver(&pxa_cpufreq_driver);
280 return ret;
281}
282
283static void __exit pxa_cpu_exit(void)
284{
285 if (cpu_is_pxa25x())
286 cpufreq_unregister_driver(&pxa_cpufreq_driver);
287}
288
289
290MODULE_AUTHOR ("Intrinsyc Software Inc.");
291MODULE_DESCRIPTION ("CPU frequency changing driver for the PXA architecture");
292MODULE_LICENSE("GPL");
293module_init(pxa_cpu_init);
294module_exit(pxa_cpu_exit);