Arnd Bergmann | 7f21779 | 2012-05-13 00:14:24 -0400 | [diff] [blame] | 1 | These properties are common to multiple MMC host controllers. Any host |
| 2 | that requires the respective functionality should implement them using |
| 3 | these definitions. |
| 4 | |
Chris Ball | ed3efc1 | 2012-06-11 22:06:43 -0400 | [diff] [blame] | 5 | Interpreted by the OF core: |
| 6 | - reg: Registers location and length. |
| 7 | - interrupts: Interrupts used by the MMC controller. |
| 8 | |
Chris Ball | abe1e05 | 2012-08-22 13:21:01 -0400 | [diff] [blame] | 9 | Card detection: |
Guennadi Liakhovetski | b477426 | 2013-01-16 17:20:41 +0100 | [diff] [blame] | 10 | If no property below is supplied, host native card detect is used. |
Chris Ball | abe1e05 | 2012-08-22 13:21:01 -0400 | [diff] [blame] | 11 | Only one of the properties in this section should be supplied: |
| 12 | - broken-cd: There is no card detection available; polling must be used. |
| 13 | - cd-gpios: Specify GPIOs for card detection, see gpio binding |
| 14 | - non-removable: non-removable slot (like eMMC); assume always present. |
| 15 | |
Arnd Bergmann | 7f21779 | 2012-05-13 00:14:24 -0400 | [diff] [blame] | 16 | Optional properties: |
Shawn Guo | 28c2a62 | 2013-01-28 16:49:11 -0500 | [diff] [blame] | 17 | - bus-width: Number of data lines, can be <1>, <4>, or <8>. The default |
| 18 | will be <1> if the property is absent. |
Chris Ball | ed3efc1 | 2012-06-11 22:06:43 -0400 | [diff] [blame] | 19 | - wp-gpios: Specify GPIOs for write protection, see gpio binding |
Guennadi Liakhovetski | 6da15e9 | 2013-02-15 16:13:51 +0100 | [diff] [blame] | 20 | - cd-inverted: when present, polarity on the CD line is inverted. See the note |
| 21 | below for the case, when a GPIO is used for the CD line |
| 22 | - wp-inverted: when present, polarity on the WP line is inverted. See the note |
| 23 | below for the case, when a GPIO is used for the WP line |
Arnd Bergmann | 7f21779 | 2012-05-13 00:14:24 -0400 | [diff] [blame] | 24 | - max-frequency: maximum operating clock frequency |
Daniel Drake | 8ed765a | 2012-11-25 13:02:54 -0500 | [diff] [blame] | 25 | - no-1-8-v: when present, denotes that 1.8v card voltage is not supported on |
| 26 | this system, even if the controller claims it is. |
Guennadi Liakhovetski | 2fdb6e2 | 2013-02-15 16:14:01 +0100 | [diff] [blame] | 27 | - cap-sd-highspeed: SD high-speed timing is supported |
| 28 | - cap-mmc-highspeed: MMC high-speed timing is supported |
Ulf Hansson | b66bd0e | 2014-02-14 13:27:07 +0100 | [diff] [blame] | 29 | - sd-uhs-sdr12: SD UHS SDR12 speed is supported |
| 30 | - sd-uhs-sdr25: SD UHS SDR25 speed is supported |
| 31 | - sd-uhs-sdr50: SD UHS SDR50 speed is supported |
| 32 | - sd-uhs-sdr104: SD UHS SDR104 speed is supported |
| 33 | - sd-uhs-ddr50: SD UHS DDR50 speed is supported |
Guennadi Liakhovetski | 2fdb6e2 | 2013-02-15 16:14:01 +0100 | [diff] [blame] | 34 | - cap-power-off-card: powering off the card is safe |
| 35 | - cap-sdio-irq: enable SDIO IRQ signalling on this interface |
Ulf Hansson | 5a36d6b | 2013-06-10 17:03:47 +0200 | [diff] [blame] | 36 | - full-pwr-cycle: full power cycle of the card is supported |
Peter Griffin | 87a0f46 | 2014-06-16 12:06:36 +0100 | [diff] [blame^] | 37 | - mmc-ddr-1_8v: eMMC high-speed DDR mode(1.8V I/O) is supported |
| 38 | - mmc-ddr-1_2v: eMMC high-speed DDR mode(1.2V I/O) is supported |
Jaehoon Chung | 321bd41 | 2014-02-14 13:27:09 +0100 | [diff] [blame] | 39 | - mmc-hs200-1_8v: eMMC HS200 mode(1.8V I/O) is supported |
| 40 | - mmc-hs200-1_2v: eMMC HS200 mode(1.2V I/O) is supported |
Seungwon Jeon | c373eb4 | 2014-04-23 17:15:08 +0900 | [diff] [blame] | 41 | - mmc-hs400-1_8v: eMMC HS400 mode(1.8V I/O) is supported |
| 42 | - mmc-hs400-1_2v: eMMC HS400 mode(1.2V I/O) is supported |
Arnd Bergmann | 7f21779 | 2012-05-13 00:14:24 -0400 | [diff] [blame] | 43 | |
Guennadi Liakhovetski | 6da15e9 | 2013-02-15 16:13:51 +0100 | [diff] [blame] | 44 | *NOTE* on CD and WP polarity. To use common for all SD/MMC host controllers line |
| 45 | polarity properties, we have to fix the meaning of the "normal" and "inverted" |
| 46 | line levels. We choose to follow the SDHCI standard, which specifies both those |
| 47 | lines as "active low." Therefore, using the "cd-inverted" property means, that |
| 48 | the CD line is active high, i.e. it is high, when a card is inserted. Similar |
| 49 | logic applies to the "wp-inverted" property. |
| 50 | |
| 51 | CD and WP lines can be implemented on the hardware in one of two ways: as GPIOs, |
| 52 | specified in cd-gpios and wp-gpios properties, or as dedicated pins. Polarity of |
| 53 | dedicated pins can be specified, using *-inverted properties. GPIO polarity can |
| 54 | also be specified using the OF_GPIO_ACTIVE_LOW flag. This creates an ambiguity |
| 55 | in the latter case. We choose to use the XOR logic for GPIO CD and WP lines. |
| 56 | This means, the two properties are "superimposed," for example leaving the |
| 57 | OF_GPIO_ACTIVE_LOW flag clear and specifying the respective *-inverted |
| 58 | property results in a double-inversion and actually means the "normal" line |
| 59 | polarity is in effect. |
| 60 | |
Abhilash Kesavan | e5d0e9c | 2012-11-19 10:26:19 +0530 | [diff] [blame] | 61 | Optional SDIO properties: |
| 62 | - keep-power-in-suspend: Preserves card power during a suspend/resume cycle |
| 63 | - enable-sdio-wakeup: Enables wake up of host system on SDIO IRQ assertion |
| 64 | |
Arnd Bergmann | 7f21779 | 2012-05-13 00:14:24 -0400 | [diff] [blame] | 65 | Example: |
| 66 | |
| 67 | sdhci@ab000000 { |
| 68 | compatible = "sdhci"; |
| 69 | reg = <0xab000000 0x200>; |
| 70 | interrupts = <23>; |
| 71 | bus-width = <4>; |
| 72 | cd-gpios = <&gpio 69 0>; |
| 73 | cd-inverted; |
| 74 | wp-gpios = <&gpio 70 0>; |
| 75 | max-frequency = <50000000>; |
Abhilash Kesavan | e5d0e9c | 2012-11-19 10:26:19 +0530 | [diff] [blame] | 76 | keep-power-in-suspend; |
| 77 | enable-sdio-wakeup; |
Arnd Bergmann | 7f21779 | 2012-05-13 00:14:24 -0400 | [diff] [blame] | 78 | } |