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gerrit-public.fairphone.software / kernel / msm-4.9 / 8810e5fa00a49d4fd010eaa48732191b32fcbfbe / . / arch / arm64 / boot / dts / qcom / sdm845-coresight.dtsi
blob: d36c0ffae6e05c3d19aeeb65da75f9117ad04091 [file] [log] [blame]
Satyajit Desaib3039812017-01-30 11:34:03 -0800[diff] [blame]1/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
Satyajit Desai84bde122016-09-13 14:36:11 -0700[diff] [blame]2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13&soc {
14
15 replicator_qdss: replicator@6046000 {
16 compatible = "arm,coresight-replicator";
17
18 coresight-name = "coresight-replicator";
19
20 ports{
21 #address-cells = <1>;
22 #size-cells = <0>;
23
24 port@0 {
25 reg = <0>;
26 replicator_out_tmc_etr: endpoint {
27 remote-endpoint=
28 <&tmc_etr_in_replicator>;
29 };
30 };
31
32 port@1 {
33 reg = <0>;
34 replicator_in_tmc_etf: endpoint {
35 slave-mode;
36 remote-endpoint=
37 <&tmc_etf_out_replicator>;
38 };
39 };
40 };
41 };
42
43 tmc_etr:tmc@6048000 {
44 compatible = "arm,primecell";
45 arm,primecell-periphid = <0x0003b961>;
46
47 reg = <0x6048000 0x1000>,
48 <0x6064000 0x15000>;
49 reg-names = "tmc-base", "bam-base";
50
51 arm,buffer-size = <0x400000>;
52
53 coresight-name = "coresight-tmc-etr";
Satyajit Desaib3039812017-01-30 11:34:03 -0800[diff] [blame]54 coresight-ctis = <&cti0 &cti8>;
Satyajit Desai84bde122016-09-13 14:36:11 -0700[diff] [blame]55
56 clocks = <&clock_gcc RPMH_QDSS_CLK>,
57 <&clock_gcc RPMH_QDSS_A_CLK>;
58 clock-names = "apb_pclk", "core_a_clk";
59
60 port {
61 tmc_etr_in_replicator: endpoint {
62 slave-mode;
63 remote-endpoint = <&replicator_out_tmc_etr>;
64 };
65 };
66 };
67
68 tmc_etf:tmc@6047000 {
69 compatible = "arm,primecell";
70 arm,primecell-periphid = <0x0003b961>;
71
72 reg = <0x6047000 0x1000>;
73 reg-names = "tmc-base";
74
75 coresight-name = "coresight-tmc-etf";
Satyajit Desaib3039812017-01-30 11:34:03 -0800[diff] [blame]76 coresight-ctis = <&cti0 &cti8>;
Satyajit Desai84bde122016-09-13 14:36:11 -0700[diff] [blame]77 arm,default-sink;
78
79 clocks = <&clock_gcc RPMH_QDSS_CLK>,
80 <&clock_gcc RPMH_QDSS_A_CLK>;
81 clock-names = "apb_pclk", "core_a_clk";
82
83 ports {
84 #address-cells = <1>;
85 #size-cells = <0>;
86
87 port@0 {
88 reg = <0>;
89 tmc_etf_out_replicator: endpoint {
90 remote-endpoint =
91 <&replicator_in_tmc_etf>;
92 };
93 };
94
95 port@1 {
96 reg = <1>;
97 tmc_etf_in_funnel_merg: endpoint {
98 slave-mode;
99 remote-endpoint =
100 <&funnel_merg_out_tmc_etf>;
101 };
102 };
103 };
104
105 };
106
107 stm: stm@6002000 {
108 compatible = "arm,primecell";
109 arm,primecell-periphid = <0x0003b962>;
110
111 reg = <0x6002000 0x1000>,
112 <0x16280000 0x180000>;
113 reg-names = "stm-base", "stm-stimulus-base";
114
115 coresight-name = "coresight-stm";
116
117 clocks = <&clock_gcc RPMH_QDSS_CLK>,
118 <&clock_gcc RPMH_QDSS_A_CLK>;
119 clock-names = "apb_pclk", "core_a_clk";
120
121 port {
122 stm_out_funnel_in0: endpoint {
123 remote-endpoint = <&funnel_in0_in_stm>;
124 };
125 };
126
127 };
128
129 funnel_in0: funnel@0x6041000 {
130 compatible = "arm,primecell";
131 arm,primecell-periphid = <0x0003b908>;
132
133 reg = <0x6041000 0x1000>;
134 reg-names = "funnel-base";
135
136 coresight-name = "coresight-funnel-in0";
137
138 clocks = <&clock_gcc RPMH_QDSS_CLK>,
139 <&clock_gcc RPMH_QDSS_A_CLK>;
140 clock-names = "apb_pclk", "core_a_clk";
141
142 ports {
143 #address-cells = <1>;
144 #size-cells = <0>;
145
146 port@0 {
147 reg = <0>;
148 funnel_in0_out_funnel_merg: endpoint {
149 remote-endpoint =
150 <&funnel_merg_in_funnel_in0>;
151 };
152 };
153
154 port@1 {
155 reg = <7>;
156 funnel_in0_in_stm: endpoint {
157 slave-mode;
158 remote-endpoint = <&stm_out_funnel_in0>;
159 };
160 };
161 };
162 };
163
164 funnel_merg:funnel@6045000 {
165 compatible = "arm,primecell";
166 arm,primecell-periphid = <0x0003b908>;
167
168 reg = <0x6045000 0x1000>;
169 reg-names = "funnel-base";
170
171 coresight-name = "coresight-funnel-merg";
172
173 clocks = <&clock_gcc RPMH_QDSS_CLK>,
174 <&clock_gcc RPMH_QDSS_A_CLK>;
175 clock-names = "apb_pclk", "core_a_clk";
176
177 ports {
178 #address-cells = <1>;
179 #size-cells = <0>;
180
181 port@0 {
182 reg = <0>;
183 funnel_merg_out_tmc_etf: endpoint {
184 remote-endpoint =
185 <&tmc_etf_in_funnel_merg>;
186 };
187 };
188
189 port@1 {
190 reg = <0>;
191 funnel_merg_in_funnel_in0: endpoint {
192 slave-mode;
193 remote-endpoint =
194 <&funnel_in0_out_funnel_merg>;
195 };
196 };
197 };
198 };
Satyajit Desaib3039812017-01-30 11:34:03 -0800[diff] [blame]199
200 cti0: cti@6010000 {
201 compatible = "arm,coresight-cti";
202 reg = <0x6010000 0x1000>;
203 reg-names = "cti-base";
204
205 coresight-name = "coresight-cti0";
206
207 clocks = <&clock_gcc RPMH_QDSS_CLK>,
208 <&clock_gcc RPMH_QDSS_A_CLK>;
209 clock-names = "core_clk", "core_a_clk";
210 };
211
212 cti1: cti@6011000 {
213 compatible = "arm,coresight-cti";
214 reg = <0x6011000 0x1000>;
215 reg-names = "cti-base";
216
217 coresight-name = "coresight-cti1";
218
219 clocks = <&clock_gcc RPMH_QDSS_CLK>,
220 <&clock_gcc RPMH_QDSS_A_CLK>;
221 clock-names = "core_clk", "core_a_clk";
222 };
223
224 cti2: cti@6012000 {
225 compatible = "arm,coresight-cti";
226 reg = <0x6012000 0x1000>;
227 reg-names = "cti-base";
228
229 coresight-name = "coresight-cti2";
230
231 clocks = <&clock_gcc RPMH_QDSS_CLK>,
232 <&clock_gcc RPMH_QDSS_A_CLK>;
233 clock-names = "core_clk", "core_a_clk";
234 };
235
236 cti3: cti@6013000 {
237 compatible = "arm,coresight-cti";
238 reg = <0x6013000 0x1000>;
239 reg-names = "cti-base";
240
241 coresight-name = "coresight-cti3";
242
243 clocks = <&clock_gcc RPMH_QDSS_CLK>,
244 <&clock_gcc RPMH_QDSS_A_CLK>;
245 clock-names = "core_clk", "core_a_clk";
246 };
247
248 cti4: cti@6014000 {
249 compatible = "arm,coresight-cti";
250 reg = <0x6014000 0x1000>;
251 reg-names = "cti-base";
252
253 coresight-name = "coresight-cti4";
254
255 clocks = <&clock_gcc RPMH_QDSS_CLK>,
256 <&clock_gcc RPMH_QDSS_A_CLK>;
257 clock-names = "core_clk", "core_a_clk";
258 };
259
260 cti5: cti@6015000 {
261 compatible = "arm,coresight-cti";
262 reg = <0x6015000 0x1000>;
263 reg-names = "cti-base";
264
265 coresight-name = "coresight-cti5";
266
267 clocks = <&clock_gcc RPMH_QDSS_CLK>,
268 <&clock_gcc RPMH_QDSS_A_CLK>;
269 clock-names = "core_clk", "core_a_clk";
270 };
271
272 cti6: cti@6016000 {
273 compatible = "arm,coresight-cti";
274 reg = <0x6016000 0x1000>;
275 reg-names = "cti-base";
276
277 coresight-name = "coresight-cti6";
278
279 clocks = <&clock_gcc RPMH_QDSS_CLK>,
280 <&clock_gcc RPMH_QDSS_A_CLK>;
281 clock-names = "core_clk", "core_a_clk";
282 };
283
284 cti7: cti@6017000 {
285 compatible = "arm,coresight-cti";
286 reg = <0x6017000 0x1000>;
287 reg-names = "cti-base";
288
289 coresight-name = "coresight-cti7";
290
291 clocks = <&clock_gcc RPMH_QDSS_CLK>,
292 <&clock_gcc RPMH_QDSS_A_CLK>;
293 clock-names = "core_clk", "core_a_clk";
294 };
295
296 cti8: cti@6018000 {
297 compatible = "arm,coresight-cti";
298 reg = <0x6018000 0x1000>;
299 reg-names = "cti-base";
300
301 coresight-name = "coresight-cti8";
302
303 clocks = <&clock_gcc RPMH_QDSS_CLK>,
304 <&clock_gcc RPMH_QDSS_A_CLK>;
305 clock-names = "core_clk", "core_a_clk";
306 };
307
308 cti9: cti@6019000 {
309 compatible = "arm,coresight-cti";
310 reg = <0x6019000 0x1000>;
311 reg-names = "cti-base";
312
313 coresight-name = "coresight-cti9";
314
315 clocks = <&clock_gcc RPMH_QDSS_CLK>,
316 <&clock_gcc RPMH_QDSS_A_CLK>;
317 clock-names = "core_clk", "core_a_clk";
318 };
319
320 cti10: cti@601a000 {
321 compatible = "arm,coresight-cti";
322 reg = <0x601a000 0x1000>;
323 reg-names = "cti-base";
324
325 coresight-name = "coresight-cti10";
326
327 clocks = <&clock_gcc RPMH_QDSS_CLK>,
328 <&clock_gcc RPMH_QDSS_A_CLK>;
329 clock-names = "core_clk", "core_a_clk";
330 };
331
332 cti11: cti@601b000 {
333 compatible = "arm,coresight-cti";
334 reg = <0x601b000 0x1000>;
335 reg-names = "cti-base";
336
337 coresight-name = "coresight-cti11";
338
339 clocks = <&clock_gcc RPMH_QDSS_CLK>,
340 <&clock_gcc RPMH_QDSS_A_CLK>;
341 clock-names = "core_clk", "core_a_clk";
342 };
343
344 cti12: cti@601c000 {
345 compatible = "arm,coresight-cti";
346 reg = <0x601c000 0x1000>;
347 reg-names = "cti-base";
348
349 coresight-name = "coresight-cti12";
350
351 clocks = <&clock_gcc RPMH_QDSS_CLK>,
352 <&clock_gcc RPMH_QDSS_A_CLK>;
353 clock-names = "core_clk", "core_a_clk";
354 };
355
356 cti13: cti@601d000 {
357 compatible = "arm,coresight-cti";
358 reg = <0x601d000 0x1000>;
359 reg-names = "cti-base";
360
361 coresight-name = "coresight-cti13";
362
363 clocks = <&clock_gcc RPMH_QDSS_CLK>,
364 <&clock_gcc RPMH_QDSS_A_CLK>;
365 clock-names = "core_clk", "core_a_clk";
366 };
367
368 cti14: cti@601e000 {
369 compatible = "arm,coresight-cti";
370 reg = <0x601e000 0x1000>;
371 reg-names = "cti-base";
372
373 coresight-name = "coresight-cti14";
374
375 clocks = <&clock_gcc RPMH_QDSS_CLK>,
376 <&clock_gcc RPMH_QDSS_A_CLK>;
377 clock-names = "core_clk", "core_a_clk";
378 };
379
380 cti15: cti@601f000 {
381 compatible = "arm,coresight-cti";
382 reg = <0x601f000 0x1000>;
383 reg-names = "cti-base";
384
385 coresight-name = "coresight-cti15";
386
387 clocks = <&clock_gcc RPMH_QDSS_CLK>,
388 <&clock_gcc RPMH_QDSS_A_CLK>;
389 clock-names = "core_clk", "core_a_clk";
390 };
391
392 cti_cpu0: cti@7420000 {
393 compatible = "arm,coresight-cti";
394 reg = <0x7420000 0x1000>;
395 reg-names = "cti-base";
396
397 coresight-name = "coresight-cti-cpu0";
398 cpu = <&CPU0>;
399
400 clocks = <&clock_gcc RPMH_QDSS_CLK>,
401 <&clock_gcc RPMH_QDSS_A_CLK>;
402 clock-names = "core_clk", "core_a_clk";
403 };
404
405 cti_cpu1: cti@7520000 {
406 compatible = "arm,coresight-cti";
407 reg = <0x7520000 0x1000>;
408 reg-names = "cti-base";
409
410 coresight-name = "coresight-cti-cpu1";
411 cpu = <&CPU1>;
412
413 clocks = <&clock_gcc RPMH_QDSS_CLK>,
414 <&clock_gcc RPMH_QDSS_A_CLK>;
415 clock-names = "core_clk", "core_a_clk";
416 };
417
418 cti_cpu2: cti@7620000 {
419 compatible = "arm,coresight-cti";
420 reg = <0x7620000 0x1000>;
421 reg-names = "cti-base";
422
423 coresight-name = "coresight-cti-cpu2";
424 cpu = <&CPU2>;
425
426 clocks = <&clock_gcc RPMH_QDSS_CLK>,
427 <&clock_gcc RPMH_QDSS_A_CLK>;
428 clock-names = "core_clk", "core_a_clk";
429 };
430
431 cti_cpu3: cti@7720000 {
432 compatible = "arm,coresight-cti";
433 reg = <0x7720000 0x1000>;
434 reg-names = "cti-base";
435
436 coresight-name = "coresight-cti-cpu3";
437 cpu = <&CPU3>;
438
439 clocks = <&clock_gcc RPMH_QDSS_CLK>,
440 <&clock_gcc RPMH_QDSS_A_CLK>;
441 clock-names = "core_clk", "core_a_clk";
442 };
443
444 cti_cpu4: cti@7020000 {
445 compatible = "arm,coresight-cti";
446 reg = <0x7020000 0x1000>;
447 reg-names = "cti-base";
448
449 coresight-name = "coresight-cti-cpu4";
450 cpu = <&CPU4>;
451
452 clocks = <&clock_gcc RPMH_QDSS_CLK>,
453 <&clock_gcc RPMH_QDSS_A_CLK>;
454 clock-names = "core_clk", "core_a_clk";
455 };
456
457 cti_cpu5: cti@7120000 {
458 compatible = "arm,coresight-cti";
459 reg = <0x7120000 0x1000>;
460 reg-names = "cti-base";
461
462 coresight-name = "coresight-cti-cpu5";
463 cpu = <&CPU5>;
464
465 clocks = <&clock_gcc RPMH_QDSS_CLK>,
466 <&clock_gcc RPMH_QDSS_A_CLK>;
467 clock-names = "core_clk", "core_a_clk";
468 };
469
470 cti_cpu6: cti@7220000 {
471 compatible = "arm,coresight-cti";
472 reg = <0x7220000 0x1000>;
473 reg-names = "cti-base";
474
475 coresight-name = "coresight-cti-cpu6";
476 cpu = <&CPU6>;
477
478 clocks = <&clock_gcc RPMH_QDSS_CLK>,
479 <&clock_gcc RPMH_QDSS_A_CLK>;
480 clock-names = "core_clk", "core_a_clk";
481 };
482
483 cti_cpu7: cti@7320000 {
484 compatible = "arm,coresight-cti";
485 reg = <0x7320000 0x1000>;
486 reg-names = "cti-base";
487
488 coresight-name = "coresight-cti-cpu7";
489 cpu = <&CPU7>;
490
491 clocks = <&clock_gcc RPMH_QDSS_CLK>,
492 <&clock_gcc RPMH_QDSS_A_CLK>;
493 clock-names = "core_clk", "core_a_clk";
494 };
Satyajit Desai84bde122016-09-13 14:36:11 -0700[diff] [blame]495};