blob: 793518a30afe6c97a97bfe5db1d62cb1651077c1 [file] [log] [blame]
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +02001/*
Liu Gang42178e22016-02-03 19:27:34 +08002 * GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +02003 *
4 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
Liu Gang42178e22016-02-03 19:27:34 +08005 * Copyright (C) 2016 Freescale Semiconductor Inc.
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +02006 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/spinlock.h>
15#include <linux/io.h>
16#include <linux/of.h>
17#include <linux/of_gpio.h>
Liu Gang42178e22016-02-03 19:27:34 +080018#include <linux/of_address.h>
Rob Herring5af50732013-09-17 14:28:33 -050019#include <linux/of_irq.h>
Ricardo Ribalda Delgado98686d9a52015-01-18 12:39:32 +010020#include <linux/of_platform.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090021#include <linux/slab.h>
Peter Korsgaard345e5c82010-01-07 17:57:46 +010022#include <linux/irq.h>
Liu Gang42178e22016-02-03 19:27:34 +080023#include <linux/gpio/driver.h>
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +020024
25#define MPC8XXX_GPIO_PINS 32
26
27#define GPIO_DIR 0x00
28#define GPIO_ODR 0x04
29#define GPIO_DAT 0x08
30#define GPIO_IER 0x0c
31#define GPIO_IMR 0x10
32#define GPIO_ICR 0x14
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +020033#define GPIO_ICR2 0x18
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +020034
35struct mpc8xxx_gpio_chip {
Liu Gang42178e22016-02-03 19:27:34 +080036 struct gpio_chip gc;
37 void __iomem *regs;
Alexander Stein50593612015-07-21 15:54:30 +020038 raw_spinlock_t lock;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +020039
Liu Gang42178e22016-02-03 19:27:34 +080040 int (*direction_output)(struct gpio_chip *chip,
41 unsigned offset, int value);
42
Grant Likelybae1d8f2012-02-14 14:06:50 -070043 struct irq_domain *irq;
Ricardo Ribalda Delgado257e1072015-01-18 12:39:33 +010044 unsigned int irqn;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +020045};
46
Felix Radenskyc1a676d2009-08-12 08:57:39 +030047/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
48 * defined as output cannot be determined by reading GPDAT register,
49 * so we use shadow data register instead. The status of input pins
50 * is determined by reading GPDAT register.
51 */
52static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
53{
54 u32 val;
Linus Walleij709d71a2015-12-07 10:34:28 +010055 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
Liu Gang1aeef302013-11-22 16:12:40 +080056 u32 out_mask, out_shadow;
Felix Radenskyc1a676d2009-08-12 08:57:39 +030057
Axel Lincd0d3f52016-02-22 15:24:01 +080058 out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
59 val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask;
Liu Gang42178e22016-02-03 19:27:34 +080060 out_shadow = gc->bgpio_data & out_mask;
Felix Radenskyc1a676d2009-08-12 08:57:39 +030061
Liu Gang42178e22016-02-03 19:27:34 +080062 return !!((val | out_shadow) & gc->pin2mask(gc, gpio));
Felix Radenskyc1a676d2009-08-12 08:57:39 +030063}
64
Liu Gang42178e22016-02-03 19:27:34 +080065static int mpc5121_gpio_dir_out(struct gpio_chip *gc,
66 unsigned int gpio, int val)
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +020067{
Linus Walleij709d71a2015-12-07 10:34:28 +010068 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
Wolfram Sang28538df2011-12-13 10:12:48 +010069 /* GPIO 28..31 are input only on MPC5121 */
70 if (gpio >= 28)
71 return -EINVAL;
72
Liu Gang42178e22016-02-03 19:27:34 +080073 return mpc8xxx_gc->direction_output(gc, gpio, val);
Wolfram Sang28538df2011-12-13 10:12:48 +010074}
75
Liu Gang42178e22016-02-03 19:27:34 +080076static int mpc5125_gpio_dir_out(struct gpio_chip *gc,
77 unsigned int gpio, int val)
Uwe Kleine-König0ba69e02015-07-16 21:08:23 +020078{
Liu Gang42178e22016-02-03 19:27:34 +080079 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
Uwe Kleine-König0ba69e02015-07-16 21:08:23 +020080 /* GPIO 0..3 are input only on MPC5125 */
81 if (gpio <= 3)
82 return -EINVAL;
83
Liu Gang42178e22016-02-03 19:27:34 +080084 return mpc8xxx_gc->direction_output(gc, gpio, val);
Uwe Kleine-König0ba69e02015-07-16 21:08:23 +020085}
86
Peter Korsgaard345e5c82010-01-07 17:57:46 +010087static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
88{
Linus Walleij709d71a2015-12-07 10:34:28 +010089 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
Peter Korsgaard345e5c82010-01-07 17:57:46 +010090
91 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
92 return irq_create_mapping(mpc8xxx_gc->irq, offset);
93 else
94 return -ENXIO;
95}
96
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +020097static void mpc8xxx_gpio_irq_cascade(struct irq_desc *desc)
Peter Korsgaard345e5c82010-01-07 17:57:46 +010098{
Thomas Gleixnerec775d02011-03-25 16:45:20 +010099 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
Felix Radenskycfadd832011-10-11 10:24:21 +0200100 struct irq_chip *chip = irq_desc_get_chip(desc);
Axel Lincd0d3f52016-02-22 15:24:01 +0800101 struct gpio_chip *gc = &mpc8xxx_gc->gc;
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100102 unsigned int mask;
103
Axel Lincd0d3f52016-02-22 15:24:01 +0800104 mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)
105 & gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100106 if (mask)
107 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
108 32 - ffs(mask)));
Thomas Gleixnerd6de85e2012-05-03 12:22:06 +0200109 if (chip->irq_eoi)
110 chip->irq_eoi(&desc->irq_data);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100111}
112
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000113static void mpc8xxx_irq_unmask(struct irq_data *d)
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100114{
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000115 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
Liu Gang42178e22016-02-03 19:27:34 +0800116 struct gpio_chip *gc = &mpc8xxx_gc->gc;
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100117 unsigned long flags;
118
Alexander Stein50593612015-07-21 15:54:30 +0200119 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100120
Axel Lincd0d3f52016-02-22 15:24:01 +0800121 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
122 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
Liu Gang42178e22016-02-03 19:27:34 +0800123 | gc->pin2mask(gc, irqd_to_hwirq(d)));
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100124
Alexander Stein50593612015-07-21 15:54:30 +0200125 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100126}
127
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000128static void mpc8xxx_irq_mask(struct irq_data *d)
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100129{
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000130 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
Liu Gang42178e22016-02-03 19:27:34 +0800131 struct gpio_chip *gc = &mpc8xxx_gc->gc;
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100132 unsigned long flags;
133
Alexander Stein50593612015-07-21 15:54:30 +0200134 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100135
Axel Lincd0d3f52016-02-22 15:24:01 +0800136 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
137 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
Liu Gang42178e22016-02-03 19:27:34 +0800138 & ~(gc->pin2mask(gc, irqd_to_hwirq(d))));
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100139
Alexander Stein50593612015-07-21 15:54:30 +0200140 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100141}
142
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000143static void mpc8xxx_irq_ack(struct irq_data *d)
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100144{
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000145 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
Liu Gang42178e22016-02-03 19:27:34 +0800146 struct gpio_chip *gc = &mpc8xxx_gc->gc;
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100147
Axel Lincd0d3f52016-02-22 15:24:01 +0800148 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER,
149 gc->pin2mask(gc, irqd_to_hwirq(d)));
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100150}
151
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000152static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100153{
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000154 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
Liu Gang42178e22016-02-03 19:27:34 +0800155 struct gpio_chip *gc = &mpc8xxx_gc->gc;
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100156 unsigned long flags;
157
158 switch (flow_type) {
159 case IRQ_TYPE_EDGE_FALLING:
Alexander Stein50593612015-07-21 15:54:30 +0200160 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
Axel Lincd0d3f52016-02-22 15:24:01 +0800161 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
162 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
Liu Gang42178e22016-02-03 19:27:34 +0800163 | gc->pin2mask(gc, irqd_to_hwirq(d)));
Alexander Stein50593612015-07-21 15:54:30 +0200164 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100165 break;
166
167 case IRQ_TYPE_EDGE_BOTH:
Alexander Stein50593612015-07-21 15:54:30 +0200168 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
Axel Lincd0d3f52016-02-22 15:24:01 +0800169 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
170 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
Liu Gang42178e22016-02-03 19:27:34 +0800171 & ~(gc->pin2mask(gc, irqd_to_hwirq(d))));
Alexander Stein50593612015-07-21 15:54:30 +0200172 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100173 break;
174
175 default:
176 return -EINVAL;
177 }
178
179 return 0;
180}
181
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000182static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200183{
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000184 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
Axel Lincd0d3f52016-02-22 15:24:01 +0800185 struct gpio_chip *gc = &mpc8xxx_gc->gc;
Grant Likely476eb492011-05-04 15:02:15 +1000186 unsigned long gpio = irqd_to_hwirq(d);
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200187 void __iomem *reg;
188 unsigned int shift;
189 unsigned long flags;
190
191 if (gpio < 16) {
Liu Gang42178e22016-02-03 19:27:34 +0800192 reg = mpc8xxx_gc->regs + GPIO_ICR;
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200193 shift = (15 - gpio) * 2;
194 } else {
Liu Gang42178e22016-02-03 19:27:34 +0800195 reg = mpc8xxx_gc->regs + GPIO_ICR2;
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200196 shift = (15 - (gpio % 16)) * 2;
197 }
198
199 switch (flow_type) {
200 case IRQ_TYPE_EDGE_FALLING:
201 case IRQ_TYPE_LEVEL_LOW:
Alexander Stein50593612015-07-21 15:54:30 +0200202 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
Axel Lincd0d3f52016-02-22 15:24:01 +0800203 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
Liu Gang42178e22016-02-03 19:27:34 +0800204 | (2 << shift));
Alexander Stein50593612015-07-21 15:54:30 +0200205 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200206 break;
207
208 case IRQ_TYPE_EDGE_RISING:
209 case IRQ_TYPE_LEVEL_HIGH:
Alexander Stein50593612015-07-21 15:54:30 +0200210 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
Axel Lincd0d3f52016-02-22 15:24:01 +0800211 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
Liu Gang42178e22016-02-03 19:27:34 +0800212 | (1 << shift));
Alexander Stein50593612015-07-21 15:54:30 +0200213 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200214 break;
215
216 case IRQ_TYPE_EDGE_BOTH:
Alexander Stein50593612015-07-21 15:54:30 +0200217 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
Axel Lincd0d3f52016-02-22 15:24:01 +0800218 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)));
Alexander Stein50593612015-07-21 15:54:30 +0200219 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200220 break;
221
222 default:
223 return -EINVAL;
224 }
225
226 return 0;
227}
228
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100229static struct irq_chip mpc8xxx_irq_chip = {
230 .name = "mpc8xxx-gpio",
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000231 .irq_unmask = mpc8xxx_irq_unmask,
232 .irq_mask = mpc8xxx_irq_mask,
233 .irq_ack = mpc8xxx_irq_ack,
Uwe Kleine-König82e39b02015-07-16 21:08:22 +0200234 /* this might get overwritten in mpc8xxx_probe() */
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000235 .irq_set_type = mpc8xxx_irq_set_type,
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100236};
237
Linus Walleij5ba17ae2013-10-11 19:37:30 +0200238static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
239 irq_hw_number_t hwirq)
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100240{
Linus Walleij5ba17ae2013-10-11 19:37:30 +0200241 irq_set_chip_data(irq, h->host_data);
Liu Gangd71cf152016-10-21 15:31:28 +0800242 irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_edge_irq);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100243
244 return 0;
245}
246
Krzysztof Kozlowski0b354dc2015-04-27 21:54:07 +0900247static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100248 .map = mpc8xxx_gpio_irq_map,
Grant Likelyff8c3ab2012-01-24 17:09:13 -0700249 .xlate = irq_domain_xlate_twocell,
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100250};
251
Uwe Kleine-König82e39b02015-07-16 21:08:22 +0200252struct mpc8xxx_gpio_devtype {
253 int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int);
254 int (*gpio_get)(struct gpio_chip *, unsigned int);
255 int (*irq_set_type)(struct irq_data *, unsigned int);
256};
257
258static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
259 .gpio_dir_out = mpc5121_gpio_dir_out,
260 .irq_set_type = mpc512x_irq_set_type,
261};
262
Uwe Kleine-König0ba69e02015-07-16 21:08:23 +0200263static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
264 .gpio_dir_out = mpc5125_gpio_dir_out,
265 .irq_set_type = mpc512x_irq_set_type,
266};
267
Uwe Kleine-König82e39b02015-07-16 21:08:22 +0200268static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
269 .gpio_get = mpc8572_gpio_get,
270};
271
272static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
Uwe Kleine-König82e39b02015-07-16 21:08:22 +0200273 .irq_set_type = mpc8xxx_irq_set_type,
274};
275
Uwe Kleine-König4183afe2015-07-16 21:08:21 +0200276static const struct of_device_id mpc8xxx_gpio_ids[] = {
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200277 { .compatible = "fsl,mpc8349-gpio", },
Uwe Kleine-König82e39b02015-07-16 21:08:22 +0200278 { .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200279 { .compatible = "fsl,mpc8610-gpio", },
Uwe Kleine-König82e39b02015-07-16 21:08:22 +0200280 { .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
Uwe Kleine-König0ba69e02015-07-16 21:08:23 +0200281 { .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
Kumar Gala15a51482011-10-22 16:20:42 -0500282 { .compatible = "fsl,pq3-gpio", },
Anatolij Gustschind1dcfbb2011-01-08 16:51:16 +0100283 { .compatible = "fsl,qoriq-gpio", },
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200284 {}
285};
286
Ricardo Ribalda Delgado98686d9a52015-01-18 12:39:32 +0100287static int mpc8xxx_probe(struct platform_device *pdev)
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200288{
Ricardo Ribalda Delgado98686d9a52015-01-18 12:39:32 +0100289 struct device_node *np = pdev->dev.of_node;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200290 struct mpc8xxx_gpio_chip *mpc8xxx_gc;
Liu Gang42178e22016-02-03 19:27:34 +0800291 struct gpio_chip *gc;
Uwe Kleine-König82e39b02015-07-16 21:08:22 +0200292 const struct mpc8xxx_gpio_devtype *devtype =
293 of_device_get_match_data(&pdev->dev);
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200294 int ret;
295
Ricardo Ribalda Delgado98686d9a52015-01-18 12:39:32 +0100296 mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
297 if (!mpc8xxx_gc)
298 return -ENOMEM;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200299
Ricardo Ribalda Delgado257e1072015-01-18 12:39:33 +0100300 platform_set_drvdata(pdev, mpc8xxx_gc);
301
Alexander Stein50593612015-07-21 15:54:30 +0200302 raw_spin_lock_init(&mpc8xxx_gc->lock);
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200303
Liu Gang42178e22016-02-03 19:27:34 +0800304 mpc8xxx_gc->regs = of_iomap(np, 0);
305 if (!mpc8xxx_gc->regs)
306 return -ENOMEM;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200307
Liu Gang42178e22016-02-03 19:27:34 +0800308 gc = &mpc8xxx_gc->gc;
309
310 if (of_property_read_bool(np, "little-endian")) {
311 ret = bgpio_init(gc, &pdev->dev, 4,
312 mpc8xxx_gc->regs + GPIO_DAT,
313 NULL, NULL,
314 mpc8xxx_gc->regs + GPIO_DIR, NULL,
315 BGPIOF_BIG_ENDIAN);
316 if (ret)
317 goto err;
318 dev_dbg(&pdev->dev, "GPIO registers are LITTLE endian\n");
319 } else {
320 ret = bgpio_init(gc, &pdev->dev, 4,
321 mpc8xxx_gc->regs + GPIO_DAT,
322 NULL, NULL,
323 mpc8xxx_gc->regs + GPIO_DIR, NULL,
324 BGPIOF_BIG_ENDIAN
325 | BGPIOF_BIG_ENDIAN_BYTE_ORDER);
326 if (ret)
327 goto err;
328 dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n");
329 }
330
Axel Linfa4007c2016-02-22 15:22:52 +0800331 mpc8xxx_gc->direction_output = gc->direction_output;
Uwe Kleine-König82e39b02015-07-16 21:08:22 +0200332
333 if (!devtype)
334 devtype = &mpc8xxx_gpio_devtype_default;
335
336 /*
337 * It's assumed that only a single type of gpio controller is available
338 * on the current machine, so overwriting global data is fine.
339 */
340 mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;
341
Axel Linadf32ea2016-02-22 15:24:54 +0800342 if (devtype->gpio_dir_out)
343 gc->direction_output = devtype->gpio_dir_out;
344 if (devtype->gpio_get)
345 gc->get = devtype->gpio_get;
346
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100347 gc->to_irq = mpc8xxx_gpio_to_irq;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200348
Liu Gang42178e22016-02-03 19:27:34 +0800349 ret = gpiochip_add_data(gc, mpc8xxx_gc);
350 if (ret) {
351 pr_err("%s: GPIO chip registration failed with status %d\n",
352 np->full_name, ret);
353 goto err;
354 }
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200355
Ricardo Ribalda Delgado257e1072015-01-18 12:39:33 +0100356 mpc8xxx_gc->irqn = irq_of_parse_and_map(np, 0);
Liu Gang42178e22016-02-03 19:27:34 +0800357 if (!mpc8xxx_gc->irqn)
Ricardo Ribalda Delgado98686d9a52015-01-18 12:39:32 +0100358 return 0;
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100359
Grant Likelya8db8cf2012-02-14 14:06:54 -0700360 mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
361 &mpc8xxx_gpio_irq_ops, mpc8xxx_gc);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100362 if (!mpc8xxx_gc->irq)
Ricardo Ribalda Delgado98686d9a52015-01-18 12:39:32 +0100363 return 0;
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100364
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100365 /* ack and mask all irqs */
Axel Lincd0d3f52016-02-22 15:24:01 +0800366 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
367 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100368
Thomas Gleixner05379812015-06-21 21:10:46 +0200369 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn,
370 mpc8xxx_gpio_irq_cascade, mpc8xxx_gc);
Ricardo Ribalda Delgado257e1072015-01-18 12:39:33 +0100371 return 0;
Liu Gang42178e22016-02-03 19:27:34 +0800372err:
373 iounmap(mpc8xxx_gc->regs);
374 return ret;
Ricardo Ribalda Delgado257e1072015-01-18 12:39:33 +0100375}
376
377static int mpc8xxx_remove(struct platform_device *pdev)
378{
379 struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
380
381 if (mpc8xxx_gc->irq) {
Thomas Gleixner05379812015-06-21 21:10:46 +0200382 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
Ricardo Ribalda Delgado257e1072015-01-18 12:39:33 +0100383 irq_domain_remove(mpc8xxx_gc->irq);
384 }
385
Liu Gang42178e22016-02-03 19:27:34 +0800386 gpiochip_remove(&mpc8xxx_gc->gc);
387 iounmap(mpc8xxx_gc->regs);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100388
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200389 return 0;
390}
Ricardo Ribalda Delgado98686d9a52015-01-18 12:39:32 +0100391
392static struct platform_driver mpc8xxx_plat_driver = {
393 .probe = mpc8xxx_probe,
Ricardo Ribalda Delgado257e1072015-01-18 12:39:33 +0100394 .remove = mpc8xxx_remove,
Ricardo Ribalda Delgado98686d9a52015-01-18 12:39:32 +0100395 .driver = {
396 .name = "gpio-mpc8xxx",
397 .of_match_table = mpc8xxx_gpio_ids,
398 },
399};
400
401static int __init mpc8xxx_init(void)
402{
403 return platform_driver_register(&mpc8xxx_plat_driver);
404}
405
406arch_initcall(mpc8xxx_init);