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gerrit-public.fairphone.software / kernel / msm-4.9 / 88ad7266d28e4e6d8bdab0d237e1588370f8062d / . / drivers / phy / phy-qcom-ufs-qmp-v3.h
blob: e9ac76b43812b4b909ac09fd755523d6e9fc3083 [file] [log] [blame]
Subhash Jadavanicce6fbc2016-08-11 11:35:26 -0700[diff] [blame]1/*
2 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 */
14
15#ifndef UFS_QCOM_PHY_QMP_V3_H_
16#define UFS_QCOM_PHY_QMP_V3_H_
17
18#include "phy-qcom-ufs-i.h"
19
20/* QCOM UFS PHY control registers */
21#define COM_OFF(x) (0x000 + x)
22#define PHY_OFF(x) (0xC00 + x)
23#define TX_OFF(n, x) (0x400 + (0x400 * n) + x)
24#define RX_OFF(n, x) (0x600 + (0x400 * n) + x)
25
26/* UFS PHY QSERDES COM registers */
27#define QSERDES_COM_ATB_SEL1 COM_OFF(0x00)
28#define QSERDES_COM_ATB_SEL2 COM_OFF(0x04)
29#define QSERDES_COM_FREQ_UPDATE COM_OFF(0x08)
30#define QSERDES_COM_BG_TIMER COM_OFF(0x0C)
31#define QSERDES_COM_SSC_EN_CENTER COM_OFF(0x10)
32#define QSERDES_COM_SSC_ADJ_PER1 COM_OFF(0x14)
33#define QSERDES_COM_SSC_ADJ_PER2 COM_OFF(0x18)
34#define QSERDES_COM_SSC_PER1 COM_OFF(0x1C)
35#define QSERDES_COM_SSC_PER2 COM_OFF(0x20)
36#define QSERDES_COM_SSC_STEP_SIZE1 COM_OFF(0x24)
37#define QSERDES_COM_SSC_STEP_SIZE2 COM_OFF(0x28)
38#define QSERDES_COM_POST_DIV COM_OFF(0x2C)
39#define QSERDES_COM_POST_DIV_MUX COM_OFF(0x30)
40#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN COM_OFF(0x34)
41#define QSERDES_COM_CLK_ENABLE1 COM_OFF(0x38)
42#define QSERDES_COM_SYS_CLK_CTRL COM_OFF(0x3C)
43#define QSERDES_COM_SYSCLK_BUF_ENABLE COM_OFF(0x40)
44#define QSERDES_COM_PLL_EN COM_OFF(0x44)
45#define QSERDES_COM_PLL_IVCO COM_OFF(0x48)
46#define QSERDES_COM_CMN_IETRIM COM_OFF(0x4C)
47#define QSERDES_COM_CMN_IPTRIM COM_OFF(0x50)
48#define QSERDES_COM_EP_CLOCK_DETECT_CTR COM_OFF(0x54)
49#define QSERDES_COM_SYSCLK_DET_COMP_STATUS COM_OFF(0x58)
50#define QSERDES_COM_CLK_EP_DIV COM_OFF(0x5C)
51#define QSERDES_COM_CP_CTRL_MODE0 COM_OFF(0x60)
52#define QSERDES_COM_CP_CTRL_MODE1 COM_OFF(0x64)
53#define QSERDES_COM_PLL_RCTRL_MODE0 COM_OFF(0x68)
54#define QSERDES_COM_PLL_RCTRL_MODE1 COM_OFF(0x6C)
55#define QSERDES_COM_PLL_CCTRL_MODE0 COM_OFF(0x70)
56#define QSERDES_COM_PLL_CCTRL_MODE1 COM_OFF(0x74)
57#define QSERDES_COM_PLL_CNTRL COM_OFF(0x78)
58#define SERDES_COM_BIAS_EN_CTRL_BY_PSM COM_OFF(0x7C)
59#define QSERDES_COM_SYSCLK_EN_SEL COM_OFF(0x80)
60#define QSERDES_COM_CML_SYSCLK_SEL COM_OFF(0x84)
61#define QSERDES_COM_RESETSM_CNTRL COM_OFF(0x88)
62#define QSERDES_COM_RESETSM_CNTRL2 COM_OFF(0x8C)
63#define QSERDES_COM_LOCK_CMP_EN COM_OFF(0x90)
64#define QSERDES_COM_LOCK_CMP_CFG COM_OFF(0x94)
65#define QSERDES_COM_LOCK_CMP1_MODE0 COM_OFF(0x98)
66#define QSERDES_COM_LOCK_CMP2_MODE0 COM_OFF(0x9C)
67#define QSERDES_COM_LOCK_CMP3_MODE0 COM_OFF(0xA0)
68#define QSERDES_COM_LOCK_CMP1_MODE1 COM_OFF(0xA4)
69#define QSERDES_COM_LOCK_CMP2_MODE1 COM_OFF(0xA8)
70#define QSERDES_COM_LOCK_CMP3_MODE1 COM_OFF(0xAC)
71#define QSERDES_COM_DEC_START_MODE0 COM_OFF(0xB0)
72#define QSERDES_COM_DEC_START_MODE1 COM_OFF(0xB4)
73#define QSERDES_COM_DIV_FRAC_START1_MODE0 COM_OFF(0xB8)
74#define QSERDES_COM_DIV_FRAC_START2_MODE0 COM_OFF(0xBC)
75#define QSERDES_COM_DIV_FRAC_START3_MODE0 COM_OFF(0xC0)
76#define QSERDES_COM_DIV_FRAC_START1_MODE1 COM_OFF(0xC4)
77#define QSERDES_COM_DIV_FRAC_START2_MODE1 COM_OFF(0xC8)
78#define QSERDES_COM_DIV_FRAC_START3_MODE1 COM_OFF(0xCC)
79#define QSERDES_COM_INTEGLOOP_INITVAL COM_OFF(0xD0)
80#define QSERDES_COM_INTEGLOOP_EN COM_OFF(0xD4)
81#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 COM_OFF(0xD8)
82#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 COM_OFF(0xDC)
83#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 COM_OFF(0xE0)
84#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 COM_OFF(0xE4)
85#define QSERDES_COM_VCOCAL_DEADMAN_CTRL COM_OFF(0xE8)
86#define QSERDES_COM_VCO_TUNE_CTRL COM_OFF(0xEC)
87#define QSERDES_COM_VCO_TUNE_MAP COM_OFF(0xF0)
88#define QSERDES_COM_VCO_TUNE1_MODE0 COM_OFF(0xF4)
89#define QSERDES_COM_VCO_TUNE2_MODE0 COM_OFF(0xF8)
90#define QSERDES_COM_VCO_TUNE1_MODE1 COM_OFF(0xFC)
91#define QSERDES_COM_VCO_TUNE2_MODE1 COM_OFF(0x100)
92#define QSERDES_COM_VCO_TUNE_INITVAL1 COM_OFF(0x104)
93#define QSERDES_COM_VCO_TUNE_INITVAL2 COM_OFF(0x108)
94#define QSERDES_COM_VCO_TUNE_MINVAL1 COM_OFF(0x10C)
95#define QSERDES_COM_VCO_TUNE_MINVAL2 COM_OFF(0x110)
96#define QSERDES_COM_VCO_TUNE_MAXVAL1 COM_OFF(0x114)
97#define QSERDES_COM_VCO_TUNE_MAXVAL2 COM_OFF(0x118)
98#define QSERDES_COM_VCO_TUNE_TIMER1 COM_OFF(0x11C)
99#define QSERDES_COM_VCO_TUNE_TIMER2 COM_OFF(0x120)
100#define QSERDES_COM_CMN_STATUS COM_OFF(0x124)
101#define QSERDES_COM_RESET_SM_STATUS COM_OFF(0x128)
102#define QSERDES_COM_RESTRIM_CODE_STATUS COM_OFF(0x12C)
103#define QSERDES_COM_PLLCAL_CODE1_STATUS COM_OFF(0x130)
104#define QSERDES_COM_PLLCAL_CODE2_STATUS COM_OFF(0x134)
105#define QSERDES_COM_CLK_SELECT COM_OFF(0x138)
106#define QSERDES_COM_HSCLK_SEL COM_OFF(0x13C)
107#define QSERDES_COM_INTEGLOOP_BINCODE_STATUS COM_OFF(0x140)
108#define QSERDES_COM_PLL_ANALOG COM_OFF(0x144)
109#define QSERDES_COM_CORECLK_DIV_MODE0 COM_OFF(0x148)
110#define QSERDES_COM_CORECLK_DIV_MODE1 COM_OFF(0x14C)
111#define QSERDES_COM_SW_RESET COM_OFF(0x150)
112#define QSERDES_COM_CORE_CLK_EN COM_OFF(0x154)
113#define QSERDES_COM_C_READY_STATUS COM_OFF(0x158)
114#define QSERDES_COM_CMN_CONFIG COM_OFF(0x15C)
115#define QSERDES_COM_CMN_RATE_OVERRIDE COM_OFF(0x160)
116#define QSERDES_COM_SVS_MODE_CLK_SEL COM_OFF(0x164)
117#define QSERDES_COM_DEBUG_BUS0 COM_OFF(0x168)
118#define QSERDES_COM_DEBUG_BUS1 COM_OFF(0x16C)
119#define QSERDES_COM_DEBUG_BUS2 COM_OFF(0x170)
120#define QSERDES_COM_DEBUG_BUS3 COM_OFF(0x174)
121#define QSERDES_COM_DEBUG_BUS_SEL COM_OFF(0x178)
122#define QSERDES_COM_CMN_MISC1 COM_OFF(0x17C)
123#define QSERDES_COM_CMN_MISC2 COM_OFF(0x180)
124#define QSERDES_COM_CMN_MODE COM_OFF(0x184)
125#define QSERDES_COM_CMN_VREG_SEL COM_OFF(0x188)
126
127/* UFS PHY registers */
128#define UFS_PHY_PHY_START PHY_OFF(0x00)
129#define UFS_PHY_POWER_DOWN_CONTROL PHY_OFF(0x04)
130#define UFS_PHY_TIMER_20US_CORECLK_STEPS_MSB PHY_OFF(0x08)
131#define UFS_PHY_TIMER_20US_CORECLK_STEPS_LSB PHY_OFF(0x0C)
132#define UFS_PHY_TX_LARGE_AMP_DRV_LVL PHY_OFF(0x2C)
133#define UFS_PHY_TX_SMALL_AMP_DRV_LVL PHY_OFF(0x34)
134#define UFS_PHY_LINECFG_DISABLE PHY_OFF(0x130)
135#define UFS_PHY_RX_SYM_RESYNC_CTRL PHY_OFF(0x134)
136#define UFS_PHY_RX_SIGDET_CTRL2 PHY_OFF(0x140)
137#define UFS_PHY_RX_PWM_GEAR_BAND PHY_OFF(0x14C)
138#define UFS_PHY_PCS_READY_STATUS PHY_OFF(0x160)
139
140/* UFS PHY TX registers */
141#define QSERDES_TX0_TRANSCEIVER_BIAS_EN TX_OFF(0, 0x5C)
142#define QSERDES_TX0_LANE_MODE_1 TX_OFF(0, 0x8C)
143#define QSERDES_TX0_LANE_MODE_2 TX_OFF(0, 0x90)
144#define QSERDES_TX0_LANE_MODE_3 TX_OFF(0, 0x94)
145
146/* UFS PHY RX registers */
147#define QSERDES_RX0_UCDR_SVS_SO_GAIN_HALF RX_OFF(0, 0x24)
148#define QSERDES_RX0_UCDR_SVS_SO_GAIN_QUARTER RX_OFF(0, 0x28)
149#define QSERDES_RX0_UCDR_SVS_SO_GAIN RX_OFF(0, 0x2C)
150#define QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN RX_OFF(0, 0x30)
151#define QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE RX_OFF(0, 0x34)
152#define QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW RX_OFF(0, 0x3C)
153#define QSERDES_RX0_UCDR_PI_CONTROLS RX_OFF(0, 0x44)
154#define QSERDES_RX0_RX_TERM_BW RX_OFF(0, 0x7C)
155#define QSERDES_RX0_RX_EQ_GAIN2_LSB RX_OFF(0, 0xC8)
156#define QSERDES_RX0_RX_EQ_GAIN2_MSB RX_OFF(0, 0xCC)
157#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL1 RX_OFF(0, 0xD0)
158#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2 RX_OFF(0, 0xD4)
159#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3 RX_OFF(0, 0xD8)
160#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4 RX_OFF(0, 0xDC)
161#define QSERDES_RX0_SIGDET_CNTRL RX_OFF(0, 0x104)
162#define QSERDES_RX0_SIGDET_LVL RX_OFF(0, 0x108)
163#define QSERDES_RX0_SIGDET_DEGLITCH_CNTRL RX_OFF(0, 0x10C)
164#define QSERDES_RX0_RX_INTERFACE_MODE RX_OFF(0, 0x11C)
165
166#define UFS_PHY_RX_LINECFG_DISABLE_BIT BIT(1)
167
168/*
169 * This structure represents the v3 specific phy.
170 * common_cfg MUST remain the first field in this structure
171 * in case extra fields are added. This way, when calling
172 * get_ufs_qcom_phy() of generic phy, we can extract the
173 * common phy structure (struct ufs_qcom_phy) out of it
174 * regardless of the relevant specific phy.
175 */
176struct ufs_qcom_phy_qmp_v3 {
177 struct ufs_qcom_phy common_cfg;
178};
179
180static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = {
181 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),
182 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_CONFIG, 0x06),
183 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0xD5),
184 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CLK_SELECT, 0x30),
185 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYS_CLK_CTRL, 0x02),
186 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
187 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BG_TIMER, 0x0A),
188 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_SEL, 0x00),
189 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_EN, 0x01),
190 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
191 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORE_CLK_EN, 0x00),
192 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x04),
193 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
194 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IVCO, 0x0F),
195 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_INITVAL1, 0xFF),
196 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
197 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE0, 0x82),
198 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE0, 0x08),
199 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
200 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE0, 0x34),
201 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x3F),
202 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
203 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE0, 0xCB),
204 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE0, 0x01),
205 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE0, 0xFF),
206 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE0, 0x0C),
207 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE1, 0x98),
208 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE1, 0x08),
209 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
210 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE1, 0x34),
211 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x3F),
212 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
213 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE1, 0xB2),
214 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
215 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
216 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE1, 0x0F),
217 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_LANE_MODE_1, 0x06),
218 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_LVL, 0x24),
219 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_CNTRL, 0x0F),
220 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x1E),
221 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_INTERFACE_MODE, 0x40),
222 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN, 0x0B),
223 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_TERM_BW, 0x5B),
224 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x06),
225 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
226 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1D),
227 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SVS_SO_GAIN_HALF, 0x04),
228 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
229 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SVS_SO_GAIN, 0x04),
230 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x4B),
231 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_PI_CONTROLS, 0xF1),
232 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW, 0x80),
233 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x6C),
234 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x0A),
235 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x02),
236 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SYM_RESYNC_CTRL, 0x03),
237};
238
239static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = {
240 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x44),
241};
242
243static struct ufs_qcom_phy_calibration phy_cal_table_svs2_enable[] = {
244 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV_MODE0, 0x14),
245 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV_MODE1, 0x14),
246 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SVS_MODE_CLK_SEL, 0x0a),
247 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x7e),
248 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
249 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE0, 0x7f),
250 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE0, 0x06),
251 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x7e),
252 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
253 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE1, 0x99),
254 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE1, 0x07),
255 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_MSB, 0x0b),
256 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_LSB, 0x66),
257};
258
259static struct ufs_qcom_phy_calibration phy_cal_table_svs2_disable[] = {
260 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV_MODE0, 0x0a),
261 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
262 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
263 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
264 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
265 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
266 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
267 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
268 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
269 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
270 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
271 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
272 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_LSB, 0xcc),
273};
274
275#endif