Alan Cox | 89c7813 | 2011-11-03 18:22:15 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright © 2006-2011 Intel Corporation |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify it |
| 5 | * under the terms and conditions of the GNU General Public License, |
| 6 | * version 2, as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 11 | * more details. |
| 12 | * |
| 13 | * You should have received a copy of the GNU General Public License along with |
| 14 | * this program; if not, write to the Free Software Foundation, Inc., |
| 15 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 16 | * |
| 17 | * Authors: |
| 18 | * Eric Anholt <eric@anholt.net> |
| 19 | */ |
| 20 | |
| 21 | #include <linux/i2c.h> |
| 22 | #include <linux/pm_runtime.h> |
| 23 | |
| 24 | #include <drm/drmP.h> |
| 25 | #include "framebuffer.h" |
| 26 | #include "psb_drv.h" |
| 27 | #include "psb_intel_drv.h" |
| 28 | #include "psb_intel_reg.h" |
| 29 | #include "psb_intel_display.h" |
| 30 | #include "power.h" |
| 31 | |
| 32 | struct psb_intel_clock_t { |
| 33 | /* given values */ |
| 34 | int n; |
| 35 | int m1, m2; |
| 36 | int p1, p2; |
| 37 | /* derived values */ |
| 38 | int dot; |
| 39 | int vco; |
| 40 | int m; |
| 41 | int p; |
| 42 | }; |
| 43 | |
| 44 | struct psb_intel_range_t { |
| 45 | int min, max; |
| 46 | }; |
| 47 | |
| 48 | struct psb_intel_p2_t { |
| 49 | int dot_limit; |
| 50 | int p2_slow, p2_fast; |
| 51 | }; |
| 52 | |
| 53 | #define INTEL_P2_NUM 2 |
| 54 | |
| 55 | struct psb_intel_limit_t { |
| 56 | struct psb_intel_range_t dot, vco, n, m, m1, m2, p, p1; |
| 57 | struct psb_intel_p2_t p2; |
| 58 | }; |
| 59 | |
| 60 | #define I8XX_DOT_MIN 25000 |
| 61 | #define I8XX_DOT_MAX 350000 |
| 62 | #define I8XX_VCO_MIN 930000 |
| 63 | #define I8XX_VCO_MAX 1400000 |
| 64 | #define I8XX_N_MIN 3 |
| 65 | #define I8XX_N_MAX 16 |
| 66 | #define I8XX_M_MIN 96 |
| 67 | #define I8XX_M_MAX 140 |
| 68 | #define I8XX_M1_MIN 18 |
| 69 | #define I8XX_M1_MAX 26 |
| 70 | #define I8XX_M2_MIN 6 |
| 71 | #define I8XX_M2_MAX 16 |
| 72 | #define I8XX_P_MIN 4 |
| 73 | #define I8XX_P_MAX 128 |
| 74 | #define I8XX_P1_MIN 2 |
| 75 | #define I8XX_P1_MAX 33 |
| 76 | #define I8XX_P1_LVDS_MIN 1 |
| 77 | #define I8XX_P1_LVDS_MAX 6 |
| 78 | #define I8XX_P2_SLOW 4 |
| 79 | #define I8XX_P2_FAST 2 |
| 80 | #define I8XX_P2_LVDS_SLOW 14 |
| 81 | #define I8XX_P2_LVDS_FAST 14 /* No fast option */ |
| 82 | #define I8XX_P2_SLOW_LIMIT 165000 |
| 83 | |
| 84 | #define I9XX_DOT_MIN 20000 |
| 85 | #define I9XX_DOT_MAX 400000 |
| 86 | #define I9XX_VCO_MIN 1400000 |
| 87 | #define I9XX_VCO_MAX 2800000 |
| 88 | #define I9XX_N_MIN 3 |
| 89 | #define I9XX_N_MAX 8 |
| 90 | #define I9XX_M_MIN 70 |
| 91 | #define I9XX_M_MAX 120 |
| 92 | #define I9XX_M1_MIN 10 |
| 93 | #define I9XX_M1_MAX 20 |
| 94 | #define I9XX_M2_MIN 5 |
| 95 | #define I9XX_M2_MAX 9 |
| 96 | #define I9XX_P_SDVO_DAC_MIN 5 |
| 97 | #define I9XX_P_SDVO_DAC_MAX 80 |
| 98 | #define I9XX_P_LVDS_MIN 7 |
| 99 | #define I9XX_P_LVDS_MAX 98 |
| 100 | #define I9XX_P1_MIN 1 |
| 101 | #define I9XX_P1_MAX 8 |
| 102 | #define I9XX_P2_SDVO_DAC_SLOW 10 |
| 103 | #define I9XX_P2_SDVO_DAC_FAST 5 |
| 104 | #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000 |
| 105 | #define I9XX_P2_LVDS_SLOW 14 |
| 106 | #define I9XX_P2_LVDS_FAST 7 |
| 107 | #define I9XX_P2_LVDS_SLOW_LIMIT 112000 |
| 108 | |
| 109 | #define INTEL_LIMIT_I8XX_DVO_DAC 0 |
| 110 | #define INTEL_LIMIT_I8XX_LVDS 1 |
| 111 | #define INTEL_LIMIT_I9XX_SDVO_DAC 2 |
| 112 | #define INTEL_LIMIT_I9XX_LVDS 3 |
| 113 | |
| 114 | static const struct psb_intel_limit_t psb_intel_limits[] = { |
| 115 | { /* INTEL_LIMIT_I8XX_DVO_DAC */ |
| 116 | .dot = {.min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX}, |
| 117 | .vco = {.min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX}, |
| 118 | .n = {.min = I8XX_N_MIN, .max = I8XX_N_MAX}, |
| 119 | .m = {.min = I8XX_M_MIN, .max = I8XX_M_MAX}, |
| 120 | .m1 = {.min = I8XX_M1_MIN, .max = I8XX_M1_MAX}, |
| 121 | .m2 = {.min = I8XX_M2_MIN, .max = I8XX_M2_MAX}, |
| 122 | .p = {.min = I8XX_P_MIN, .max = I8XX_P_MAX}, |
| 123 | .p1 = {.min = I8XX_P1_MIN, .max = I8XX_P1_MAX}, |
| 124 | .p2 = {.dot_limit = I8XX_P2_SLOW_LIMIT, |
| 125 | .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST}, |
| 126 | }, |
| 127 | { /* INTEL_LIMIT_I8XX_LVDS */ |
| 128 | .dot = {.min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX}, |
| 129 | .vco = {.min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX}, |
| 130 | .n = {.min = I8XX_N_MIN, .max = I8XX_N_MAX}, |
| 131 | .m = {.min = I8XX_M_MIN, .max = I8XX_M_MAX}, |
| 132 | .m1 = {.min = I8XX_M1_MIN, .max = I8XX_M1_MAX}, |
| 133 | .m2 = {.min = I8XX_M2_MIN, .max = I8XX_M2_MAX}, |
| 134 | .p = {.min = I8XX_P_MIN, .max = I8XX_P_MAX}, |
| 135 | .p1 = {.min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX}, |
| 136 | .p2 = {.dot_limit = I8XX_P2_SLOW_LIMIT, |
| 137 | .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST}, |
| 138 | }, |
| 139 | { /* INTEL_LIMIT_I9XX_SDVO_DAC */ |
| 140 | .dot = {.min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX}, |
| 141 | .vco = {.min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX}, |
| 142 | .n = {.min = I9XX_N_MIN, .max = I9XX_N_MAX}, |
| 143 | .m = {.min = I9XX_M_MIN, .max = I9XX_M_MAX}, |
| 144 | .m1 = {.min = I9XX_M1_MIN, .max = I9XX_M1_MAX}, |
| 145 | .m2 = {.min = I9XX_M2_MIN, .max = I9XX_M2_MAX}, |
| 146 | .p = {.min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX}, |
| 147 | .p1 = {.min = I9XX_P1_MIN, .max = I9XX_P1_MAX}, |
| 148 | .p2 = {.dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, |
| 149 | .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = |
| 150 | I9XX_P2_SDVO_DAC_FAST}, |
| 151 | }, |
| 152 | { /* INTEL_LIMIT_I9XX_LVDS */ |
| 153 | .dot = {.min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX}, |
| 154 | .vco = {.min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX}, |
| 155 | .n = {.min = I9XX_N_MIN, .max = I9XX_N_MAX}, |
| 156 | .m = {.min = I9XX_M_MIN, .max = I9XX_M_MAX}, |
| 157 | .m1 = {.min = I9XX_M1_MIN, .max = I9XX_M1_MAX}, |
| 158 | .m2 = {.min = I9XX_M2_MIN, .max = I9XX_M2_MAX}, |
| 159 | .p = {.min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX}, |
| 160 | .p1 = {.min = I9XX_P1_MIN, .max = I9XX_P1_MAX}, |
| 161 | /* The single-channel range is 25-112Mhz, and dual-channel |
| 162 | * is 80-224Mhz. Prefer single channel as much as possible. |
| 163 | */ |
| 164 | .p2 = {.dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, |
| 165 | .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST}, |
| 166 | }, |
| 167 | }; |
| 168 | |
| 169 | static const struct psb_intel_limit_t *psb_intel_limit(struct drm_crtc *crtc) |
| 170 | { |
| 171 | const struct psb_intel_limit_t *limit; |
| 172 | |
| 173 | if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
| 174 | limit = &psb_intel_limits[INTEL_LIMIT_I9XX_LVDS]; |
| 175 | else |
| 176 | limit = &psb_intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC]; |
| 177 | return limit; |
| 178 | } |
| 179 | |
| 180 | /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */ |
| 181 | |
| 182 | static void i8xx_clock(int refclk, struct psb_intel_clock_t *clock) |
| 183 | { |
| 184 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); |
| 185 | clock->p = clock->p1 * clock->p2; |
| 186 | clock->vco = refclk * clock->m / (clock->n + 2); |
| 187 | clock->dot = clock->vco / clock->p; |
| 188 | } |
| 189 | |
| 190 | /** Derive the pixel clock for the given refclk and divisors for 9xx chips. */ |
| 191 | |
| 192 | static void i9xx_clock(int refclk, struct psb_intel_clock_t *clock) |
| 193 | { |
| 194 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); |
| 195 | clock->p = clock->p1 * clock->p2; |
| 196 | clock->vco = refclk * clock->m / (clock->n + 2); |
| 197 | clock->dot = clock->vco / clock->p; |
| 198 | } |
| 199 | |
| 200 | static void psb_intel_clock(struct drm_device *dev, int refclk, |
| 201 | struct psb_intel_clock_t *clock) |
| 202 | { |
| 203 | return i9xx_clock(refclk, clock); |
| 204 | } |
| 205 | |
| 206 | /** |
| 207 | * Returns whether any output on the specified pipe is of the specified type |
| 208 | */ |
| 209 | bool psb_intel_pipe_has_type(struct drm_crtc *crtc, int type) |
| 210 | { |
| 211 | struct drm_device *dev = crtc->dev; |
| 212 | struct drm_mode_config *mode_config = &dev->mode_config; |
| 213 | struct drm_connector *l_entry; |
| 214 | |
| 215 | list_for_each_entry(l_entry, &mode_config->connector_list, head) { |
| 216 | if (l_entry->encoder && l_entry->encoder->crtc == crtc) { |
| 217 | struct psb_intel_output *psb_intel_output = |
| 218 | to_psb_intel_output(l_entry); |
| 219 | if (psb_intel_output->type == type) |
| 220 | return true; |
| 221 | } |
| 222 | } |
| 223 | return false; |
| 224 | } |
| 225 | |
| 226 | #define INTELPllInvalid(s) { /* ErrorF (s) */; return false; } |
| 227 | /** |
| 228 | * Returns whether the given set of divisors are valid for a given refclk with |
| 229 | * the given connectors. |
| 230 | */ |
| 231 | |
| 232 | static bool psb_intel_PLL_is_valid(struct drm_crtc *crtc, |
| 233 | struct psb_intel_clock_t *clock) |
| 234 | { |
| 235 | const struct psb_intel_limit_t *limit = psb_intel_limit(crtc); |
| 236 | |
| 237 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
| 238 | INTELPllInvalid("p1 out of range\n"); |
| 239 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
| 240 | INTELPllInvalid("p out of range\n"); |
| 241 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
| 242 | INTELPllInvalid("m2 out of range\n"); |
| 243 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
| 244 | INTELPllInvalid("m1 out of range\n"); |
| 245 | if (clock->m1 <= clock->m2) |
| 246 | INTELPllInvalid("m1 <= m2\n"); |
| 247 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
| 248 | INTELPllInvalid("m out of range\n"); |
| 249 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
| 250 | INTELPllInvalid("n out of range\n"); |
| 251 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
| 252 | INTELPllInvalid("vco out of range\n"); |
| 253 | /* XXX: We may need to be checking "Dot clock" |
| 254 | * depending on the multiplier, connector, etc., |
| 255 | * rather than just a single range. |
| 256 | */ |
| 257 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) |
| 258 | INTELPllInvalid("dot out of range\n"); |
| 259 | |
| 260 | return true; |
| 261 | } |
| 262 | |
| 263 | /** |
| 264 | * Returns a set of divisors for the desired target clock with the given |
| 265 | * refclk, or FALSE. The returned values represent the clock equation: |
| 266 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
| 267 | */ |
| 268 | static bool psb_intel_find_best_PLL(struct drm_crtc *crtc, int target, |
| 269 | int refclk, |
| 270 | struct psb_intel_clock_t *best_clock) |
| 271 | { |
| 272 | struct drm_device *dev = crtc->dev; |
| 273 | struct psb_intel_clock_t clock; |
| 274 | const struct psb_intel_limit_t *limit = psb_intel_limit(crtc); |
| 275 | int err = target; |
| 276 | |
| 277 | if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
| 278 | (REG_READ(LVDS) & LVDS_PORT_EN) != 0) { |
| 279 | /* |
| 280 | * For LVDS, if the panel is on, just rely on its current |
| 281 | * settings for dual-channel. We haven't figured out how to |
| 282 | * reliably set up different single/dual channel state, if we |
| 283 | * even can. |
| 284 | */ |
| 285 | if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) == |
| 286 | LVDS_CLKB_POWER_UP) |
| 287 | clock.p2 = limit->p2.p2_fast; |
| 288 | else |
| 289 | clock.p2 = limit->p2.p2_slow; |
| 290 | } else { |
| 291 | if (target < limit->p2.dot_limit) |
| 292 | clock.p2 = limit->p2.p2_slow; |
| 293 | else |
| 294 | clock.p2 = limit->p2.p2_fast; |
| 295 | } |
| 296 | |
| 297 | memset(best_clock, 0, sizeof(*best_clock)); |
| 298 | |
| 299 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
| 300 | clock.m1++) { |
| 301 | for (clock.m2 = limit->m2.min; |
| 302 | clock.m2 < clock.m1 && clock.m2 <= limit->m2.max; |
| 303 | clock.m2++) { |
| 304 | for (clock.n = limit->n.min; |
| 305 | clock.n <= limit->n.max; clock.n++) { |
| 306 | for (clock.p1 = limit->p1.min; |
| 307 | clock.p1 <= limit->p1.max; |
| 308 | clock.p1++) { |
| 309 | int this_err; |
| 310 | |
| 311 | psb_intel_clock(dev, refclk, &clock); |
| 312 | |
| 313 | if (!psb_intel_PLL_is_valid |
| 314 | (crtc, &clock)) |
| 315 | continue; |
| 316 | |
| 317 | this_err = abs(clock.dot - target); |
| 318 | if (this_err < err) { |
| 319 | *best_clock = clock; |
| 320 | err = this_err; |
| 321 | } |
| 322 | } |
| 323 | } |
| 324 | } |
| 325 | } |
| 326 | |
| 327 | return err != target; |
| 328 | } |
| 329 | |
| 330 | void psb_intel_wait_for_vblank(struct drm_device *dev) |
| 331 | { |
| 332 | /* Wait for 20ms, i.e. one cycle at 50hz. */ |
| 333 | mdelay(20); |
| 334 | } |
| 335 | |
| 336 | int psb_intel_pipe_set_base(struct drm_crtc *crtc, |
| 337 | int x, int y, struct drm_framebuffer *old_fb) |
| 338 | { |
| 339 | struct drm_device *dev = crtc->dev; |
| 340 | /* struct drm_i915_master_private *master_priv; */ |
| 341 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); |
| 342 | struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb); |
| 343 | int pipe = psb_intel_crtc->pipe; |
| 344 | unsigned long start, offset; |
| 345 | int dspbase = (pipe == 0 ? DSPABASE : DSPBBASE); |
| 346 | int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF); |
| 347 | int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE; |
| 348 | int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; |
| 349 | u32 dspcntr; |
| 350 | int ret = 0; |
| 351 | |
| 352 | if (!gma_power_begin(dev, true)) |
| 353 | return 0; |
| 354 | |
| 355 | /* no fb bound */ |
| 356 | if (!crtc->fb) { |
| 357 | dev_dbg(dev->dev, "No FB bound\n"); |
| 358 | goto psb_intel_pipe_cleaner; |
| 359 | } |
| 360 | |
| 361 | /* We are displaying this buffer, make sure it is actually loaded |
| 362 | into the GTT */ |
| 363 | ret = psb_gtt_pin(psbfb->gtt); |
| 364 | if (ret < 0) |
| 365 | goto psb_intel_pipe_set_base_exit; |
| 366 | start = psbfb->gtt->offset; |
| 367 | |
| 368 | offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8); |
| 369 | |
| 370 | REG_WRITE(dspstride, crtc->fb->pitch); |
| 371 | |
| 372 | dspcntr = REG_READ(dspcntr_reg); |
| 373 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; |
| 374 | |
| 375 | switch (crtc->fb->bits_per_pixel) { |
| 376 | case 8: |
| 377 | dspcntr |= DISPPLANE_8BPP; |
| 378 | break; |
| 379 | case 16: |
| 380 | if (crtc->fb->depth == 15) |
| 381 | dspcntr |= DISPPLANE_15_16BPP; |
| 382 | else |
| 383 | dspcntr |= DISPPLANE_16BPP; |
| 384 | break; |
| 385 | case 24: |
| 386 | case 32: |
| 387 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; |
| 388 | break; |
| 389 | default: |
| 390 | dev_err(dev->dev, "Unknown color depth\n"); |
| 391 | ret = -EINVAL; |
| 392 | psb_gtt_unpin(psbfb->gtt); |
| 393 | goto psb_intel_pipe_set_base_exit; |
| 394 | } |
| 395 | REG_WRITE(dspcntr_reg, dspcntr); |
| 396 | |
| 397 | |
| 398 | if (0 /* FIXMEAC - check what PSB needs */) { |
| 399 | REG_WRITE(dspbase, offset); |
| 400 | REG_READ(dspbase); |
| 401 | REG_WRITE(dspsurf, start); |
| 402 | REG_READ(dspsurf); |
| 403 | } else { |
| 404 | REG_WRITE(dspbase, start + offset); |
| 405 | REG_READ(dspbase); |
| 406 | } |
| 407 | |
| 408 | psb_intel_pipe_cleaner: |
| 409 | /* If there was a previous display we can now unpin it */ |
| 410 | if (old_fb) |
| 411 | psb_gtt_unpin(to_psb_fb(old_fb)->gtt); |
| 412 | |
| 413 | psb_intel_pipe_set_base_exit: |
| 414 | gma_power_end(dev); |
| 415 | return ret; |
| 416 | } |
| 417 | |
| 418 | /** |
| 419 | * Sets the power management mode of the pipe and plane. |
| 420 | * |
| 421 | * This code should probably grow support for turning the cursor off and back |
| 422 | * on appropriately at the same time as we're turning the pipe off/on. |
| 423 | */ |
| 424 | static void psb_intel_crtc_dpms(struct drm_crtc *crtc, int mode) |
| 425 | { |
| 426 | struct drm_device *dev = crtc->dev; |
| 427 | /* struct drm_i915_master_private *master_priv; */ |
| 428 | /* struct drm_i915_private *dev_priv = dev->dev_private; */ |
| 429 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); |
| 430 | int pipe = psb_intel_crtc->pipe; |
| 431 | int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; |
| 432 | int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; |
| 433 | int dspbase_reg = (pipe == 0) ? DSPABASE : DSPBBASE; |
| 434 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; |
| 435 | u32 temp; |
| 436 | bool enabled; |
| 437 | |
| 438 | /* XXX: When our outputs are all unaware of DPMS modes other than off |
| 439 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. |
| 440 | */ |
| 441 | switch (mode) { |
| 442 | case DRM_MODE_DPMS_ON: |
| 443 | case DRM_MODE_DPMS_STANDBY: |
| 444 | case DRM_MODE_DPMS_SUSPEND: |
| 445 | /* Enable the DPLL */ |
| 446 | temp = REG_READ(dpll_reg); |
| 447 | if ((temp & DPLL_VCO_ENABLE) == 0) { |
| 448 | REG_WRITE(dpll_reg, temp); |
| 449 | REG_READ(dpll_reg); |
| 450 | /* Wait for the clocks to stabilize. */ |
| 451 | udelay(150); |
| 452 | REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); |
| 453 | REG_READ(dpll_reg); |
| 454 | /* Wait for the clocks to stabilize. */ |
| 455 | udelay(150); |
| 456 | REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); |
| 457 | REG_READ(dpll_reg); |
| 458 | /* Wait for the clocks to stabilize. */ |
| 459 | udelay(150); |
| 460 | } |
| 461 | |
| 462 | /* Enable the pipe */ |
| 463 | temp = REG_READ(pipeconf_reg); |
| 464 | if ((temp & PIPEACONF_ENABLE) == 0) |
| 465 | REG_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE); |
| 466 | |
| 467 | /* Enable the plane */ |
| 468 | temp = REG_READ(dspcntr_reg); |
| 469 | if ((temp & DISPLAY_PLANE_ENABLE) == 0) { |
| 470 | REG_WRITE(dspcntr_reg, |
| 471 | temp | DISPLAY_PLANE_ENABLE); |
| 472 | /* Flush the plane changes */ |
| 473 | REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); |
| 474 | } |
| 475 | |
| 476 | psb_intel_crtc_load_lut(crtc); |
| 477 | |
| 478 | /* Give the overlay scaler a chance to enable |
| 479 | * if it's on this pipe */ |
| 480 | /* psb_intel_crtc_dpms_video(crtc, true); TODO */ |
| 481 | break; |
| 482 | case DRM_MODE_DPMS_OFF: |
| 483 | /* Give the overlay scaler a chance to disable |
| 484 | * if it's on this pipe */ |
| 485 | /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */ |
| 486 | |
| 487 | /* Disable the VGA plane that we never use */ |
| 488 | REG_WRITE(VGACNTRL, VGA_DISP_DISABLE); |
| 489 | |
| 490 | /* Disable display plane */ |
| 491 | temp = REG_READ(dspcntr_reg); |
| 492 | if ((temp & DISPLAY_PLANE_ENABLE) != 0) { |
| 493 | REG_WRITE(dspcntr_reg, |
| 494 | temp & ~DISPLAY_PLANE_ENABLE); |
| 495 | /* Flush the plane changes */ |
| 496 | REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); |
| 497 | REG_READ(dspbase_reg); |
| 498 | } |
| 499 | |
| 500 | /* Next, disable display pipes */ |
| 501 | temp = REG_READ(pipeconf_reg); |
| 502 | if ((temp & PIPEACONF_ENABLE) != 0) { |
| 503 | REG_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE); |
| 504 | REG_READ(pipeconf_reg); |
| 505 | } |
| 506 | |
| 507 | /* Wait for vblank for the disable to take effect. */ |
| 508 | psb_intel_wait_for_vblank(dev); |
| 509 | |
| 510 | temp = REG_READ(dpll_reg); |
| 511 | if ((temp & DPLL_VCO_ENABLE) != 0) { |
| 512 | REG_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE); |
| 513 | REG_READ(dpll_reg); |
| 514 | } |
| 515 | |
| 516 | /* Wait for the clocks to turn off. */ |
| 517 | udelay(150); |
| 518 | break; |
| 519 | } |
| 520 | |
| 521 | enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF; |
| 522 | |
| 523 | /*Set FIFO Watermarks*/ |
| 524 | REG_WRITE(DSPARB, 0x3F3E); |
| 525 | } |
| 526 | |
| 527 | static void psb_intel_crtc_prepare(struct drm_crtc *crtc) |
| 528 | { |
| 529 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; |
| 530 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); |
| 531 | } |
| 532 | |
| 533 | static void psb_intel_crtc_commit(struct drm_crtc *crtc) |
| 534 | { |
| 535 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; |
| 536 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); |
| 537 | } |
| 538 | |
| 539 | void psb_intel_encoder_prepare(struct drm_encoder *encoder) |
| 540 | { |
| 541 | struct drm_encoder_helper_funcs *encoder_funcs = |
| 542 | encoder->helper_private; |
| 543 | /* lvds has its own version of prepare see psb_intel_lvds_prepare */ |
| 544 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); |
| 545 | } |
| 546 | |
| 547 | void psb_intel_encoder_commit(struct drm_encoder *encoder) |
| 548 | { |
| 549 | struct drm_encoder_helper_funcs *encoder_funcs = |
| 550 | encoder->helper_private; |
| 551 | /* lvds has its own version of commit see psb_intel_lvds_commit */ |
| 552 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); |
| 553 | } |
| 554 | |
| 555 | static bool psb_intel_crtc_mode_fixup(struct drm_crtc *crtc, |
| 556 | struct drm_display_mode *mode, |
| 557 | struct drm_display_mode *adjusted_mode) |
| 558 | { |
| 559 | return true; |
| 560 | } |
| 561 | |
| 562 | |
| 563 | /** |
| 564 | * Return the pipe currently connected to the panel fitter, |
| 565 | * or -1 if the panel fitter is not present or not in use |
| 566 | */ |
| 567 | static int psb_intel_panel_fitter_pipe(struct drm_device *dev) |
| 568 | { |
| 569 | u32 pfit_control; |
| 570 | |
| 571 | pfit_control = REG_READ(PFIT_CONTROL); |
| 572 | |
| 573 | /* See if the panel fitter is in use */ |
| 574 | if ((pfit_control & PFIT_ENABLE) == 0) |
| 575 | return -1; |
| 576 | /* Must be on PIPE 1 for PSB */ |
| 577 | return 1; |
| 578 | } |
| 579 | |
| 580 | static int psb_intel_crtc_mode_set(struct drm_crtc *crtc, |
| 581 | struct drm_display_mode *mode, |
| 582 | struct drm_display_mode *adjusted_mode, |
| 583 | int x, int y, |
| 584 | struct drm_framebuffer *old_fb) |
| 585 | { |
| 586 | struct drm_device *dev = crtc->dev; |
| 587 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); |
| 588 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; |
| 589 | int pipe = psb_intel_crtc->pipe; |
| 590 | int fp_reg = (pipe == 0) ? FPA0 : FPB0; |
| 591 | int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; |
| 592 | int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; |
| 593 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; |
| 594 | int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B; |
| 595 | int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B; |
| 596 | int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B; |
| 597 | int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B; |
| 598 | int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B; |
| 599 | int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B; |
| 600 | int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE; |
| 601 | int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS; |
| 602 | int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC; |
| 603 | int refclk; |
| 604 | struct psb_intel_clock_t clock; |
| 605 | u32 dpll = 0, fp = 0, dspcntr, pipeconf; |
| 606 | bool ok, is_sdvo = false, is_dvo = false; |
| 607 | bool is_crt = false, is_lvds = false, is_tv = false; |
| 608 | struct drm_mode_config *mode_config = &dev->mode_config; |
| 609 | struct drm_connector *connector; |
| 610 | |
| 611 | /* No scan out no play */ |
| 612 | if (crtc->fb == NULL) { |
| 613 | crtc_funcs->mode_set_base(crtc, x, y, old_fb); |
| 614 | return 0; |
| 615 | } |
| 616 | |
| 617 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
| 618 | struct psb_intel_output *psb_intel_output = |
| 619 | to_psb_intel_output(connector); |
| 620 | |
| 621 | if (!connector->encoder |
| 622 | || connector->encoder->crtc != crtc) |
| 623 | continue; |
| 624 | |
| 625 | switch (psb_intel_output->type) { |
| 626 | case INTEL_OUTPUT_LVDS: |
| 627 | is_lvds = true; |
| 628 | break; |
| 629 | case INTEL_OUTPUT_SDVO: |
| 630 | is_sdvo = true; |
| 631 | break; |
| 632 | case INTEL_OUTPUT_DVO: |
| 633 | is_dvo = true; |
| 634 | break; |
| 635 | case INTEL_OUTPUT_TVOUT: |
| 636 | is_tv = true; |
| 637 | break; |
| 638 | case INTEL_OUTPUT_ANALOG: |
| 639 | is_crt = true; |
| 640 | break; |
| 641 | } |
| 642 | } |
| 643 | |
| 644 | refclk = 96000; |
| 645 | |
| 646 | ok = psb_intel_find_best_PLL(crtc, adjusted_mode->clock, refclk, |
| 647 | &clock); |
| 648 | if (!ok) { |
| 649 | dev_err(dev->dev, "Couldn't find PLL settings for mode!\n"); |
| 650 | return 0; |
| 651 | } |
| 652 | |
| 653 | fp = clock.n << 16 | clock.m1 << 8 | clock.m2; |
| 654 | |
| 655 | dpll = DPLL_VGA_MODE_DIS; |
| 656 | if (is_lvds) { |
| 657 | dpll |= DPLLB_MODE_LVDS; |
| 658 | dpll |= DPLL_DVO_HIGH_SPEED; |
| 659 | } else |
| 660 | dpll |= DPLLB_MODE_DAC_SERIAL; |
| 661 | if (is_sdvo) { |
| 662 | int sdvo_pixel_multiply = |
| 663 | adjusted_mode->clock / mode->clock; |
| 664 | dpll |= DPLL_DVO_HIGH_SPEED; |
| 665 | dpll |= |
| 666 | (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; |
| 667 | } |
| 668 | |
| 669 | /* compute bitmask from p1 value */ |
| 670 | dpll |= (1 << (clock.p1 - 1)) << 16; |
| 671 | switch (clock.p2) { |
| 672 | case 5: |
| 673 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
| 674 | break; |
| 675 | case 7: |
| 676 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
| 677 | break; |
| 678 | case 10: |
| 679 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
| 680 | break; |
| 681 | case 14: |
| 682 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
| 683 | break; |
| 684 | } |
| 685 | |
| 686 | if (is_tv) { |
| 687 | /* XXX: just matching BIOS for now */ |
| 688 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
| 689 | dpll |= 3; |
| 690 | } |
| 691 | dpll |= PLL_REF_INPUT_DREFCLK; |
| 692 | |
| 693 | /* setup pipeconf */ |
| 694 | pipeconf = REG_READ(pipeconf_reg); |
| 695 | |
| 696 | /* Set up the display plane register */ |
| 697 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
| 698 | |
| 699 | if (pipe == 0) |
| 700 | dspcntr |= DISPPLANE_SEL_PIPE_A; |
| 701 | else |
| 702 | dspcntr |= DISPPLANE_SEL_PIPE_B; |
| 703 | |
| 704 | dspcntr |= DISPLAY_PLANE_ENABLE; |
| 705 | pipeconf |= PIPEACONF_ENABLE; |
| 706 | dpll |= DPLL_VCO_ENABLE; |
| 707 | |
| 708 | |
| 709 | /* Disable the panel fitter if it was on our pipe */ |
| 710 | if (psb_intel_panel_fitter_pipe(dev) == pipe) |
| 711 | REG_WRITE(PFIT_CONTROL, 0); |
| 712 | |
| 713 | drm_mode_debug_printmodeline(mode); |
| 714 | |
| 715 | if (dpll & DPLL_VCO_ENABLE) { |
| 716 | REG_WRITE(fp_reg, fp); |
| 717 | REG_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE); |
| 718 | REG_READ(dpll_reg); |
| 719 | udelay(150); |
| 720 | } |
| 721 | |
| 722 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
| 723 | * This is an exception to the general rule that mode_set doesn't turn |
| 724 | * things on. |
| 725 | */ |
| 726 | if (is_lvds) { |
| 727 | u32 lvds = REG_READ(LVDS); |
| 728 | |
| 729 | lvds &= ~LVDS_PIPEB_SELECT; |
| 730 | if (pipe == 1) |
| 731 | lvds |= LVDS_PIPEB_SELECT; |
| 732 | |
| 733 | lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; |
| 734 | /* Set the B0-B3 data pairs corresponding to |
| 735 | * whether we're going to |
| 736 | * set the DPLLs for dual-channel mode or not. |
| 737 | */ |
| 738 | lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); |
| 739 | if (clock.p2 == 7) |
| 740 | lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; |
| 741 | |
| 742 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) |
| 743 | * appropriately here, but we need to look more |
| 744 | * thoroughly into how panels behave in the two modes. |
| 745 | */ |
| 746 | |
| 747 | REG_WRITE(LVDS, lvds); |
| 748 | REG_READ(LVDS); |
| 749 | } |
| 750 | |
| 751 | REG_WRITE(fp_reg, fp); |
| 752 | REG_WRITE(dpll_reg, dpll); |
| 753 | REG_READ(dpll_reg); |
| 754 | /* Wait for the clocks to stabilize. */ |
| 755 | udelay(150); |
| 756 | |
| 757 | /* write it again -- the BIOS does, after all */ |
| 758 | REG_WRITE(dpll_reg, dpll); |
| 759 | |
| 760 | REG_READ(dpll_reg); |
| 761 | /* Wait for the clocks to stabilize. */ |
| 762 | udelay(150); |
| 763 | |
| 764 | REG_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) | |
| 765 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
| 766 | REG_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) | |
| 767 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
| 768 | REG_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) | |
| 769 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
| 770 | REG_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) | |
| 771 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
| 772 | REG_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) | |
| 773 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
| 774 | REG_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) | |
| 775 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
| 776 | /* pipesrc and dspsize control the size that is scaled from, |
| 777 | * which should always be the user's requested size. |
| 778 | */ |
| 779 | REG_WRITE(dspsize_reg, |
| 780 | ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1)); |
| 781 | REG_WRITE(dsppos_reg, 0); |
| 782 | REG_WRITE(pipesrc_reg, |
| 783 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); |
| 784 | REG_WRITE(pipeconf_reg, pipeconf); |
| 785 | REG_READ(pipeconf_reg); |
| 786 | |
| 787 | psb_intel_wait_for_vblank(dev); |
| 788 | |
| 789 | REG_WRITE(dspcntr_reg, dspcntr); |
| 790 | |
| 791 | /* Flush the plane changes */ |
| 792 | crtc_funcs->mode_set_base(crtc, x, y, old_fb); |
| 793 | |
| 794 | psb_intel_wait_for_vblank(dev); |
| 795 | |
| 796 | return 0; |
| 797 | } |
| 798 | |
| 799 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
| 800 | void psb_intel_crtc_load_lut(struct drm_crtc *crtc) |
| 801 | { |
| 802 | struct drm_device *dev = crtc->dev; |
| 803 | struct drm_psb_private *dev_priv = |
| 804 | (struct drm_psb_private *)dev->dev_private; |
| 805 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); |
| 806 | int palreg = PALETTE_A; |
| 807 | int i; |
| 808 | |
| 809 | /* The clocks have to be on to load the palette. */ |
| 810 | if (!crtc->enabled) |
| 811 | return; |
| 812 | |
| 813 | switch (psb_intel_crtc->pipe) { |
| 814 | case 0: |
| 815 | break; |
| 816 | case 1: |
| 817 | palreg = PALETTE_B; |
| 818 | break; |
| 819 | case 2: |
| 820 | palreg = PALETTE_C; |
| 821 | break; |
| 822 | default: |
| 823 | dev_err(dev->dev, "Illegal Pipe Number.\n"); |
| 824 | return; |
| 825 | } |
| 826 | |
| 827 | if (gma_power_begin(dev, false)) { |
| 828 | for (i = 0; i < 256; i++) { |
| 829 | REG_WRITE(palreg + 4 * i, |
| 830 | ((psb_intel_crtc->lut_r[i] + |
| 831 | psb_intel_crtc->lut_adj[i]) << 16) | |
| 832 | ((psb_intel_crtc->lut_g[i] + |
| 833 | psb_intel_crtc->lut_adj[i]) << 8) | |
| 834 | (psb_intel_crtc->lut_b[i] + |
| 835 | psb_intel_crtc->lut_adj[i])); |
| 836 | } |
| 837 | gma_power_end(dev); |
| 838 | } else { |
| 839 | for (i = 0; i < 256; i++) { |
| 840 | dev_priv->save_palette_a[i] = |
| 841 | ((psb_intel_crtc->lut_r[i] + |
| 842 | psb_intel_crtc->lut_adj[i]) << 16) | |
| 843 | ((psb_intel_crtc->lut_g[i] + |
| 844 | psb_intel_crtc->lut_adj[i]) << 8) | |
| 845 | (psb_intel_crtc->lut_b[i] + |
| 846 | psb_intel_crtc->lut_adj[i]); |
| 847 | } |
| 848 | |
| 849 | } |
| 850 | } |
| 851 | |
| 852 | /** |
| 853 | * Save HW states of giving crtc |
| 854 | */ |
| 855 | static void psb_intel_crtc_save(struct drm_crtc *crtc) |
| 856 | { |
| 857 | struct drm_device *dev = crtc->dev; |
| 858 | /* struct drm_psb_private *dev_priv = |
| 859 | (struct drm_psb_private *)dev->dev_private; */ |
| 860 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); |
| 861 | struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state; |
| 862 | int pipeA = (psb_intel_crtc->pipe == 0); |
| 863 | uint32_t paletteReg; |
| 864 | int i; |
| 865 | |
| 866 | if (!crtc_state) { |
| 867 | dev_err(dev->dev, "No CRTC state found\n"); |
| 868 | return; |
| 869 | } |
| 870 | |
| 871 | crtc_state->saveDSPCNTR = REG_READ(pipeA ? DSPACNTR : DSPBCNTR); |
| 872 | crtc_state->savePIPECONF = REG_READ(pipeA ? PIPEACONF : PIPEBCONF); |
| 873 | crtc_state->savePIPESRC = REG_READ(pipeA ? PIPEASRC : PIPEBSRC); |
| 874 | crtc_state->saveFP0 = REG_READ(pipeA ? FPA0 : FPB0); |
| 875 | crtc_state->saveFP1 = REG_READ(pipeA ? FPA1 : FPB1); |
| 876 | crtc_state->saveDPLL = REG_READ(pipeA ? DPLL_A : DPLL_B); |
| 877 | crtc_state->saveHTOTAL = REG_READ(pipeA ? HTOTAL_A : HTOTAL_B); |
| 878 | crtc_state->saveHBLANK = REG_READ(pipeA ? HBLANK_A : HBLANK_B); |
| 879 | crtc_state->saveHSYNC = REG_READ(pipeA ? HSYNC_A : HSYNC_B); |
| 880 | crtc_state->saveVTOTAL = REG_READ(pipeA ? VTOTAL_A : VTOTAL_B); |
| 881 | crtc_state->saveVBLANK = REG_READ(pipeA ? VBLANK_A : VBLANK_B); |
| 882 | crtc_state->saveVSYNC = REG_READ(pipeA ? VSYNC_A : VSYNC_B); |
| 883 | crtc_state->saveDSPSTRIDE = REG_READ(pipeA ? DSPASTRIDE : DSPBSTRIDE); |
| 884 | |
| 885 | /*NOTE: DSPSIZE DSPPOS only for psb*/ |
| 886 | crtc_state->saveDSPSIZE = REG_READ(pipeA ? DSPASIZE : DSPBSIZE); |
| 887 | crtc_state->saveDSPPOS = REG_READ(pipeA ? DSPAPOS : DSPBPOS); |
| 888 | |
| 889 | crtc_state->saveDSPBASE = REG_READ(pipeA ? DSPABASE : DSPBBASE); |
| 890 | |
| 891 | paletteReg = pipeA ? PALETTE_A : PALETTE_B; |
| 892 | for (i = 0; i < 256; ++i) |
| 893 | crtc_state->savePalette[i] = REG_READ(paletteReg + (i << 2)); |
| 894 | } |
| 895 | |
| 896 | /** |
| 897 | * Restore HW states of giving crtc |
| 898 | */ |
| 899 | static void psb_intel_crtc_restore(struct drm_crtc *crtc) |
| 900 | { |
| 901 | struct drm_device *dev = crtc->dev; |
| 902 | /* struct drm_psb_private * dev_priv = |
| 903 | (struct drm_psb_private *)dev->dev_private; */ |
| 904 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); |
| 905 | struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state; |
| 906 | /* struct drm_crtc_helper_funcs * crtc_funcs = crtc->helper_private; */ |
| 907 | int pipeA = (psb_intel_crtc->pipe == 0); |
| 908 | uint32_t paletteReg; |
| 909 | int i; |
| 910 | |
| 911 | if (!crtc_state) { |
| 912 | dev_err(dev->dev, "No crtc state\n"); |
| 913 | return; |
| 914 | } |
| 915 | |
| 916 | if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) { |
| 917 | REG_WRITE(pipeA ? DPLL_A : DPLL_B, |
| 918 | crtc_state->saveDPLL & ~DPLL_VCO_ENABLE); |
| 919 | REG_READ(pipeA ? DPLL_A : DPLL_B); |
| 920 | udelay(150); |
| 921 | } |
| 922 | |
| 923 | REG_WRITE(pipeA ? FPA0 : FPB0, crtc_state->saveFP0); |
| 924 | REG_READ(pipeA ? FPA0 : FPB0); |
| 925 | |
| 926 | REG_WRITE(pipeA ? FPA1 : FPB1, crtc_state->saveFP1); |
| 927 | REG_READ(pipeA ? FPA1 : FPB1); |
| 928 | |
| 929 | REG_WRITE(pipeA ? DPLL_A : DPLL_B, crtc_state->saveDPLL); |
| 930 | REG_READ(pipeA ? DPLL_A : DPLL_B); |
| 931 | udelay(150); |
| 932 | |
| 933 | REG_WRITE(pipeA ? HTOTAL_A : HTOTAL_B, crtc_state->saveHTOTAL); |
| 934 | REG_WRITE(pipeA ? HBLANK_A : HBLANK_B, crtc_state->saveHBLANK); |
| 935 | REG_WRITE(pipeA ? HSYNC_A : HSYNC_B, crtc_state->saveHSYNC); |
| 936 | REG_WRITE(pipeA ? VTOTAL_A : VTOTAL_B, crtc_state->saveVTOTAL); |
| 937 | REG_WRITE(pipeA ? VBLANK_A : VBLANK_B, crtc_state->saveVBLANK); |
| 938 | REG_WRITE(pipeA ? VSYNC_A : VSYNC_B, crtc_state->saveVSYNC); |
| 939 | REG_WRITE(pipeA ? DSPASTRIDE : DSPBSTRIDE, crtc_state->saveDSPSTRIDE); |
| 940 | |
| 941 | REG_WRITE(pipeA ? DSPASIZE : DSPBSIZE, crtc_state->saveDSPSIZE); |
| 942 | REG_WRITE(pipeA ? DSPAPOS : DSPBPOS, crtc_state->saveDSPPOS); |
| 943 | |
| 944 | REG_WRITE(pipeA ? PIPEASRC : PIPEBSRC, crtc_state->savePIPESRC); |
| 945 | REG_WRITE(pipeA ? DSPABASE : DSPBBASE, crtc_state->saveDSPBASE); |
| 946 | REG_WRITE(pipeA ? PIPEACONF : PIPEBCONF, crtc_state->savePIPECONF); |
| 947 | |
| 948 | psb_intel_wait_for_vblank(dev); |
| 949 | |
| 950 | REG_WRITE(pipeA ? DSPACNTR : DSPBCNTR, crtc_state->saveDSPCNTR); |
| 951 | REG_WRITE(pipeA ? DSPABASE : DSPBBASE, crtc_state->saveDSPBASE); |
| 952 | |
| 953 | psb_intel_wait_for_vblank(dev); |
| 954 | |
| 955 | paletteReg = pipeA ? PALETTE_A : PALETTE_B; |
| 956 | for (i = 0; i < 256; ++i) |
| 957 | REG_WRITE(paletteReg + (i << 2), crtc_state->savePalette[i]); |
| 958 | } |
| 959 | |
| 960 | static int psb_intel_crtc_cursor_set(struct drm_crtc *crtc, |
| 961 | struct drm_file *file_priv, |
| 962 | uint32_t handle, |
| 963 | uint32_t width, uint32_t height) |
| 964 | { |
| 965 | struct drm_device *dev = crtc->dev; |
| 966 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); |
| 967 | int pipe = psb_intel_crtc->pipe; |
| 968 | uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR; |
| 969 | uint32_t base = (pipe == 0) ? CURABASE : CURBBASE; |
| 970 | uint32_t temp; |
| 971 | size_t addr = 0; |
| 972 | struct gtt_range *gt; |
| 973 | struct drm_gem_object *obj; |
| 974 | int ret; |
| 975 | |
| 976 | /* if we want to turn of the cursor ignore width and height */ |
| 977 | if (!handle) { |
| 978 | /* turn off the cursor */ |
| 979 | temp = CURSOR_MODE_DISABLE; |
| 980 | |
| 981 | if (gma_power_begin(dev, false)) { |
| 982 | REG_WRITE(control, temp); |
| 983 | REG_WRITE(base, 0); |
| 984 | gma_power_end(dev); |
| 985 | } |
| 986 | |
| 987 | /* Unpin the old GEM object */ |
| 988 | if (psb_intel_crtc->cursor_obj) { |
| 989 | gt = container_of(psb_intel_crtc->cursor_obj, |
| 990 | struct gtt_range, gem); |
| 991 | psb_gtt_unpin(gt); |
| 992 | drm_gem_object_unreference(psb_intel_crtc->cursor_obj); |
| 993 | psb_intel_crtc->cursor_obj = NULL; |
| 994 | } |
| 995 | |
| 996 | return 0; |
| 997 | } |
| 998 | |
| 999 | /* Currently we only support 64x64 cursors */ |
| 1000 | if (width != 64 || height != 64) { |
| 1001 | dev_dbg(dev->dev, "we currently only support 64x64 cursors\n"); |
| 1002 | return -EINVAL; |
| 1003 | } |
| 1004 | |
| 1005 | obj = drm_gem_object_lookup(dev, file_priv, handle); |
| 1006 | if (!obj) |
| 1007 | return -ENOENT; |
| 1008 | |
| 1009 | if (obj->size < width * height * 4) { |
| 1010 | dev_dbg(dev->dev, "buffer is to small\n"); |
| 1011 | return -ENOMEM; |
| 1012 | } |
| 1013 | |
| 1014 | gt = container_of(obj, struct gtt_range, gem); |
| 1015 | |
| 1016 | /* Pin the memory into the GTT */ |
| 1017 | ret = psb_gtt_pin(gt); |
| 1018 | if (ret) { |
| 1019 | dev_err(dev->dev, "Can not pin down handle 0x%x\n", handle); |
| 1020 | return ret; |
| 1021 | } |
| 1022 | |
| 1023 | |
| 1024 | addr = gt->offset; /* Or resource.start ??? */ |
| 1025 | |
| 1026 | psb_intel_crtc->cursor_addr = addr; |
| 1027 | |
| 1028 | temp = 0; |
| 1029 | /* set the pipe for the cursor */ |
| 1030 | temp |= (pipe << 28); |
| 1031 | temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; |
| 1032 | |
| 1033 | if (gma_power_begin(dev, false)) { |
| 1034 | REG_WRITE(control, temp); |
| 1035 | REG_WRITE(base, addr); |
| 1036 | gma_power_end(dev); |
| 1037 | } |
| 1038 | |
| 1039 | /* unpin the old bo */ |
| 1040 | if (psb_intel_crtc->cursor_obj) { |
| 1041 | gt = container_of(psb_intel_crtc->cursor_obj, |
| 1042 | struct gtt_range, gem); |
| 1043 | psb_gtt_unpin(gt); |
| 1044 | drm_gem_object_unreference(psb_intel_crtc->cursor_obj); |
| 1045 | psb_intel_crtc->cursor_obj = obj; |
| 1046 | } |
| 1047 | return 0; |
| 1048 | } |
| 1049 | |
| 1050 | static int psb_intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) |
| 1051 | { |
| 1052 | struct drm_device *dev = crtc->dev; |
| 1053 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); |
| 1054 | int pipe = psb_intel_crtc->pipe; |
| 1055 | uint32_t temp = 0; |
| 1056 | uint32_t addr; |
| 1057 | |
| 1058 | |
| 1059 | if (x < 0) { |
| 1060 | temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT); |
| 1061 | x = -x; |
| 1062 | } |
| 1063 | if (y < 0) { |
| 1064 | temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT); |
| 1065 | y = -y; |
| 1066 | } |
| 1067 | |
| 1068 | temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT); |
| 1069 | temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT); |
| 1070 | |
| 1071 | addr = psb_intel_crtc->cursor_addr; |
| 1072 | |
| 1073 | if (gma_power_begin(dev, false)) { |
| 1074 | REG_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp); |
| 1075 | REG_WRITE((pipe == 0) ? CURABASE : CURBBASE, addr); |
| 1076 | gma_power_end(dev); |
| 1077 | } |
| 1078 | return 0; |
| 1079 | } |
| 1080 | |
| 1081 | void psb_intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, |
| 1082 | u16 *green, u16 *blue, uint32_t type, uint32_t size) |
| 1083 | { |
| 1084 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); |
| 1085 | int i; |
| 1086 | |
| 1087 | if (size != 256) |
| 1088 | return; |
| 1089 | |
| 1090 | for (i = 0; i < 256; i++) { |
| 1091 | psb_intel_crtc->lut_r[i] = red[i] >> 8; |
| 1092 | psb_intel_crtc->lut_g[i] = green[i] >> 8; |
| 1093 | psb_intel_crtc->lut_b[i] = blue[i] >> 8; |
| 1094 | } |
| 1095 | |
| 1096 | psb_intel_crtc_load_lut(crtc); |
| 1097 | } |
| 1098 | |
| 1099 | static int psb_crtc_set_config(struct drm_mode_set *set) |
| 1100 | { |
| 1101 | int ret; |
| 1102 | struct drm_device *dev = set->crtc->dev; |
| 1103 | struct drm_psb_private *dev_priv = dev->dev_private; |
| 1104 | |
| 1105 | if (!dev_priv->rpm_enabled) |
| 1106 | return drm_crtc_helper_set_config(set); |
| 1107 | |
| 1108 | pm_runtime_forbid(&dev->pdev->dev); |
| 1109 | ret = drm_crtc_helper_set_config(set); |
| 1110 | pm_runtime_allow(&dev->pdev->dev); |
| 1111 | return ret; |
| 1112 | } |
| 1113 | |
| 1114 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
| 1115 | static int psb_intel_crtc_clock_get(struct drm_device *dev, |
| 1116 | struct drm_crtc *crtc) |
| 1117 | { |
| 1118 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); |
| 1119 | int pipe = psb_intel_crtc->pipe; |
| 1120 | u32 dpll; |
| 1121 | u32 fp; |
| 1122 | struct psb_intel_clock_t clock; |
| 1123 | bool is_lvds; |
| 1124 | struct drm_psb_private *dev_priv = dev->dev_private; |
| 1125 | |
| 1126 | if (gma_power_begin(dev, false)) { |
| 1127 | dpll = REG_READ((pipe == 0) ? DPLL_A : DPLL_B); |
| 1128 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) |
| 1129 | fp = REG_READ((pipe == 0) ? FPA0 : FPB0); |
| 1130 | else |
| 1131 | fp = REG_READ((pipe == 0) ? FPA1 : FPB1); |
| 1132 | is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN); |
| 1133 | gma_power_end(dev); |
| 1134 | } else { |
| 1135 | dpll = (pipe == 0) ? |
| 1136 | dev_priv->saveDPLL_A : dev_priv->saveDPLL_B; |
| 1137 | |
| 1138 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) |
| 1139 | fp = (pipe == 0) ? |
| 1140 | dev_priv->saveFPA0 : |
| 1141 | dev_priv->saveFPB0; |
| 1142 | else |
| 1143 | fp = (pipe == 0) ? |
| 1144 | dev_priv->saveFPA1 : |
| 1145 | dev_priv->saveFPB1; |
| 1146 | |
| 1147 | is_lvds = (pipe == 1) && (dev_priv->saveLVDS & LVDS_PORT_EN); |
| 1148 | } |
| 1149 | |
| 1150 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; |
| 1151 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; |
| 1152 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; |
| 1153 | |
| 1154 | if (is_lvds) { |
| 1155 | clock.p1 = |
| 1156 | ffs((dpll & |
| 1157 | DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> |
| 1158 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
| 1159 | clock.p2 = 14; |
| 1160 | |
| 1161 | if ((dpll & PLL_REF_INPUT_MASK) == |
| 1162 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { |
| 1163 | /* XXX: might not be 66MHz */ |
| 1164 | i8xx_clock(66000, &clock); |
| 1165 | } else |
| 1166 | i8xx_clock(48000, &clock); |
| 1167 | } else { |
| 1168 | if (dpll & PLL_P1_DIVIDE_BY_TWO) |
| 1169 | clock.p1 = 2; |
| 1170 | else { |
| 1171 | clock.p1 = |
| 1172 | ((dpll & |
| 1173 | DPLL_FPA01_P1_POST_DIV_MASK_I830) >> |
| 1174 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; |
| 1175 | } |
| 1176 | if (dpll & PLL_P2_DIVIDE_BY_4) |
| 1177 | clock.p2 = 4; |
| 1178 | else |
| 1179 | clock.p2 = 2; |
| 1180 | |
| 1181 | i8xx_clock(48000, &clock); |
| 1182 | } |
| 1183 | |
| 1184 | /* XXX: It would be nice to validate the clocks, but we can't reuse |
| 1185 | * i830PllIsValid() because it relies on the xf86_config connector |
| 1186 | * configuration being accurate, which it isn't necessarily. |
| 1187 | */ |
| 1188 | |
| 1189 | return clock.dot; |
| 1190 | } |
| 1191 | |
| 1192 | /** Returns the currently programmed mode of the given pipe. */ |
| 1193 | struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev, |
| 1194 | struct drm_crtc *crtc) |
| 1195 | { |
| 1196 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); |
| 1197 | int pipe = psb_intel_crtc->pipe; |
| 1198 | struct drm_display_mode *mode; |
| 1199 | int htot; |
| 1200 | int hsync; |
| 1201 | int vtot; |
| 1202 | int vsync; |
| 1203 | struct drm_psb_private *dev_priv = dev->dev_private; |
| 1204 | |
| 1205 | if (gma_power_begin(dev, false)) { |
| 1206 | htot = REG_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B); |
| 1207 | hsync = REG_READ((pipe == 0) ? HSYNC_A : HSYNC_B); |
| 1208 | vtot = REG_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B); |
| 1209 | vsync = REG_READ((pipe == 0) ? VSYNC_A : VSYNC_B); |
| 1210 | gma_power_end(dev); |
| 1211 | } else { |
| 1212 | htot = (pipe == 0) ? |
| 1213 | dev_priv->saveHTOTAL_A : dev_priv->saveHTOTAL_B; |
| 1214 | hsync = (pipe == 0) ? |
| 1215 | dev_priv->saveHSYNC_A : dev_priv->saveHSYNC_B; |
| 1216 | vtot = (pipe == 0) ? |
| 1217 | dev_priv->saveVTOTAL_A : dev_priv->saveVTOTAL_B; |
| 1218 | vsync = (pipe == 0) ? |
| 1219 | dev_priv->saveVSYNC_A : dev_priv->saveVSYNC_B; |
| 1220 | } |
| 1221 | |
| 1222 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); |
| 1223 | if (!mode) |
| 1224 | return NULL; |
| 1225 | |
| 1226 | mode->clock = psb_intel_crtc_clock_get(dev, crtc); |
| 1227 | mode->hdisplay = (htot & 0xffff) + 1; |
| 1228 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; |
| 1229 | mode->hsync_start = (hsync & 0xffff) + 1; |
| 1230 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; |
| 1231 | mode->vdisplay = (vtot & 0xffff) + 1; |
| 1232 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; |
| 1233 | mode->vsync_start = (vsync & 0xffff) + 1; |
| 1234 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; |
| 1235 | |
| 1236 | drm_mode_set_name(mode); |
| 1237 | drm_mode_set_crtcinfo(mode, 0); |
| 1238 | |
| 1239 | return mode; |
| 1240 | } |
| 1241 | |
| 1242 | void psb_intel_crtc_destroy(struct drm_crtc *crtc) |
| 1243 | { |
| 1244 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); |
| 1245 | struct gtt_range *gt; |
| 1246 | |
| 1247 | /* Unpin the old GEM object */ |
| 1248 | if (psb_intel_crtc->cursor_obj) { |
| 1249 | gt = container_of(psb_intel_crtc->cursor_obj, |
| 1250 | struct gtt_range, gem); |
| 1251 | psb_gtt_unpin(gt); |
| 1252 | drm_gem_object_unreference(psb_intel_crtc->cursor_obj); |
| 1253 | psb_intel_crtc->cursor_obj = NULL; |
| 1254 | } |
| 1255 | kfree(psb_intel_crtc->crtc_state); |
| 1256 | drm_crtc_cleanup(crtc); |
| 1257 | kfree(psb_intel_crtc); |
| 1258 | } |
| 1259 | |
| 1260 | const struct drm_crtc_helper_funcs psb_intel_helper_funcs = { |
| 1261 | .dpms = psb_intel_crtc_dpms, |
| 1262 | .mode_fixup = psb_intel_crtc_mode_fixup, |
| 1263 | .mode_set = psb_intel_crtc_mode_set, |
| 1264 | .mode_set_base = psb_intel_pipe_set_base, |
| 1265 | .prepare = psb_intel_crtc_prepare, |
| 1266 | .commit = psb_intel_crtc_commit, |
| 1267 | }; |
| 1268 | |
| 1269 | const struct drm_crtc_funcs psb_intel_crtc_funcs = { |
| 1270 | .save = psb_intel_crtc_save, |
| 1271 | .restore = psb_intel_crtc_restore, |
| 1272 | .cursor_set = psb_intel_crtc_cursor_set, |
| 1273 | .cursor_move = psb_intel_crtc_cursor_move, |
| 1274 | .gamma_set = psb_intel_crtc_gamma_set, |
| 1275 | .set_config = psb_crtc_set_config, |
| 1276 | .destroy = psb_intel_crtc_destroy, |
| 1277 | }; |
| 1278 | |
| 1279 | /* |
| 1280 | * Set the default value of cursor control and base register |
| 1281 | * to zero. This is a workaround for h/w defect on Oaktrail |
| 1282 | */ |
| 1283 | static void psb_intel_cursor_init(struct drm_device *dev, int pipe) |
| 1284 | { |
| 1285 | u32 control[3] = { CURACNTR, CURBCNTR, CURCCNTR }; |
| 1286 | u32 base[3] = { CURABASE, CURBBASE, CURCBASE }; |
| 1287 | |
| 1288 | REG_WRITE(control[pipe], 0); |
| 1289 | REG_WRITE(base[pipe], 0); |
| 1290 | } |
| 1291 | |
| 1292 | void psb_intel_crtc_init(struct drm_device *dev, int pipe, |
| 1293 | struct psb_intel_mode_device *mode_dev) |
| 1294 | { |
| 1295 | struct drm_psb_private *dev_priv = dev->dev_private; |
| 1296 | struct psb_intel_crtc *psb_intel_crtc; |
| 1297 | int i; |
| 1298 | uint16_t *r_base, *g_base, *b_base; |
| 1299 | |
| 1300 | /* We allocate a extra array of drm_connector pointers |
| 1301 | * for fbdev after the crtc */ |
| 1302 | psb_intel_crtc = |
| 1303 | kzalloc(sizeof(struct psb_intel_crtc) + |
| 1304 | (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), |
| 1305 | GFP_KERNEL); |
| 1306 | if (psb_intel_crtc == NULL) |
| 1307 | return; |
| 1308 | |
| 1309 | psb_intel_crtc->crtc_state = |
| 1310 | kzalloc(sizeof(struct psb_intel_crtc_state), GFP_KERNEL); |
| 1311 | if (!psb_intel_crtc->crtc_state) { |
| 1312 | dev_err(dev->dev, "Crtc state error: No memory\n"); |
| 1313 | kfree(psb_intel_crtc); |
| 1314 | return; |
| 1315 | } |
| 1316 | |
| 1317 | /* Set the CRTC operations from the chip specific data */ |
| 1318 | drm_crtc_init(dev, &psb_intel_crtc->base, dev_priv->ops->crtc_funcs); |
| 1319 | |
| 1320 | drm_mode_crtc_set_gamma_size(&psb_intel_crtc->base, 256); |
| 1321 | psb_intel_crtc->pipe = pipe; |
| 1322 | psb_intel_crtc->plane = pipe; |
| 1323 | |
| 1324 | r_base = psb_intel_crtc->base.gamma_store; |
| 1325 | g_base = r_base + 256; |
| 1326 | b_base = g_base + 256; |
| 1327 | for (i = 0; i < 256; i++) { |
| 1328 | psb_intel_crtc->lut_r[i] = i; |
| 1329 | psb_intel_crtc->lut_g[i] = i; |
| 1330 | psb_intel_crtc->lut_b[i] = i; |
| 1331 | r_base[i] = i << 8; |
| 1332 | g_base[i] = i << 8; |
| 1333 | b_base[i] = i << 8; |
| 1334 | |
| 1335 | psb_intel_crtc->lut_adj[i] = 0; |
| 1336 | } |
| 1337 | |
| 1338 | psb_intel_crtc->mode_dev = mode_dev; |
| 1339 | psb_intel_crtc->cursor_addr = 0; |
| 1340 | |
| 1341 | drm_crtc_helper_add(&psb_intel_crtc->base, |
| 1342 | dev_priv->ops->crtc_helper); |
| 1343 | |
| 1344 | /* Setup the array of drm_connector pointer array */ |
| 1345 | psb_intel_crtc->mode_set.crtc = &psb_intel_crtc->base; |
| 1346 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
| 1347 | dev_priv->plane_to_crtc_mapping[psb_intel_crtc->plane] != NULL); |
| 1348 | dev_priv->plane_to_crtc_mapping[psb_intel_crtc->plane] = |
| 1349 | &psb_intel_crtc->base; |
| 1350 | dev_priv->pipe_to_crtc_mapping[psb_intel_crtc->pipe] = |
| 1351 | &psb_intel_crtc->base; |
| 1352 | psb_intel_crtc->mode_set.connectors = |
| 1353 | (struct drm_connector **) (psb_intel_crtc + 1); |
| 1354 | psb_intel_crtc->mode_set.num_connectors = 0; |
| 1355 | psb_intel_cursor_init(dev, pipe); |
| 1356 | } |
| 1357 | |
| 1358 | int psb_intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
| 1359 | struct drm_file *file_priv) |
| 1360 | { |
| 1361 | struct drm_psb_private *dev_priv = dev->dev_private; |
| 1362 | struct drm_psb_get_pipe_from_crtc_id_arg *pipe_from_crtc_id = data; |
| 1363 | struct drm_mode_object *drmmode_obj; |
| 1364 | struct psb_intel_crtc *crtc; |
| 1365 | |
| 1366 | if (!dev_priv) { |
| 1367 | dev_err(dev->dev, "called with no initialization\n"); |
| 1368 | return -EINVAL; |
| 1369 | } |
| 1370 | |
| 1371 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
| 1372 | DRM_MODE_OBJECT_CRTC); |
| 1373 | |
| 1374 | if (!drmmode_obj) { |
| 1375 | dev_err(dev->dev, "no such CRTC id\n"); |
| 1376 | return -EINVAL; |
| 1377 | } |
| 1378 | |
| 1379 | crtc = to_psb_intel_crtc(obj_to_crtc(drmmode_obj)); |
| 1380 | pipe_from_crtc_id->pipe = crtc->pipe; |
| 1381 | |
| 1382 | return 0; |
| 1383 | } |
| 1384 | |
| 1385 | struct drm_crtc *psb_intel_get_crtc_from_pipe(struct drm_device *dev, int pipe) |
| 1386 | { |
| 1387 | struct drm_crtc *crtc = NULL; |
| 1388 | |
| 1389 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 1390 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); |
| 1391 | if (psb_intel_crtc->pipe == pipe) |
| 1392 | break; |
| 1393 | } |
| 1394 | return crtc; |
| 1395 | } |
| 1396 | |
| 1397 | int psb_intel_connector_clones(struct drm_device *dev, int type_mask) |
| 1398 | { |
| 1399 | int index_mask = 0; |
| 1400 | struct drm_connector *connector; |
| 1401 | int entry = 0; |
| 1402 | |
| 1403 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
| 1404 | head) { |
| 1405 | struct psb_intel_output *psb_intel_output = |
| 1406 | to_psb_intel_output(connector); |
| 1407 | if (type_mask & (1 << psb_intel_output->type)) |
| 1408 | index_mask |= (1 << entry); |
| 1409 | entry++; |
| 1410 | } |
| 1411 | return index_mask; |
| 1412 | } |
| 1413 | |
| 1414 | |
| 1415 | void psb_intel_modeset_cleanup(struct drm_device *dev) |
| 1416 | { |
| 1417 | drm_mode_config_cleanup(dev); |
| 1418 | } |
| 1419 | |
| 1420 | |
| 1421 | /* current intel driver doesn't take advantage of encoders |
| 1422 | always give back the encoder for the connector |
| 1423 | */ |
| 1424 | struct drm_encoder *psb_intel_best_encoder(struct drm_connector *connector) |
| 1425 | { |
| 1426 | struct psb_intel_output *psb_intel_output = |
| 1427 | to_psb_intel_output(connector); |
| 1428 | |
| 1429 | return &psb_intel_output->enc; |
| 1430 | } |
| 1431 | |