blob: c7cd8e6802d75687169e69ba8b41cec57d40b1de [file] [log] [blame]
Marc Dietrichcc2afa42011-11-01 10:37:05 +00001/dts-v1/;
2
Laxman Dewangan6bccbd52013-12-02 18:39:57 +05303#include <dt-bindings/input/input.h>
Stephen Warren1bd0bd42012-10-17 16:38:21 -06004#include "tegra20.dtsi"
Marc Dietrichcc2afa42011-11-01 10:37:05 +00005
6/ {
7 model = "Toshiba AC100 / Dynabook AZ";
8 compatible = "compal,paz00", "nvidia,tegra20";
9
Stephen Warren553c0a22013-12-09 14:43:59 -070010 aliases {
11 rtc0 = "/i2c@7000d000/tps6586x@34";
12 rtc1 = "/rtc@7000e000";
13 };
14
Stephen Warrenf9eb26a2012-05-11 16:17:47 -060015 memory {
Marc Dietrichcc2afa42011-11-01 10:37:05 +000016 reg = <0x00000000 0x20000000>;
17 };
18
Stephen Warren58ecb232013-11-25 17:53:16 -070019 host1x@50000000 {
20 hdmi@54280000 {
Stephen Warren11a3c862013-01-02 14:53:22 -070021 status = "okay";
22
23 vdd-supply = <&hdmi_vdd_reg>;
24 pll-supply = <&hdmi_pll_reg>;
25
26 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
Stephen Warren3325f1b2013-02-12 17:25:15 -070027 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
28 GPIO_ACTIVE_HIGH>;
Stephen Warren11a3c862013-01-02 14:53:22 -070029 };
30 };
31
Stephen Warren58ecb232013-11-25 17:53:16 -070032 pinmux@70000014 {
Stephen Warrenecc295b2012-03-15 16:27:36 -060033 pinctrl-names = "default";
34 pinctrl-0 = <&state_default>;
35
36 state_default: pinmux {
37 ata {
38 nvidia,pins = "ata", "atc", "atd", "ate",
39 "dap2", "gmb", "gmc", "gmd", "spia",
40 "spib", "spic", "spid", "spie";
41 nvidia,function = "gmi";
42 };
43 atb {
44 nvidia,pins = "atb", "gma", "gme";
45 nvidia,function = "sdio4";
46 };
47 cdev1 {
48 nvidia,pins = "cdev1";
49 nvidia,function = "plla_out";
50 };
51 cdev2 {
52 nvidia,pins = "cdev2";
53 nvidia,function = "pllp_out4";
54 };
55 crtp {
56 nvidia,pins = "crtp";
57 nvidia,function = "crt";
58 };
59 csus {
60 nvidia,pins = "csus";
61 nvidia,function = "pllc_out1";
62 };
63 dap1 {
64 nvidia,pins = "dap1";
65 nvidia,function = "dap1";
66 };
67 dap3 {
68 nvidia,pins = "dap3";
69 nvidia,function = "dap3";
70 };
71 dap4 {
72 nvidia,pins = "dap4";
73 nvidia,function = "dap4";
74 };
75 ddc {
76 nvidia,pins = "ddc";
77 nvidia,function = "i2c2";
78 };
79 dta {
80 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
81 nvidia,function = "rsvd1";
82 };
83 dtf {
84 nvidia,pins = "dtf";
85 nvidia,function = "i2c3";
86 };
87 gpu {
88 nvidia,pins = "gpu", "sdb", "sdd";
89 nvidia,function = "pwm";
90 };
91 gpu7 {
92 nvidia,pins = "gpu7";
93 nvidia,function = "rtck";
94 };
95 gpv {
96 nvidia,pins = "gpv", "slxa", "slxk";
97 nvidia,function = "pcie";
98 };
99 hdint {
100 nvidia,pins = "hdint", "pta";
101 nvidia,function = "hdmi";
102 };
103 i2cp {
104 nvidia,pins = "i2cp";
105 nvidia,function = "i2cp";
106 };
107 irrx {
108 nvidia,pins = "irrx", "irtx";
109 nvidia,function = "uarta";
110 };
111 kbca {
112 nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
113 nvidia,function = "kbc";
114 };
115 kbcb {
116 nvidia,pins = "kbcb", "kbcd";
117 nvidia,function = "sdio2";
118 };
119 lcsn {
120 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
121 "ld3", "ld4", "ld5", "ld6", "ld7",
122 "ld8", "ld9", "ld10", "ld11", "ld12",
123 "ld13", "ld14", "ld15", "ld16", "ld17",
124 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
125 "lhs", "lm0", "lm1", "lpp", "lpw0",
126 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
127 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
128 "lvs";
129 nvidia,function = "displaya";
130 };
131 owc {
132 nvidia,pins = "owc";
133 nvidia,function = "owr";
134 };
135 pmc {
136 nvidia,pins = "pmc";
137 nvidia,function = "pwr_on";
138 };
139 rm {
140 nvidia,pins = "rm";
141 nvidia,function = "i2c1";
142 };
143 sdc {
144 nvidia,pins = "sdc";
145 nvidia,function = "twc";
146 };
147 sdio1 {
148 nvidia,pins = "sdio1";
149 nvidia,function = "sdio1";
150 };
151 slxc {
152 nvidia,pins = "slxc", "slxd";
153 nvidia,function = "spi4";
154 };
155 spdi {
156 nvidia,pins = "spdi", "spdo";
157 nvidia,function = "rsvd2";
158 };
159 spif {
160 nvidia,pins = "spif", "uac";
161 nvidia,function = "rsvd4";
162 };
163 spig {
164 nvidia,pins = "spig", "spih";
165 nvidia,function = "spi2_alt";
166 };
167 uaa {
168 nvidia,pins = "uaa", "uab", "uda";
169 nvidia,function = "ulpi";
170 };
171 uad {
172 nvidia,pins = "uad";
173 nvidia,function = "spdif";
174 };
175 uca {
176 nvidia,pins = "uca", "ucb";
177 nvidia,function = "uartc";
178 };
179 conf_ata {
180 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
Stephen Warren563da212012-04-13 16:35:20 -0600181 "cdev1", "cdev2", "dap1", "dap2", "dtf",
182 "gma", "gmb", "gmc", "gmd", "gme",
183 "gpu", "gpu7", "gpv", "i2cp", "pta",
184 "rm", "sdio1", "slxk", "spdo", "uac",
185 "uda";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530186 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
187 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600188 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600189 conf_ck32 {
190 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
191 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530192 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600193 };
194 conf_crtp {
195 nvidia,pins = "crtp", "dap3", "dap4", "dtb",
196 "dtc", "dte", "slxa", "slxc", "slxd",
197 "spdi";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530198 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
199 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600200 };
201 conf_csus {
202 nvidia,pins = "csus", "spia", "spib", "spid",
203 "spif";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530204 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
205 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600206 };
207 conf_ddc {
208 nvidia,pins = "ddc", "irrx", "irtx", "kbca",
209 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
210 "spic", "spig", "uaa", "uab";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530211 nvidia,pull = <TEGRA_PIN_PULL_UP>;
212 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600213 };
214 conf_dta {
215 nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
216 "spie", "spih", "uad", "uca", "ucb";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530217 nvidia,pull = <TEGRA_PIN_PULL_UP>;
218 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600219 };
220 conf_hdint {
221 nvidia,pins = "hdint", "ld0", "ld1", "ld2",
222 "ld3", "ld4", "ld5", "ld6", "ld7",
223 "ld8", "ld9", "ld10", "ld11", "ld12",
224 "ld13", "ld14", "ld15", "ld16", "ld17",
225 "ldc", "ldi", "lhs", "lsc0", "lspi",
226 "lvs", "pmc";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530227 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600228 };
229 conf_lc {
230 nvidia,pins = "lc", "ls";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530231 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600232 };
233 conf_lcsn {
234 nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
235 "lm0", "lm1", "lpp", "lpw0", "lpw1",
236 "lpw2", "lsc1", "lsck", "lsda", "lsdi",
237 "lvp0", "lvp1", "sdb";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530238 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600239 };
240 conf_ld17_0 {
241 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
242 "ld23_22";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530243 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600244 };
245 };
246 };
247
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600248 i2s@70002800 {
249 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600250 };
251
252 serial@70006000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600253 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600254 };
255
Stephen Warrenc04abb32012-05-11 17:03:26 -0600256 serial@70006200 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600257 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600258 };
259
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000260 i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600261 status = "okay";
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000262 clock-frequency = <400000>;
Leon Romanovsky613e9652012-02-02 22:13:35 +0200263
264 alc5632: alc5632@1e {
265 compatible = "realtek,alc5632";
266 reg = <0x1e>;
267 gpio-controller;
268 #gpio-cells = <2>;
269 };
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000270 };
271
Stephen Warren11a3c862013-01-02 14:53:22 -0700272 hdmi_ddc: i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600273 status = "okay";
Stephen Warren11a3c862013-01-02 14:53:22 -0700274 clock-frequency = <100000>;
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000275 };
276
Stephen Warren58ecb232013-11-25 17:53:16 -0700277 nvec@7000c500 {
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000278 compatible = "nvidia,nvec";
Stephen Warrenba04c282012-05-11 16:28:59 -0600279 reg = <0x7000c500 0x100>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700280 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600281 #address-cells = <1>;
282 #size-cells = <0>;
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000283 clock-frequency = <80000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700284 request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000285 slave-addr = <138>;
Hiroshi Doyu885a8cf2013-05-22 19:45:32 +0300286 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
287 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
Prashant Gaikwadd409b3a2013-01-11 13:31:23 +0530288 clock-names = "div-clk", "fast-clk";
Stephen Warren3393d422013-11-06 14:01:16 -0700289 resets = <&tegra_car 67>;
290 reset-names = "i2c";
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000291 };
292
293 i2c@7000d000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600294 status = "okay";
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000295 clock-frequency = <400000>;
Marc Dietrich1266f892012-01-31 19:53:21 +0100296
Stephen Warren217b8f02012-06-21 14:24:57 -0600297 pmic: tps6586x@34 {
298 compatible = "ti,tps6586x";
299 reg = <0x34>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700300 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
Stephen Warren217b8f02012-06-21 14:24:57 -0600301
302 #gpio-cells = <2>;
303 gpio-controller;
304
305 sys-supply = <&p5valw_reg>;
306 vin-sm0-supply = <&sys_reg>;
307 vin-sm1-supply = <&sys_reg>;
308 vin-sm2-supply = <&sys_reg>;
309 vinldo01-supply = <&sm2_reg>;
310 vinldo23-supply = <&sm2_reg>;
311 vinldo4-supply = <&sm2_reg>;
312 vinldo678-supply = <&sm2_reg>;
313 vinldo9-supply = <&sm2_reg>;
314
315 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600316 sys_reg: sys {
Stephen Warren217b8f02012-06-21 14:24:57 -0600317 regulator-name = "vdd_sys";
318 regulator-always-on;
319 };
320
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600321 sm0 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600322 regulator-name = "+1.2vs_sm0,vdd_core";
323 regulator-min-microvolt = <1200000>;
324 regulator-max-microvolt = <1200000>;
325 regulator-always-on;
326 };
327
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600328 sm1 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600329 regulator-name = "+1.0vs_sm1,vdd_cpu";
330 regulator-min-microvolt = <1000000>;
331 regulator-max-microvolt = <1000000>;
332 regulator-always-on;
333 };
334
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600335 sm2_reg: sm2 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600336 regulator-name = "+3.7vs_sm2,vin_ldo*";
337 regulator-min-microvolt = <3700000>;
338 regulator-max-microvolt = <3700000>;
339 regulator-always-on;
340 };
341
342 /* LDO0 is not connected to anything */
343
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600344 ldo1 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600345 regulator-name = "+1.1vs_ldo1,avdd_pll*";
346 regulator-min-microvolt = <1100000>;
347 regulator-max-microvolt = <1100000>;
348 regulator-always-on;
349 };
350
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600351 ldo2 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600352 regulator-name = "+1.2vs_ldo2,vdd_rtc";
353 regulator-min-microvolt = <1200000>;
354 regulator-max-microvolt = <1200000>;
355 };
356
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600357 ldo3 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600358 regulator-name = "+3.3vs_ldo3,avdd_usb*";
359 regulator-min-microvolt = <3300000>;
360 regulator-max-microvolt = <3300000>;
361 regulator-always-on;
362 };
363
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600364 ldo4 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600365 regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys";
366 regulator-min-microvolt = <1800000>;
367 regulator-max-microvolt = <1800000>;
368 regulator-always-on;
369 };
370
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600371 ldo5 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600372 regulator-name = "+2.85vs_ldo5,vcore_mmc";
373 regulator-min-microvolt = <2850000>;
374 regulator-max-microvolt = <2850000>;
375 regulator-always-on;
376 };
377
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600378 ldo6 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600379 /*
380 * Research indicates this should be
381 * 1.8v; other boards that use this
382 * rail for the same purpose need it
383 * set to 1.8v. The schematic signal
384 * name is incorrect; perhaps copied
385 * from an incorrect NVIDIA reference.
386 */
387 regulator-name = "+2.85vs_ldo6,avdd_vdac";
388 regulator-min-microvolt = <1800000>;
389 regulator-max-microvolt = <1800000>;
390 };
391
Stephen Warren11a3c862013-01-02 14:53:22 -0700392 hdmi_vdd_reg: ldo7 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600393 regulator-name = "+3.3vs_ldo7,avdd_hdmi";
394 regulator-min-microvolt = <3300000>;
395 regulator-max-microvolt = <3300000>;
396 };
397
Stephen Warren11a3c862013-01-02 14:53:22 -0700398 hdmi_pll_reg: ldo8 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600399 regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
400 regulator-min-microvolt = <1800000>;
401 regulator-max-microvolt = <1800000>;
402 };
403
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600404 ldo9 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600405 regulator-name = "+2.85vs_ldo9,vdd_ddr_rx";
406 regulator-min-microvolt = <2850000>;
407 regulator-max-microvolt = <2850000>;
408 regulator-always-on;
409 };
410
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600411 ldo_rtc {
Stephen Warren217b8f02012-06-21 14:24:57 -0600412 regulator-name = "+3.3vs_rtc";
413 regulator-min-microvolt = <3300000>;
414 regulator-max-microvolt = <3300000>;
415 regulator-always-on;
416 };
417 };
418 };
419
Marc Dietrich1266f892012-01-31 19:53:21 +0100420 adt7461@4c {
421 compatible = "adi,adt7461";
422 reg = <0x4c>;
423 };
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000424 };
425
Stephen Warren58ecb232013-11-25 17:53:16 -0700426 pmc@7000e400 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600427 nvidia,invert-interrupt;
Joseph Lo47d2d632013-08-12 17:40:07 +0800428 nvidia,suspend-mode = <1>;
Joseph Loa44a0192013-04-03 19:31:52 +0800429 nvidia,cpu-pwr-good-time = <2000>;
430 nvidia,cpu-pwr-off-time = <0>;
431 nvidia,core-pwr-good-time = <3845 3845>;
432 nvidia,core-pwr-off-time = <0>;
433 nvidia,sys-clock-req-active-high;
Stephen Warren217b8f02012-06-21 14:24:57 -0600434 };
435
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600436 usb@c5000000 {
437 status = "okay";
438 };
439
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530440 usb-phy@c5000000 {
441 status = "okay";
442 };
443
Stephen Warrenc04abb32012-05-11 17:03:26 -0600444 usb@c5004000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600445 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700446 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
447 GPIO_ACTIVE_LOW>;
Venu Byravarasu9dffe3b2013-05-16 19:42:56 +0530448 };
449
450 usb-phy@c5004000 {
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530451 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700452 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
453 GPIO_ACTIVE_LOW>;
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000454 };
455
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600456 usb@c5008000 {
457 status = "okay";
458 };
459
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530460 usb-phy@c5008000 {
461 status = "okay";
462 };
463
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000464 sdhci@c8000000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600465 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700466 cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>;
467 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
468 power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
Arnd Bergmann7f217792012-05-13 00:14:24 -0400469 bus-width = <4>;
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000470 };
471
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000472 sdhci@c8000600 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600473 status = "okay";
Arnd Bergmann7f217792012-05-13 00:14:24 -0400474 bus-width = <8>;
Joseph Lo7a2617a2013-04-03 14:34:39 -0600475 non-removable;
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000476 };
Marc Dietrichd8d56c82012-01-28 20:03:07 +0100477
Joseph Lo7021d122013-04-03 19:31:27 +0800478 clocks {
479 compatible = "simple-bus";
480 #address-cells = <1>;
481 #size-cells = <0>;
482
Stephen Warren58ecb232013-11-25 17:53:16 -0700483 clk32k_in: clock@0 {
Joseph Lo7021d122013-04-03 19:31:27 +0800484 compatible = "fixed-clock";
485 reg=<0>;
486 #clock-cells = <0>;
487 clock-frequency = <32768>;
488 };
489 };
490
Marc Dietrichd8d56c82012-01-28 20:03:07 +0100491 gpio-keys {
492 compatible = "gpio-keys";
493
494 power {
495 label = "Power";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700496 gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530497 linux,code = <KEY_POWER>;
Marc Dietrichd8d56c82012-01-28 20:03:07 +0100498 gpio-key,wakeup;
499 };
500 };
Marc Dietrich80c94732012-01-28 20:03:08 +0100501
502 gpio-leds {
503 compatible = "gpio-leds";
504
505 wifi {
506 label = "wifi-led";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700507 gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
Marc Dietrich80c94732012-01-28 20:03:08 +0100508 linux,default-trigger = "rfkill0";
509 };
510 };
Stephen Warrenaa607eb2012-04-12 15:46:49 -0600511
Stephen Warren217b8f02012-06-21 14:24:57 -0600512 regulators {
513 compatible = "simple-bus";
514 #address-cells = <1>;
515 #size-cells = <0>;
516
517 p5valw_reg: regulator@0 {
518 compatible = "regulator-fixed";
519 reg = <0>;
520 regulator-name = "+5valw";
521 regulator-min-microvolt = <5000000>;
522 regulator-max-microvolt = <5000000>;
523 regulator-always-on;
524 };
525 };
526
Stephen Warrenc04abb32012-05-11 17:03:26 -0600527 sound {
528 compatible = "nvidia,tegra-audio-alc5632-paz00",
529 "nvidia,tegra-audio-alc5632";
530
531 nvidia,model = "Compal PAZ00";
532
533 nvidia,audio-routing =
534 "Int Spk", "SPKOUT",
535 "Int Spk", "SPKOUTN",
536 "Headset Mic", "MICBIAS1",
537 "MIC1", "Headset Mic",
538 "Headset Stereophone", "HPR",
539 "Headset Stereophone", "HPL",
540 "DMICDAT", "Digital Mic";
541
542 nvidia,audio-codec = <&alc5632>;
543 nvidia,i2s-controller = <&tegra_i2s1>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700544 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
545 GPIO_ACTIVE_HIGH>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600546
Hiroshi Doyu885a8cf2013-05-22 19:45:32 +0300547 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
548 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
549 <&tegra_car TEGRA20_CLK_CDEV1>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600550 clock-names = "pll_a", "pll_a_out0", "mclk";
Stephen Warrenaa607eb2012-04-12 15:46:49 -0600551 };
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000552};