blob: 654876b7ba1deae84a06f89cdf617b153d4315ef [file] [log] [blame]
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001/*
2 * Copyright (C) 2007, 2008, Marvell International Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 * for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software Foundation,
15 * Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
16 */
17
18#ifndef MV_XOR_H
19#define MV_XOR_H
20
21#include <linux/types.h>
22#include <linux/io.h>
23#include <linux/dmaengine.h>
24#include <linux/interrupt.h>
25
26#define USE_TIMER
27#define MV_XOR_SLOT_SIZE 64
28#define MV_XOR_THRESHOLD 1
29
30#define XOR_OPERATION_MODE_XOR 0
31#define XOR_OPERATION_MODE_MEMCPY 2
32#define XOR_OPERATION_MODE_MEMSET 4
33
34#define XOR_CURR_DESC(chan) (chan->mmr_base + 0x210 + (chan->idx * 4))
35#define XOR_NEXT_DESC(chan) (chan->mmr_base + 0x200 + (chan->idx * 4))
36#define XOR_BYTE_COUNT(chan) (chan->mmr_base + 0x220 + (chan->idx * 4))
37#define XOR_DEST_POINTER(chan) (chan->mmr_base + 0x2B0 + (chan->idx * 4))
38#define XOR_BLOCK_SIZE(chan) (chan->mmr_base + 0x2C0 + (chan->idx * 4))
39#define XOR_INIT_VALUE_LOW(chan) (chan->mmr_base + 0x2E0)
40#define XOR_INIT_VALUE_HIGH(chan) (chan->mmr_base + 0x2E4)
41
42#define XOR_CONFIG(chan) (chan->mmr_base + 0x10 + (chan->idx * 4))
43#define XOR_ACTIVATION(chan) (chan->mmr_base + 0x20 + (chan->idx * 4))
44#define XOR_INTR_CAUSE(chan) (chan->mmr_base + 0x30)
45#define XOR_INTR_MASK(chan) (chan->mmr_base + 0x40)
46#define XOR_ERROR_CAUSE(chan) (chan->mmr_base + 0x50)
47#define XOR_ERROR_ADDR(chan) (chan->mmr_base + 0x60)
48#define XOR_INTR_MASK_VALUE 0x3F5
49
50#define WINDOW_BASE(w) (0x250 + ((w) << 2))
51#define WINDOW_SIZE(w) (0x270 + ((w) << 2))
52#define WINDOW_REMAP_HIGH(w) (0x290 + ((w) << 2))
53#define WINDOW_BAR_ENABLE(chan) (0x240 + ((chan) << 2))
54
55struct mv_xor_shared_private {
56 void __iomem *xor_base;
57 void __iomem *xor_high_base;
58};
59
60
61/**
62 * struct mv_xor_device - internal representation of a XOR device
63 * @pdev: Platform device
64 * @id: HW XOR Device selector
65 * @dma_desc_pool: base of DMA descriptor region (DMA address)
66 * @dma_desc_pool_virt: base of DMA descriptor region (CPU address)
67 * @common: embedded struct dma_device
68 */
69struct mv_xor_device {
70 struct platform_device *pdev;
71 int id;
72 dma_addr_t dma_desc_pool;
73 void *dma_desc_pool_virt;
74 struct dma_device common;
75 struct mv_xor_shared_private *shared;
76};
77
78/**
79 * struct mv_xor_chan - internal representation of a XOR channel
80 * @pending: allows batching of hardware operations
Saeed Bisharaff7b0472008-07-08 11:58:36 -070081 * @lock: serializes enqueue/dequeue operations to the descriptors pool
82 * @mmr_base: memory mapped register base
83 * @idx: the index of the xor channel
84 * @chain: device chain view of the descriptors
85 * @completed_slots: slots completed by HW but still need to be acked
86 * @device: parent device
87 * @common: common dmaengine channel object members
88 * @last_used: place holder for allocation to continue from where it left off
89 * @all_slots: complete domain of slots usable by the channel
90 * @slots_allocated: records the actual size of the descriptor slot pool
91 * @irq_tasklet: bottom half where mv_xor_slot_cleanup runs
92 */
93struct mv_xor_chan {
94 int pending;
Saeed Bisharaff7b0472008-07-08 11:58:36 -070095 spinlock_t lock; /* protects the descriptor slot pool */
96 void __iomem *mmr_base;
97 unsigned int idx;
98 enum dma_transaction_type current_type;
99 struct list_head chain;
100 struct list_head completed_slots;
101 struct mv_xor_device *device;
102 struct dma_chan common;
103 struct mv_xor_desc_slot *last_used;
104 struct list_head all_slots;
105 int slots_allocated;
106 struct tasklet_struct irq_tasklet;
107#ifdef USE_TIMER
108 unsigned long cleanup_time;
109 u32 current_on_last_cleanup;
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700110#endif
111};
112
113/**
114 * struct mv_xor_desc_slot - software descriptor
115 * @slot_node: node on the mv_xor_chan.all_slots list
116 * @chain_node: node on the mv_xor_chan.chain list
117 * @completed_node: node on the mv_xor_chan.completed_slots list
118 * @hw_desc: virtual address of the hardware descriptor chain
119 * @phys: hardware address of the hardware descriptor chain
120 * @group_head: first operation in a transaction
121 * @slot_cnt: total slots used in an transaction (group of operations)
122 * @slots_per_op: number of slots per operation
123 * @idx: pool index
124 * @unmap_src_cnt: number of xor sources
125 * @unmap_len: transaction bytecount
Dan Williams64203b62009-09-08 17:53:03 -0700126 * @tx_list: list of slots that make up a multi-descriptor transaction
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700127 * @async_tx: support for the async_tx api
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700128 * @xor_check_result: result of zero sum
129 * @crc32_result: result crc calculation
130 */
131struct mv_xor_desc_slot {
132 struct list_head slot_node;
133 struct list_head chain_node;
134 struct list_head completed_node;
135 enum dma_transaction_type type;
136 void *hw_desc;
137 struct mv_xor_desc_slot *group_head;
138 u16 slot_cnt;
139 u16 slots_per_op;
140 u16 idx;
141 u16 unmap_src_cnt;
142 u32 value;
143 size_t unmap_len;
Dan Williams64203b62009-09-08 17:53:03 -0700144 struct list_head tx_list;
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700145 struct dma_async_tx_descriptor async_tx;
146 union {
147 u32 *xor_check_result;
148 u32 *crc32_result;
149 };
150#ifdef USE_TIMER
151 unsigned long arrival_time;
152 struct timer_list timeout;
153#endif
154};
155
156/* This structure describes XOR descriptor size 64bytes */
157struct mv_xor_desc {
158 u32 status; /* descriptor execution status */
159 u32 crc32_result; /* result of CRC-32 calculation */
160 u32 desc_command; /* type of operation to be carried out */
161 u32 phy_next_desc; /* next descriptor address pointer */
162 u32 byte_count; /* size of src/dst blocks in bytes */
163 u32 phy_dest_addr; /* destination block address */
164 u32 phy_src_addr[8]; /* source block addresses */
165 u32 reserved0;
166 u32 reserved1;
167};
168
169#define to_mv_sw_desc(addr_hw_desc) \
170 container_of(addr_hw_desc, struct mv_xor_desc_slot, hw_desc)
171
172#define mv_hw_desc_slot_idx(hw_desc, idx) \
173 ((void *)(((unsigned long)hw_desc) + ((idx) << 5)))
174
175#define MV_XOR_MIN_BYTE_COUNT (128)
176#define XOR_MAX_BYTE_COUNT ((16 * 1024 * 1024) - 1)
177#define MV_XOR_MAX_BYTE_COUNT XOR_MAX_BYTE_COUNT
178
179
180#endif