Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. |
| 3 | * |
| 4 | * Refer to drivers/dma/imx-sdma.c |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | */ |
| 10 | |
| 11 | #include <linux/init.h> |
| 12 | #include <linux/types.h> |
| 13 | #include <linux/mm.h> |
| 14 | #include <linux/interrupt.h> |
| 15 | #include <linux/clk.h> |
| 16 | #include <linux/wait.h> |
| 17 | #include <linux/sched.h> |
| 18 | #include <linux/semaphore.h> |
| 19 | #include <linux/device.h> |
| 20 | #include <linux/dma-mapping.h> |
| 21 | #include <linux/slab.h> |
| 22 | #include <linux/platform_device.h> |
| 23 | #include <linux/dmaengine.h> |
| 24 | #include <linux/delay.h> |
Huang Shijie | 3946860 | 2012-02-16 14:17:32 +0800 | [diff] [blame] | 25 | #include <linux/fsl/mxs-dma.h> |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 26 | |
| 27 | #include <asm/irq.h> |
| 28 | #include <mach/mxs.h> |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 29 | #include <mach/common.h> |
| 30 | |
Russell King - ARM Linux | d2ebfb3 | 2012-03-06 22:34:26 +0000 | [diff] [blame] | 31 | #include "dmaengine.h" |
| 32 | |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 33 | /* |
| 34 | * NOTE: The term "PIO" throughout the mxs-dma implementation means |
| 35 | * PIO mode of mxs apbh-dma and apbx-dma. With this working mode, |
| 36 | * dma can program the controller registers of peripheral devices. |
| 37 | */ |
| 38 | |
| 39 | #define MXS_DMA_APBH 0 |
| 40 | #define MXS_DMA_APBX 1 |
| 41 | #define dma_is_apbh() (mxs_dma->dev_id == MXS_DMA_APBH) |
| 42 | |
| 43 | #define APBH_VERSION_LATEST 3 |
| 44 | #define apbh_is_old() (mxs_dma->version < APBH_VERSION_LATEST) |
| 45 | |
| 46 | #define HW_APBHX_CTRL0 0x000 |
| 47 | #define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29) |
| 48 | #define BM_APBH_CTRL0_APB_BURST_EN (1 << 28) |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 49 | #define BP_APBH_CTRL0_RESET_CHANNEL 16 |
| 50 | #define HW_APBHX_CTRL1 0x010 |
| 51 | #define HW_APBHX_CTRL2 0x020 |
| 52 | #define HW_APBHX_CHANNEL_CTRL 0x030 |
| 53 | #define BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL 16 |
| 54 | #define HW_APBH_VERSION (cpu_is_mx23() ? 0x3f0 : 0x800) |
| 55 | #define HW_APBX_VERSION 0x800 |
| 56 | #define BP_APBHX_VERSION_MAJOR 24 |
| 57 | #define HW_APBHX_CHn_NXTCMDAR(n) \ |
| 58 | (((dma_is_apbh() && apbh_is_old()) ? 0x050 : 0x110) + (n) * 0x70) |
| 59 | #define HW_APBHX_CHn_SEMA(n) \ |
| 60 | (((dma_is_apbh() && apbh_is_old()) ? 0x080 : 0x140) + (n) * 0x70) |
| 61 | |
| 62 | /* |
| 63 | * ccw bits definitions |
| 64 | * |
| 65 | * COMMAND: 0..1 (2) |
| 66 | * CHAIN: 2 (1) |
| 67 | * IRQ: 3 (1) |
| 68 | * NAND_LOCK: 4 (1) - not implemented |
| 69 | * NAND_WAIT4READY: 5 (1) - not implemented |
| 70 | * DEC_SEM: 6 (1) |
| 71 | * WAIT4END: 7 (1) |
| 72 | * HALT_ON_TERMINATE: 8 (1) |
| 73 | * TERMINATE_FLUSH: 9 (1) |
| 74 | * RESERVED: 10..11 (2) |
| 75 | * PIO_NUM: 12..15 (4) |
| 76 | */ |
| 77 | #define BP_CCW_COMMAND 0 |
| 78 | #define BM_CCW_COMMAND (3 << 0) |
| 79 | #define CCW_CHAIN (1 << 2) |
| 80 | #define CCW_IRQ (1 << 3) |
| 81 | #define CCW_DEC_SEM (1 << 6) |
| 82 | #define CCW_WAIT4END (1 << 7) |
| 83 | #define CCW_HALT_ON_TERM (1 << 8) |
| 84 | #define CCW_TERM_FLUSH (1 << 9) |
| 85 | #define BP_CCW_PIO_NUM 12 |
| 86 | #define BM_CCW_PIO_NUM (0xf << 12) |
| 87 | |
| 88 | #define BF_CCW(value, field) (((value) << BP_CCW_##field) & BM_CCW_##field) |
| 89 | |
| 90 | #define MXS_DMA_CMD_NO_XFER 0 |
| 91 | #define MXS_DMA_CMD_WRITE 1 |
| 92 | #define MXS_DMA_CMD_READ 2 |
| 93 | #define MXS_DMA_CMD_DMA_SENSE 3 /* not implemented */ |
| 94 | |
| 95 | struct mxs_dma_ccw { |
| 96 | u32 next; |
| 97 | u16 bits; |
| 98 | u16 xfer_bytes; |
| 99 | #define MAX_XFER_BYTES 0xff00 |
| 100 | u32 bufaddr; |
| 101 | #define MXS_PIO_WORDS 16 |
| 102 | u32 pio_words[MXS_PIO_WORDS]; |
| 103 | }; |
| 104 | |
| 105 | #define NUM_CCW (int)(PAGE_SIZE / sizeof(struct mxs_dma_ccw)) |
| 106 | |
| 107 | struct mxs_dma_chan { |
| 108 | struct mxs_dma_engine *mxs_dma; |
| 109 | struct dma_chan chan; |
| 110 | struct dma_async_tx_descriptor desc; |
| 111 | struct tasklet_struct tasklet; |
| 112 | int chan_irq; |
| 113 | struct mxs_dma_ccw *ccw; |
| 114 | dma_addr_t ccw_phys; |
Lothar Waßmann | 6d23ea4 | 2011-12-08 09:15:43 +0100 | [diff] [blame] | 115 | int desc_count; |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 116 | enum dma_status status; |
| 117 | unsigned int flags; |
| 118 | #define MXS_DMA_SG_LOOP (1 << 0) |
| 119 | }; |
| 120 | |
| 121 | #define MXS_DMA_CHANNELS 16 |
| 122 | #define MXS_DMA_CHANNELS_MASK 0xffff |
| 123 | |
| 124 | struct mxs_dma_engine { |
| 125 | int dev_id; |
| 126 | unsigned int version; |
| 127 | void __iomem *base; |
| 128 | struct clk *clk; |
| 129 | struct dma_device dma_device; |
| 130 | struct device_dma_parameters dma_parms; |
| 131 | struct mxs_dma_chan mxs_chans[MXS_DMA_CHANNELS]; |
| 132 | }; |
| 133 | |
| 134 | static void mxs_dma_reset_chan(struct mxs_dma_chan *mxs_chan) |
| 135 | { |
| 136 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; |
| 137 | int chan_id = mxs_chan->chan.chan_id; |
| 138 | |
| 139 | if (dma_is_apbh() && apbh_is_old()) |
| 140 | writel(1 << (chan_id + BP_APBH_CTRL0_RESET_CHANNEL), |
| 141 | mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR); |
| 142 | else |
| 143 | writel(1 << (chan_id + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL), |
| 144 | mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR); |
| 145 | } |
| 146 | |
| 147 | static void mxs_dma_enable_chan(struct mxs_dma_chan *mxs_chan) |
| 148 | { |
| 149 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; |
| 150 | int chan_id = mxs_chan->chan.chan_id; |
| 151 | |
| 152 | /* set cmd_addr up */ |
| 153 | writel(mxs_chan->ccw_phys, |
| 154 | mxs_dma->base + HW_APBHX_CHn_NXTCMDAR(chan_id)); |
| 155 | |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 156 | /* write 1 to SEMA to kick off the channel */ |
| 157 | writel(1, mxs_dma->base + HW_APBHX_CHn_SEMA(chan_id)); |
| 158 | } |
| 159 | |
| 160 | static void mxs_dma_disable_chan(struct mxs_dma_chan *mxs_chan) |
| 161 | { |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 162 | mxs_chan->status = DMA_SUCCESS; |
| 163 | } |
| 164 | |
| 165 | static void mxs_dma_pause_chan(struct mxs_dma_chan *mxs_chan) |
| 166 | { |
| 167 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; |
| 168 | int chan_id = mxs_chan->chan.chan_id; |
| 169 | |
| 170 | /* freeze the channel */ |
| 171 | if (dma_is_apbh() && apbh_is_old()) |
| 172 | writel(1 << chan_id, |
| 173 | mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR); |
| 174 | else |
| 175 | writel(1 << chan_id, |
| 176 | mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR); |
| 177 | |
| 178 | mxs_chan->status = DMA_PAUSED; |
| 179 | } |
| 180 | |
| 181 | static void mxs_dma_resume_chan(struct mxs_dma_chan *mxs_chan) |
| 182 | { |
| 183 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; |
| 184 | int chan_id = mxs_chan->chan.chan_id; |
| 185 | |
| 186 | /* unfreeze the channel */ |
| 187 | if (dma_is_apbh() && apbh_is_old()) |
| 188 | writel(1 << chan_id, |
| 189 | mxs_dma->base + HW_APBHX_CTRL0 + MXS_CLR_ADDR); |
| 190 | else |
| 191 | writel(1 << chan_id, |
| 192 | mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_CLR_ADDR); |
| 193 | |
| 194 | mxs_chan->status = DMA_IN_PROGRESS; |
| 195 | } |
| 196 | |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 197 | static struct mxs_dma_chan *to_mxs_dma_chan(struct dma_chan *chan) |
| 198 | { |
| 199 | return container_of(chan, struct mxs_dma_chan, chan); |
| 200 | } |
| 201 | |
| 202 | static dma_cookie_t mxs_dma_tx_submit(struct dma_async_tx_descriptor *tx) |
| 203 | { |
| 204 | struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(tx->chan); |
| 205 | |
| 206 | mxs_dma_enable_chan(mxs_chan); |
| 207 | |
Russell King - ARM Linux | 884485e | 2012-03-06 22:34:46 +0000 | [diff] [blame] | 208 | return dma_cookie_assign(tx); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 209 | } |
| 210 | |
| 211 | static void mxs_dma_tasklet(unsigned long data) |
| 212 | { |
| 213 | struct mxs_dma_chan *mxs_chan = (struct mxs_dma_chan *) data; |
| 214 | |
| 215 | if (mxs_chan->desc.callback) |
| 216 | mxs_chan->desc.callback(mxs_chan->desc.callback_param); |
| 217 | } |
| 218 | |
| 219 | static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id) |
| 220 | { |
| 221 | struct mxs_dma_engine *mxs_dma = dev_id; |
| 222 | u32 stat1, stat2; |
| 223 | |
| 224 | /* completion status */ |
| 225 | stat1 = readl(mxs_dma->base + HW_APBHX_CTRL1); |
| 226 | stat1 &= MXS_DMA_CHANNELS_MASK; |
| 227 | writel(stat1, mxs_dma->base + HW_APBHX_CTRL1 + MXS_CLR_ADDR); |
| 228 | |
| 229 | /* error status */ |
| 230 | stat2 = readl(mxs_dma->base + HW_APBHX_CTRL2); |
| 231 | writel(stat2, mxs_dma->base + HW_APBHX_CTRL2 + MXS_CLR_ADDR); |
| 232 | |
| 233 | /* |
| 234 | * When both completion and error of termination bits set at the |
| 235 | * same time, we do not take it as an error. IOW, it only becomes |
Lothar Waßmann | 4003122 | 2011-12-08 09:15:41 +0100 | [diff] [blame] | 236 | * an error we need to handle here in case of either it's (1) a bus |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 237 | * error or (2) a termination error with no completion. |
| 238 | */ |
| 239 | stat2 = ((stat2 >> MXS_DMA_CHANNELS) & stat2) | /* (1) */ |
| 240 | (~(stat2 >> MXS_DMA_CHANNELS) & stat2 & ~stat1); /* (2) */ |
| 241 | |
| 242 | /* combine error and completion status for checking */ |
| 243 | stat1 = (stat2 << MXS_DMA_CHANNELS) | stat1; |
| 244 | while (stat1) { |
| 245 | int channel = fls(stat1) - 1; |
| 246 | struct mxs_dma_chan *mxs_chan = |
| 247 | &mxs_dma->mxs_chans[channel % MXS_DMA_CHANNELS]; |
| 248 | |
| 249 | if (channel >= MXS_DMA_CHANNELS) { |
| 250 | dev_dbg(mxs_dma->dma_device.dev, |
| 251 | "%s: error in channel %d\n", __func__, |
| 252 | channel - MXS_DMA_CHANNELS); |
| 253 | mxs_chan->status = DMA_ERROR; |
| 254 | mxs_dma_reset_chan(mxs_chan); |
| 255 | } else { |
| 256 | if (mxs_chan->flags & MXS_DMA_SG_LOOP) |
| 257 | mxs_chan->status = DMA_IN_PROGRESS; |
| 258 | else |
| 259 | mxs_chan->status = DMA_SUCCESS; |
| 260 | } |
| 261 | |
| 262 | stat1 &= ~(1 << channel); |
| 263 | |
| 264 | if (mxs_chan->status == DMA_SUCCESS) |
Russell King - ARM Linux | f7fbce0 | 2012-03-06 22:35:07 +0000 | [diff] [blame] | 265 | dma_cookie_complete(&mxs_chan->desc); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 266 | |
| 267 | /* schedule tasklet on this channel */ |
| 268 | tasklet_schedule(&mxs_chan->tasklet); |
| 269 | } |
| 270 | |
| 271 | return IRQ_HANDLED; |
| 272 | } |
| 273 | |
| 274 | static int mxs_dma_alloc_chan_resources(struct dma_chan *chan) |
| 275 | { |
| 276 | struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); |
| 277 | struct mxs_dma_data *data = chan->private; |
| 278 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; |
| 279 | int ret; |
| 280 | |
| 281 | if (!data) |
| 282 | return -EINVAL; |
| 283 | |
| 284 | mxs_chan->chan_irq = data->chan_irq; |
| 285 | |
| 286 | mxs_chan->ccw = dma_alloc_coherent(mxs_dma->dma_device.dev, PAGE_SIZE, |
| 287 | &mxs_chan->ccw_phys, GFP_KERNEL); |
| 288 | if (!mxs_chan->ccw) { |
| 289 | ret = -ENOMEM; |
| 290 | goto err_alloc; |
| 291 | } |
| 292 | |
| 293 | memset(mxs_chan->ccw, 0, PAGE_SIZE); |
| 294 | |
Shawn Guo | 95bfea1 | 2011-06-30 16:06:33 +0800 | [diff] [blame] | 295 | if (mxs_chan->chan_irq != NO_IRQ) { |
| 296 | ret = request_irq(mxs_chan->chan_irq, mxs_dma_int_handler, |
| 297 | 0, "mxs-dma", mxs_dma); |
| 298 | if (ret) |
| 299 | goto err_irq; |
| 300 | } |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 301 | |
Shawn Guo | 759a2e3 | 2011-12-20 13:54:00 +0800 | [diff] [blame] | 302 | ret = clk_prepare_enable(mxs_dma->clk); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 303 | if (ret) |
| 304 | goto err_clk; |
| 305 | |
| 306 | mxs_dma_reset_chan(mxs_chan); |
| 307 | |
| 308 | dma_async_tx_descriptor_init(&mxs_chan->desc, chan); |
| 309 | mxs_chan->desc.tx_submit = mxs_dma_tx_submit; |
| 310 | |
| 311 | /* the descriptor is ready */ |
| 312 | async_tx_ack(&mxs_chan->desc); |
| 313 | |
| 314 | return 0; |
| 315 | |
| 316 | err_clk: |
| 317 | free_irq(mxs_chan->chan_irq, mxs_dma); |
| 318 | err_irq: |
| 319 | dma_free_coherent(mxs_dma->dma_device.dev, PAGE_SIZE, |
| 320 | mxs_chan->ccw, mxs_chan->ccw_phys); |
| 321 | err_alloc: |
| 322 | return ret; |
| 323 | } |
| 324 | |
| 325 | static void mxs_dma_free_chan_resources(struct dma_chan *chan) |
| 326 | { |
| 327 | struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); |
| 328 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; |
| 329 | |
| 330 | mxs_dma_disable_chan(mxs_chan); |
| 331 | |
| 332 | free_irq(mxs_chan->chan_irq, mxs_dma); |
| 333 | |
| 334 | dma_free_coherent(mxs_dma->dma_device.dev, PAGE_SIZE, |
| 335 | mxs_chan->ccw, mxs_chan->ccw_phys); |
| 336 | |
Shawn Guo | 759a2e3 | 2011-12-20 13:54:00 +0800 | [diff] [blame] | 337 | clk_disable_unprepare(mxs_dma->clk); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 338 | } |
| 339 | |
Huang Shijie | 921de86 | 2012-02-16 14:17:33 +0800 | [diff] [blame] | 340 | /* |
| 341 | * How to use the flags for ->device_prep_slave_sg() : |
| 342 | * [1] If there is only one DMA command in the DMA chain, the code should be: |
| 343 | * ...... |
| 344 | * ->device_prep_slave_sg(DMA_CTRL_ACK); |
| 345 | * ...... |
| 346 | * [2] If there are two DMA commands in the DMA chain, the code should be |
| 347 | * ...... |
| 348 | * ->device_prep_slave_sg(0); |
| 349 | * ...... |
| 350 | * ->device_prep_slave_sg(DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 351 | * ...... |
| 352 | * [3] If there are more than two DMA commands in the DMA chain, the code |
| 353 | * should be: |
| 354 | * ...... |
| 355 | * ->device_prep_slave_sg(0); // First |
| 356 | * ...... |
| 357 | * ->device_prep_slave_sg(DMA_PREP_INTERRUPT [| DMA_CTRL_ACK]); |
| 358 | * ...... |
| 359 | * ->device_prep_slave_sg(DMA_PREP_INTERRUPT | DMA_CTRL_ACK); // Last |
| 360 | * ...... |
| 361 | */ |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 362 | static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg( |
| 363 | struct dma_chan *chan, struct scatterlist *sgl, |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 364 | unsigned int sg_len, enum dma_transfer_direction direction, |
Linus Torvalds | 623ff77 | 2012-03-30 17:31:56 -0700 | [diff] [blame] | 365 | unsigned long flags, void *context) |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 366 | { |
| 367 | struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); |
| 368 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; |
| 369 | struct mxs_dma_ccw *ccw; |
| 370 | struct scatterlist *sg; |
| 371 | int i, j; |
| 372 | u32 *pio; |
Huang Shijie | 921de86 | 2012-02-16 14:17:33 +0800 | [diff] [blame] | 373 | bool append = flags & DMA_PREP_INTERRUPT; |
Lothar Waßmann | 6d23ea4 | 2011-12-08 09:15:43 +0100 | [diff] [blame] | 374 | int idx = append ? mxs_chan->desc_count : 0; |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 375 | |
| 376 | if (mxs_chan->status == DMA_IN_PROGRESS && !append) |
| 377 | return NULL; |
| 378 | |
| 379 | if (sg_len + (append ? idx : 0) > NUM_CCW) { |
| 380 | dev_err(mxs_dma->dma_device.dev, |
| 381 | "maximum number of sg exceeded: %d > %d\n", |
| 382 | sg_len, NUM_CCW); |
| 383 | goto err_out; |
| 384 | } |
| 385 | |
| 386 | mxs_chan->status = DMA_IN_PROGRESS; |
| 387 | mxs_chan->flags = 0; |
| 388 | |
| 389 | /* |
| 390 | * If the sg is prepared with append flag set, the sg |
| 391 | * will be appended to the last prepared sg. |
| 392 | */ |
| 393 | if (append) { |
| 394 | BUG_ON(idx < 1); |
| 395 | ccw = &mxs_chan->ccw[idx - 1]; |
| 396 | ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx; |
| 397 | ccw->bits |= CCW_CHAIN; |
| 398 | ccw->bits &= ~CCW_IRQ; |
| 399 | ccw->bits &= ~CCW_DEC_SEM; |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 400 | } else { |
| 401 | idx = 0; |
| 402 | } |
| 403 | |
Shawn Guo | 62268ce | 2011-12-13 23:48:03 +0800 | [diff] [blame] | 404 | if (direction == DMA_TRANS_NONE) { |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 405 | ccw = &mxs_chan->ccw[idx++]; |
| 406 | pio = (u32 *) sgl; |
| 407 | |
| 408 | for (j = 0; j < sg_len;) |
| 409 | ccw->pio_words[j++] = *pio++; |
| 410 | |
| 411 | ccw->bits = 0; |
| 412 | ccw->bits |= CCW_IRQ; |
| 413 | ccw->bits |= CCW_DEC_SEM; |
Huang Shijie | 921de86 | 2012-02-16 14:17:33 +0800 | [diff] [blame] | 414 | if (flags & DMA_CTRL_ACK) |
| 415 | ccw->bits |= CCW_WAIT4END; |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 416 | ccw->bits |= CCW_HALT_ON_TERM; |
| 417 | ccw->bits |= CCW_TERM_FLUSH; |
| 418 | ccw->bits |= BF_CCW(sg_len, PIO_NUM); |
| 419 | ccw->bits |= BF_CCW(MXS_DMA_CMD_NO_XFER, COMMAND); |
| 420 | } else { |
| 421 | for_each_sg(sgl, sg, sg_len, i) { |
| 422 | if (sg->length > MAX_XFER_BYTES) { |
| 423 | dev_err(mxs_dma->dma_device.dev, "maximum bytes for sg entry exceeded: %d > %d\n", |
| 424 | sg->length, MAX_XFER_BYTES); |
| 425 | goto err_out; |
| 426 | } |
| 427 | |
| 428 | ccw = &mxs_chan->ccw[idx++]; |
| 429 | |
| 430 | ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx; |
| 431 | ccw->bufaddr = sg->dma_address; |
| 432 | ccw->xfer_bytes = sg->length; |
| 433 | |
| 434 | ccw->bits = 0; |
| 435 | ccw->bits |= CCW_CHAIN; |
| 436 | ccw->bits |= CCW_HALT_ON_TERM; |
| 437 | ccw->bits |= CCW_TERM_FLUSH; |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 438 | ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ? |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 439 | MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, |
| 440 | COMMAND); |
| 441 | |
| 442 | if (i + 1 == sg_len) { |
| 443 | ccw->bits &= ~CCW_CHAIN; |
| 444 | ccw->bits |= CCW_IRQ; |
| 445 | ccw->bits |= CCW_DEC_SEM; |
Huang Shijie | 921de86 | 2012-02-16 14:17:33 +0800 | [diff] [blame] | 446 | if (flags & DMA_CTRL_ACK) |
| 447 | ccw->bits |= CCW_WAIT4END; |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 448 | } |
| 449 | } |
| 450 | } |
Lothar Waßmann | 6d23ea4 | 2011-12-08 09:15:43 +0100 | [diff] [blame] | 451 | mxs_chan->desc_count = idx; |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 452 | |
| 453 | return &mxs_chan->desc; |
| 454 | |
| 455 | err_out: |
| 456 | mxs_chan->status = DMA_ERROR; |
| 457 | return NULL; |
| 458 | } |
| 459 | |
| 460 | static struct dma_async_tx_descriptor *mxs_dma_prep_dma_cyclic( |
| 461 | struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, |
Alexandre Bounine | 185ecb5 | 2012-03-08 15:35:13 -0500 | [diff] [blame] | 462 | size_t period_len, enum dma_transfer_direction direction, |
| 463 | void *context) |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 464 | { |
| 465 | struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); |
| 466 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; |
| 467 | int num_periods = buf_len / period_len; |
| 468 | int i = 0, buf = 0; |
| 469 | |
| 470 | if (mxs_chan->status == DMA_IN_PROGRESS) |
| 471 | return NULL; |
| 472 | |
| 473 | mxs_chan->status = DMA_IN_PROGRESS; |
| 474 | mxs_chan->flags |= MXS_DMA_SG_LOOP; |
| 475 | |
| 476 | if (num_periods > NUM_CCW) { |
| 477 | dev_err(mxs_dma->dma_device.dev, |
| 478 | "maximum number of sg exceeded: %d > %d\n", |
| 479 | num_periods, NUM_CCW); |
| 480 | goto err_out; |
| 481 | } |
| 482 | |
| 483 | if (period_len > MAX_XFER_BYTES) { |
| 484 | dev_err(mxs_dma->dma_device.dev, |
| 485 | "maximum period size exceeded: %d > %d\n", |
| 486 | period_len, MAX_XFER_BYTES); |
| 487 | goto err_out; |
| 488 | } |
| 489 | |
| 490 | while (buf < buf_len) { |
| 491 | struct mxs_dma_ccw *ccw = &mxs_chan->ccw[i]; |
| 492 | |
| 493 | if (i + 1 == num_periods) |
| 494 | ccw->next = mxs_chan->ccw_phys; |
| 495 | else |
| 496 | ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * (i + 1); |
| 497 | |
| 498 | ccw->bufaddr = dma_addr; |
| 499 | ccw->xfer_bytes = period_len; |
| 500 | |
| 501 | ccw->bits = 0; |
| 502 | ccw->bits |= CCW_CHAIN; |
| 503 | ccw->bits |= CCW_IRQ; |
| 504 | ccw->bits |= CCW_HALT_ON_TERM; |
| 505 | ccw->bits |= CCW_TERM_FLUSH; |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 506 | ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ? |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 507 | MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, COMMAND); |
| 508 | |
| 509 | dma_addr += period_len; |
| 510 | buf += period_len; |
| 511 | |
| 512 | i++; |
| 513 | } |
Lothar Waßmann | 6d23ea4 | 2011-12-08 09:15:43 +0100 | [diff] [blame] | 514 | mxs_chan->desc_count = i; |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 515 | |
| 516 | return &mxs_chan->desc; |
| 517 | |
| 518 | err_out: |
| 519 | mxs_chan->status = DMA_ERROR; |
| 520 | return NULL; |
| 521 | } |
| 522 | |
| 523 | static int mxs_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
| 524 | unsigned long arg) |
| 525 | { |
| 526 | struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); |
| 527 | int ret = 0; |
| 528 | |
| 529 | switch (cmd) { |
| 530 | case DMA_TERMINATE_ALL: |
Dong Aisheng | a62bae9 | 2011-07-19 12:09:56 +0800 | [diff] [blame] | 531 | mxs_dma_reset_chan(mxs_chan); |
Lothar Waßmann | 7ad7a34 | 2011-12-08 09:15:44 +0100 | [diff] [blame] | 532 | mxs_dma_disable_chan(mxs_chan); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 533 | break; |
| 534 | case DMA_PAUSE: |
| 535 | mxs_dma_pause_chan(mxs_chan); |
| 536 | break; |
| 537 | case DMA_RESUME: |
| 538 | mxs_dma_resume_chan(mxs_chan); |
| 539 | break; |
| 540 | default: |
| 541 | ret = -ENOSYS; |
| 542 | } |
| 543 | |
| 544 | return ret; |
| 545 | } |
| 546 | |
| 547 | static enum dma_status mxs_dma_tx_status(struct dma_chan *chan, |
| 548 | dma_cookie_t cookie, struct dma_tx_state *txstate) |
| 549 | { |
| 550 | struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); |
| 551 | dma_cookie_t last_used; |
| 552 | |
| 553 | last_used = chan->cookie; |
Russell King - ARM Linux | 4d4e58d | 2012-03-06 22:34:06 +0000 | [diff] [blame] | 554 | dma_set_tx_state(txstate, chan->completed_cookie, last_used, 0); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 555 | |
| 556 | return mxs_chan->status; |
| 557 | } |
| 558 | |
| 559 | static void mxs_dma_issue_pending(struct dma_chan *chan) |
| 560 | { |
| 561 | /* |
| 562 | * Nothing to do. We only have a single descriptor. |
| 563 | */ |
| 564 | } |
| 565 | |
| 566 | static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma) |
| 567 | { |
| 568 | int ret; |
| 569 | |
Shawn Guo | 759a2e3 | 2011-12-20 13:54:00 +0800 | [diff] [blame] | 570 | ret = clk_prepare_enable(mxs_dma->clk); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 571 | if (ret) |
Lothar Waßmann | feb397d | 2011-12-08 09:15:42 +0100 | [diff] [blame] | 572 | return ret; |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 573 | |
| 574 | ret = mxs_reset_block(mxs_dma->base); |
| 575 | if (ret) |
| 576 | goto err_out; |
| 577 | |
| 578 | /* only major version matters */ |
| 579 | mxs_dma->version = readl(mxs_dma->base + |
| 580 | ((mxs_dma->dev_id == MXS_DMA_APBX) ? |
| 581 | HW_APBX_VERSION : HW_APBH_VERSION)) >> |
| 582 | BP_APBHX_VERSION_MAJOR; |
| 583 | |
| 584 | /* enable apbh burst */ |
| 585 | if (dma_is_apbh()) { |
| 586 | writel(BM_APBH_CTRL0_APB_BURST_EN, |
| 587 | mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR); |
| 588 | writel(BM_APBH_CTRL0_APB_BURST8_EN, |
| 589 | mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR); |
| 590 | } |
| 591 | |
| 592 | /* enable irq for all the channels */ |
| 593 | writel(MXS_DMA_CHANNELS_MASK << MXS_DMA_CHANNELS, |
| 594 | mxs_dma->base + HW_APBHX_CTRL1 + MXS_SET_ADDR); |
| 595 | |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 596 | err_out: |
Linus Torvalds | 57f2685 | 2012-01-17 18:40:24 -0800 | [diff] [blame] | 597 | clk_disable_unprepare(mxs_dma->clk); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 598 | return ret; |
| 599 | } |
| 600 | |
| 601 | static int __init mxs_dma_probe(struct platform_device *pdev) |
| 602 | { |
| 603 | const struct platform_device_id *id_entry = |
| 604 | platform_get_device_id(pdev); |
| 605 | struct mxs_dma_engine *mxs_dma; |
| 606 | struct resource *iores; |
| 607 | int ret, i; |
| 608 | |
| 609 | mxs_dma = kzalloc(sizeof(*mxs_dma), GFP_KERNEL); |
| 610 | if (!mxs_dma) |
| 611 | return -ENOMEM; |
| 612 | |
| 613 | mxs_dma->dev_id = id_entry->driver_data; |
| 614 | |
| 615 | iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 616 | |
| 617 | if (!request_mem_region(iores->start, resource_size(iores), |
| 618 | pdev->name)) { |
| 619 | ret = -EBUSY; |
| 620 | goto err_request_region; |
| 621 | } |
| 622 | |
| 623 | mxs_dma->base = ioremap(iores->start, resource_size(iores)); |
| 624 | if (!mxs_dma->base) { |
| 625 | ret = -ENOMEM; |
| 626 | goto err_ioremap; |
| 627 | } |
| 628 | |
| 629 | mxs_dma->clk = clk_get(&pdev->dev, NULL); |
| 630 | if (IS_ERR(mxs_dma->clk)) { |
| 631 | ret = PTR_ERR(mxs_dma->clk); |
| 632 | goto err_clk; |
| 633 | } |
| 634 | |
| 635 | dma_cap_set(DMA_SLAVE, mxs_dma->dma_device.cap_mask); |
| 636 | dma_cap_set(DMA_CYCLIC, mxs_dma->dma_device.cap_mask); |
| 637 | |
| 638 | INIT_LIST_HEAD(&mxs_dma->dma_device.channels); |
| 639 | |
| 640 | /* Initialize channel parameters */ |
| 641 | for (i = 0; i < MXS_DMA_CHANNELS; i++) { |
| 642 | struct mxs_dma_chan *mxs_chan = &mxs_dma->mxs_chans[i]; |
| 643 | |
| 644 | mxs_chan->mxs_dma = mxs_dma; |
| 645 | mxs_chan->chan.device = &mxs_dma->dma_device; |
Russell King - ARM Linux | 8ac6954 | 2012-03-06 22:36:27 +0000 | [diff] [blame] | 646 | dma_cookie_init(&mxs_chan->chan); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 647 | |
| 648 | tasklet_init(&mxs_chan->tasklet, mxs_dma_tasklet, |
| 649 | (unsigned long) mxs_chan); |
| 650 | |
| 651 | |
| 652 | /* Add the channel to mxs_chan list */ |
| 653 | list_add_tail(&mxs_chan->chan.device_node, |
| 654 | &mxs_dma->dma_device.channels); |
| 655 | } |
| 656 | |
| 657 | ret = mxs_dma_init(mxs_dma); |
| 658 | if (ret) |
| 659 | goto err_init; |
| 660 | |
| 661 | mxs_dma->dma_device.dev = &pdev->dev; |
| 662 | |
| 663 | /* mxs_dma gets 65535 bytes maximum sg size */ |
| 664 | mxs_dma->dma_device.dev->dma_parms = &mxs_dma->dma_parms; |
| 665 | dma_set_max_seg_size(mxs_dma->dma_device.dev, MAX_XFER_BYTES); |
| 666 | |
| 667 | mxs_dma->dma_device.device_alloc_chan_resources = mxs_dma_alloc_chan_resources; |
| 668 | mxs_dma->dma_device.device_free_chan_resources = mxs_dma_free_chan_resources; |
| 669 | mxs_dma->dma_device.device_tx_status = mxs_dma_tx_status; |
| 670 | mxs_dma->dma_device.device_prep_slave_sg = mxs_dma_prep_slave_sg; |
| 671 | mxs_dma->dma_device.device_prep_dma_cyclic = mxs_dma_prep_dma_cyclic; |
| 672 | mxs_dma->dma_device.device_control = mxs_dma_control; |
| 673 | mxs_dma->dma_device.device_issue_pending = mxs_dma_issue_pending; |
| 674 | |
| 675 | ret = dma_async_device_register(&mxs_dma->dma_device); |
| 676 | if (ret) { |
| 677 | dev_err(mxs_dma->dma_device.dev, "unable to register\n"); |
| 678 | goto err_init; |
| 679 | } |
| 680 | |
| 681 | dev_info(mxs_dma->dma_device.dev, "initialized\n"); |
| 682 | |
| 683 | return 0; |
| 684 | |
| 685 | err_init: |
| 686 | clk_put(mxs_dma->clk); |
| 687 | err_clk: |
| 688 | iounmap(mxs_dma->base); |
| 689 | err_ioremap: |
| 690 | release_mem_region(iores->start, resource_size(iores)); |
| 691 | err_request_region: |
| 692 | kfree(mxs_dma); |
| 693 | return ret; |
| 694 | } |
| 695 | |
| 696 | static struct platform_device_id mxs_dma_type[] = { |
| 697 | { |
| 698 | .name = "mxs-dma-apbh", |
| 699 | .driver_data = MXS_DMA_APBH, |
| 700 | }, { |
| 701 | .name = "mxs-dma-apbx", |
| 702 | .driver_data = MXS_DMA_APBX, |
Axel Lin | 2a9778e | 2011-07-12 18:53:52 +0800 | [diff] [blame] | 703 | }, { |
| 704 | /* end of list */ |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 705 | } |
| 706 | }; |
| 707 | |
| 708 | static struct platform_driver mxs_dma_driver = { |
| 709 | .driver = { |
| 710 | .name = "mxs-dma", |
| 711 | }, |
| 712 | .id_table = mxs_dma_type, |
| 713 | }; |
| 714 | |
| 715 | static int __init mxs_dma_module_init(void) |
| 716 | { |
| 717 | return platform_driver_probe(&mxs_dma_driver, mxs_dma_probe); |
| 718 | } |
| 719 | subsys_initcall(mxs_dma_module_init); |