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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3 *
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey. It's neither supported nor endorsed
7 * by NVIDIA Corp. Use at your own risk.
8 *
9 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
10 * trademarks of NVIDIA Corporation in the United States and other
11 * countries.
12 *
13 * Copyright (C) 2003,4 Manfred Spraul
14 * Copyright (C) 2004 Andrew de Quincey (wol support)
15 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
16 * IRQ rate fixes, bigendian fixes, cleanups, verification)
17 * Copyright (c) 2004 NVIDIA Corporation
18 *
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License as published by
21 * the Free Software Foundation; either version 2 of the License, or
22 * (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
32 *
33 * Changelog:
34 * 0.01: 05 Oct 2003: First release that compiles without warnings.
35 * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
36 * Check all PCI BARs for the register window.
37 * udelay added to mii_rw.
38 * 0.03: 06 Oct 2003: Initialize dev->irq.
39 * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
40 * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
41 * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
42 * irq mask updated
43 * 0.07: 14 Oct 2003: Further irq mask updates.
44 * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
45 * added into irq handler, NULL check for drain_ring.
46 * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
47 * requested interrupt sources.
48 * 0.10: 20 Oct 2003: First cleanup for release.
49 * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
50 * MAC Address init fix, set_multicast cleanup.
51 * 0.12: 23 Oct 2003: Cleanups for release.
52 * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
53 * Set link speed correctly. start rx before starting
54 * tx (nv_start_rx sets the link speed).
55 * 0.14: 25 Oct 2003: Nic dependant irq mask.
56 * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
57 * open.
58 * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
59 * increased to 1628 bytes.
60 * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
61 * the tx length.
62 * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
63 * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
64 * addresses, really stop rx if already running
65 * in nv_start_rx, clean up a bit.
66 * 0.20: 07 Dec 2003: alloc fixes
67 * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
68 * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
69 * on close.
70 * 0.23: 26 Jan 2004: various small cleanups
71 * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces
72 * 0.25: 09 Mar 2004: wol support
73 * 0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
74 * 0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
75 * added CK804/MCP04 device IDs, code fixes
76 * for registers, link status and other minor fixes.
77 * 0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
78 * 0.29: 31 Aug 2004: Add backup timer for link change notification.
79 * 0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
80 * into nv_close, otherwise reenabling for wol can
81 * cause DMA to kfree'd memory.
82 * 0.31: 14 Nov 2004: ethtool support for getting/setting link
83 * capabilities.
Manfred Spraul22c6d142005-04-19 21:17:09 +020084 * 0.32: 16 Apr 2005: RX_ERROR4 handling added.
Manfred Spraul8f767fc2005-06-18 16:27:19 +020085 * 0.33: 16 May 2005: Support for MCP51 added.
86 * 0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
Manfred Spraulf49d16e2005-06-26 11:36:52 +020087 * 0.35: 26 Jun 2005: Support for MCP55 added.
Manfred Sprauldc8216c2005-07-31 18:26:05 +020088 * 0.36: 28 Jun 2005: Add jumbo frame support.
89 * 0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
Manfred Spraulc2dba062005-07-31 18:29:47 +020090 * 0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
91 * per-packet flags.
Manfred Spraulee733622005-07-31 18:32:26 +020092 * 0.39: 18 Jul 2005: Add 64bit descriptor support.
Manfred Spraul72b31782005-07-31 18:33:34 +020093 * 0.40: 19 Jul 2005: Add support for mac address change.
Manfred Spraulb3df9f82005-07-31 18:38:58 +020094 * 0.41: 30 Jul 2005: Write back original MAC in nv_close instead
95 * of nv_remove
Manfred Spraul1b1b3c92005-08-06 23:47:55 +020096 * 0.42: 06 Aug 2005: Fix lack of link speed initialization
97 * in the second (and later) nv_open call
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -040098 * 0.43: 10 Aug 2005: Add support for tx checksum.
Linus Torvalds1da177e2005-04-16 15:20:36 -070099 *
100 * Known bugs:
101 * We suspect that on some hardware no TX done interrupts are generated.
102 * This means recovery from netif_stop_queue only happens if the hw timer
103 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
104 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
105 * If your hardware reliably generates tx done interrupts, then you can remove
106 * DEV_NEED_TIMERIRQ from the driver_data flags.
107 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
108 * superfluous timer interrupts from the nic.
109 */
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400110#define FORCEDETH_VERSION "0.43"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700111#define DRV_NAME "forcedeth"
112
113#include <linux/module.h>
114#include <linux/types.h>
115#include <linux/pci.h>
116#include <linux/interrupt.h>
117#include <linux/netdevice.h>
118#include <linux/etherdevice.h>
119#include <linux/delay.h>
120#include <linux/spinlock.h>
121#include <linux/ethtool.h>
122#include <linux/timer.h>
123#include <linux/skbuff.h>
124#include <linux/mii.h>
125#include <linux/random.h>
126#include <linux/init.h>
Manfred Spraul22c6d142005-04-19 21:17:09 +0200127#include <linux/if_vlan.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700128
129#include <asm/irq.h>
130#include <asm/io.h>
131#include <asm/uaccess.h>
132#include <asm/system.h>
133
134#if 0
135#define dprintk printk
136#else
137#define dprintk(x...) do { } while (0)
138#endif
139
140
141/*
142 * Hardware access:
143 */
144
Manfred Spraulc2dba062005-07-31 18:29:47 +0200145#define DEV_NEED_TIMERIRQ 0x0001 /* set the timer irq flag in the irq mask */
146#define DEV_NEED_LINKTIMER 0x0002 /* poll link settings. Relies on the timer irq */
147#define DEV_HAS_LARGEDESC 0x0004 /* device supports jumbo frames and needs packet format 2 */
Manfred Spraulee733622005-07-31 18:32:26 +0200148#define DEV_HAS_HIGH_DMA 0x0008 /* device supports 64bit dma */
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400149#define DEV_HAS_CHECKSUM 0x0010 /* device supports tx and rx checksum offloads */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700150
151enum {
152 NvRegIrqStatus = 0x000,
153#define NVREG_IRQSTAT_MIIEVENT 0x040
154#define NVREG_IRQSTAT_MASK 0x1ff
155 NvRegIrqMask = 0x004,
156#define NVREG_IRQ_RX_ERROR 0x0001
157#define NVREG_IRQ_RX 0x0002
158#define NVREG_IRQ_RX_NOBUF 0x0004
159#define NVREG_IRQ_TX_ERR 0x0008
Manfred Spraulc2dba062005-07-31 18:29:47 +0200160#define NVREG_IRQ_TX_OK 0x0010
Linus Torvalds1da177e2005-04-16 15:20:36 -0700161#define NVREG_IRQ_TIMER 0x0020
162#define NVREG_IRQ_LINK 0x0040
Manfred Spraulc2dba062005-07-31 18:29:47 +0200163#define NVREG_IRQ_TX_ERROR 0x0080
Linus Torvalds1da177e2005-04-16 15:20:36 -0700164#define NVREG_IRQ_TX1 0x0100
Manfred Spraulc2dba062005-07-31 18:29:47 +0200165#define NVREG_IRQMASK_WANTED 0x00df
166
167#define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
168 NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_TX_ERROR| \
169 NVREG_IRQ_TX1))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700170
171 NvRegUnknownSetupReg6 = 0x008,
172#define NVREG_UNKSETUP6_VAL 3
173
174/*
175 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
176 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
177 */
178 NvRegPollingInterval = 0x00c,
179#define NVREG_POLL_DEFAULT 970
180 NvRegMisc1 = 0x080,
181#define NVREG_MISC1_HD 0x02
182#define NVREG_MISC1_FORCE 0x3b0f3c
183
184 NvRegTransmitterControl = 0x084,
185#define NVREG_XMITCTL_START 0x01
186 NvRegTransmitterStatus = 0x088,
187#define NVREG_XMITSTAT_BUSY 0x01
188
189 NvRegPacketFilterFlags = 0x8c,
190#define NVREG_PFF_ALWAYS 0x7F0008
191#define NVREG_PFF_PROMISC 0x80
192#define NVREG_PFF_MYADDR 0x20
193
194 NvRegOffloadConfig = 0x90,
195#define NVREG_OFFLOAD_HOMEPHY 0x601
196#define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
197 NvRegReceiverControl = 0x094,
198#define NVREG_RCVCTL_START 0x01
199 NvRegReceiverStatus = 0x98,
200#define NVREG_RCVSTAT_BUSY 0x01
201
202 NvRegRandomSeed = 0x9c,
203#define NVREG_RNDSEED_MASK 0x00ff
204#define NVREG_RNDSEED_FORCE 0x7f00
205#define NVREG_RNDSEED_FORCE2 0x2d00
206#define NVREG_RNDSEED_FORCE3 0x7400
207
208 NvRegUnknownSetupReg1 = 0xA0,
209#define NVREG_UNKSETUP1_VAL 0x16070f
210 NvRegUnknownSetupReg2 = 0xA4,
211#define NVREG_UNKSETUP2_VAL 0x16
212 NvRegMacAddrA = 0xA8,
213 NvRegMacAddrB = 0xAC,
214 NvRegMulticastAddrA = 0xB0,
215#define NVREG_MCASTADDRA_FORCE 0x01
216 NvRegMulticastAddrB = 0xB4,
217 NvRegMulticastMaskA = 0xB8,
218 NvRegMulticastMaskB = 0xBC,
219
220 NvRegPhyInterface = 0xC0,
221#define PHY_RGMII 0x10000000
222
223 NvRegTxRingPhysAddr = 0x100,
224 NvRegRxRingPhysAddr = 0x104,
225 NvRegRingSizes = 0x108,
226#define NVREG_RINGSZ_TXSHIFT 0
227#define NVREG_RINGSZ_RXSHIFT 16
228 NvRegUnknownTransmitterReg = 0x10c,
229 NvRegLinkSpeed = 0x110,
230#define NVREG_LINKSPEED_FORCE 0x10000
231#define NVREG_LINKSPEED_10 1000
232#define NVREG_LINKSPEED_100 100
233#define NVREG_LINKSPEED_1000 50
234#define NVREG_LINKSPEED_MASK (0xFFF)
235 NvRegUnknownSetupReg5 = 0x130,
236#define NVREG_UNKSETUP5_BIT31 (1<<31)
237 NvRegUnknownSetupReg3 = 0x13c,
238#define NVREG_UNKSETUP3_VAL1 0x200010
239 NvRegTxRxControl = 0x144,
240#define NVREG_TXRXCTL_KICK 0x0001
241#define NVREG_TXRXCTL_BIT1 0x0002
242#define NVREG_TXRXCTL_BIT2 0x0004
243#define NVREG_TXRXCTL_IDLE 0x0008
244#define NVREG_TXRXCTL_RESET 0x0010
245#define NVREG_TXRXCTL_RXCHECK 0x0400
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400246#define NVREG_TXRXCTL_DESC_1 0
247#define NVREG_TXRXCTL_DESC_2 0x02100
248#define NVREG_TXRXCTL_DESC_3 0x02200
Linus Torvalds1da177e2005-04-16 15:20:36 -0700249 NvRegMIIStatus = 0x180,
250#define NVREG_MIISTAT_ERROR 0x0001
251#define NVREG_MIISTAT_LINKCHANGE 0x0008
252#define NVREG_MIISTAT_MASK 0x000f
253#define NVREG_MIISTAT_MASK2 0x000f
254 NvRegUnknownSetupReg4 = 0x184,
255#define NVREG_UNKSETUP4_VAL 8
256
257 NvRegAdapterControl = 0x188,
258#define NVREG_ADAPTCTL_START 0x02
259#define NVREG_ADAPTCTL_LINKUP 0x04
260#define NVREG_ADAPTCTL_PHYVALID 0x40000
261#define NVREG_ADAPTCTL_RUNNING 0x100000
262#define NVREG_ADAPTCTL_PHYSHIFT 24
263 NvRegMIISpeed = 0x18c,
264#define NVREG_MIISPEED_BIT8 (1<<8)
265#define NVREG_MIIDELAY 5
266 NvRegMIIControl = 0x190,
267#define NVREG_MIICTL_INUSE 0x08000
268#define NVREG_MIICTL_WRITE 0x00400
269#define NVREG_MIICTL_ADDRSHIFT 5
270 NvRegMIIData = 0x194,
271 NvRegWakeUpFlags = 0x200,
272#define NVREG_WAKEUPFLAGS_VAL 0x7770
273#define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
274#define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
275#define NVREG_WAKEUPFLAGS_D3SHIFT 12
276#define NVREG_WAKEUPFLAGS_D2SHIFT 8
277#define NVREG_WAKEUPFLAGS_D1SHIFT 4
278#define NVREG_WAKEUPFLAGS_D0SHIFT 0
279#define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
280#define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
281#define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
282#define NVREG_WAKEUPFLAGS_ENABLE 0x1111
283
284 NvRegPatternCRC = 0x204,
285 NvRegPatternMask = 0x208,
286 NvRegPowerCap = 0x268,
287#define NVREG_POWERCAP_D3SUPP (1<<30)
288#define NVREG_POWERCAP_D2SUPP (1<<26)
289#define NVREG_POWERCAP_D1SUPP (1<<25)
290 NvRegPowerState = 0x26c,
291#define NVREG_POWERSTATE_POWEREDUP 0x8000
292#define NVREG_POWERSTATE_VALID 0x0100
293#define NVREG_POWERSTATE_MASK 0x0003
294#define NVREG_POWERSTATE_D0 0x0000
295#define NVREG_POWERSTATE_D1 0x0001
296#define NVREG_POWERSTATE_D2 0x0002
297#define NVREG_POWERSTATE_D3 0x0003
298};
299
300/* Big endian: should work, but is untested */
301struct ring_desc {
302 u32 PacketBuffer;
303 u32 FlagLen;
304};
305
Manfred Spraulee733622005-07-31 18:32:26 +0200306struct ring_desc_ex {
307 u32 PacketBufferHigh;
308 u32 PacketBufferLow;
309 u32 Reserved;
310 u32 FlagLen;
311};
312
313typedef union _ring_type {
314 struct ring_desc* orig;
315 struct ring_desc_ex* ex;
316} ring_type;
317
Linus Torvalds1da177e2005-04-16 15:20:36 -0700318#define FLAG_MASK_V1 0xffff0000
319#define FLAG_MASK_V2 0xffffc000
320#define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
321#define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
322
323#define NV_TX_LASTPACKET (1<<16)
324#define NV_TX_RETRYERROR (1<<19)
Manfred Spraulc2dba062005-07-31 18:29:47 +0200325#define NV_TX_FORCED_INTERRUPT (1<<24)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700326#define NV_TX_DEFERRED (1<<26)
327#define NV_TX_CARRIERLOST (1<<27)
328#define NV_TX_LATECOLLISION (1<<28)
329#define NV_TX_UNDERFLOW (1<<29)
330#define NV_TX_ERROR (1<<30)
331#define NV_TX_VALID (1<<31)
332
333#define NV_TX2_LASTPACKET (1<<29)
334#define NV_TX2_RETRYERROR (1<<18)
Manfred Spraulc2dba062005-07-31 18:29:47 +0200335#define NV_TX2_FORCED_INTERRUPT (1<<30)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700336#define NV_TX2_DEFERRED (1<<25)
337#define NV_TX2_CARRIERLOST (1<<26)
338#define NV_TX2_LATECOLLISION (1<<27)
339#define NV_TX2_UNDERFLOW (1<<28)
340/* error and valid are the same for both */
341#define NV_TX2_ERROR (1<<30)
342#define NV_TX2_VALID (1<<31)
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400343#define NV_TX2_CHECKSUM_L3 (1<<27)
344#define NV_TX2_CHECKSUM_L4 (1<<26)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700345
346#define NV_RX_DESCRIPTORVALID (1<<16)
347#define NV_RX_MISSEDFRAME (1<<17)
348#define NV_RX_SUBSTRACT1 (1<<18)
349#define NV_RX_ERROR1 (1<<23)
350#define NV_RX_ERROR2 (1<<24)
351#define NV_RX_ERROR3 (1<<25)
352#define NV_RX_ERROR4 (1<<26)
353#define NV_RX_CRCERR (1<<27)
354#define NV_RX_OVERFLOW (1<<28)
355#define NV_RX_FRAMINGERR (1<<29)
356#define NV_RX_ERROR (1<<30)
357#define NV_RX_AVAIL (1<<31)
358
359#define NV_RX2_CHECKSUMMASK (0x1C000000)
360#define NV_RX2_CHECKSUMOK1 (0x10000000)
361#define NV_RX2_CHECKSUMOK2 (0x14000000)
362#define NV_RX2_CHECKSUMOK3 (0x18000000)
363#define NV_RX2_DESCRIPTORVALID (1<<29)
364#define NV_RX2_SUBSTRACT1 (1<<25)
365#define NV_RX2_ERROR1 (1<<18)
366#define NV_RX2_ERROR2 (1<<19)
367#define NV_RX2_ERROR3 (1<<20)
368#define NV_RX2_ERROR4 (1<<21)
369#define NV_RX2_CRCERR (1<<22)
370#define NV_RX2_OVERFLOW (1<<23)
371#define NV_RX2_FRAMINGERR (1<<24)
372/* error and avail are the same for both */
373#define NV_RX2_ERROR (1<<30)
374#define NV_RX2_AVAIL (1<<31)
375
376/* Miscelaneous hardware related defines: */
377#define NV_PCI_REGSZ 0x270
378
379/* various timeout delays: all in usec */
380#define NV_TXRX_RESET_DELAY 4
381#define NV_TXSTOP_DELAY1 10
382#define NV_TXSTOP_DELAY1MAX 500000
383#define NV_TXSTOP_DELAY2 100
384#define NV_RXSTOP_DELAY1 10
385#define NV_RXSTOP_DELAY1MAX 500000
386#define NV_RXSTOP_DELAY2 100
387#define NV_SETUP5_DELAY 5
388#define NV_SETUP5_DELAYMAX 50000
389#define NV_POWERUP_DELAY 5
390#define NV_POWERUP_DELAYMAX 5000
391#define NV_MIIBUSY_DELAY 50
392#define NV_MIIPHY_DELAY 10
393#define NV_MIIPHY_DELAYMAX 10000
394
395#define NV_WAKEUPPATTERNS 5
396#define NV_WAKEUPMASKENTRIES 4
397
398/* General driver defaults */
399#define NV_WATCHDOG_TIMEO (5*HZ)
400
401#define RX_RING 128
402#define TX_RING 64
403/*
404 * If your nic mysteriously hangs then try to reduce the limits
405 * to 1/0: It might be required to set NV_TX_LASTPACKET in the
406 * last valid ring entry. But this would be impossible to
407 * implement - probably a disassembly error.
408 */
409#define TX_LIMIT_STOP 63
410#define TX_LIMIT_START 62
411
412/* rx/tx mac addr + type + vlan + align + slack*/
Manfred Sprauld81c0982005-07-31 18:20:30 +0200413#define NV_RX_HEADERS (64)
414/* even more slack. */
415#define NV_RX_ALLOC_PAD (64)
416
417/* maximum mtu size */
418#define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
419#define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700420
421#define OOM_REFILL (1+HZ/20)
422#define POLL_WAIT (1+HZ/100)
423#define LINK_TIMEOUT (3*HZ)
424
425/*
426 * desc_ver values:
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400427 * The nic supports three different descriptor types:
428 * - DESC_VER_1: Original
429 * - DESC_VER_2: support for jumbo frames.
430 * - DESC_VER_3: 64-bit format.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700431 */
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400432#define DESC_VER_1 1
433#define DESC_VER_2 2
434#define DESC_VER_3 3
Linus Torvalds1da177e2005-04-16 15:20:36 -0700435
436/* PHY defines */
437#define PHY_OUI_MARVELL 0x5043
438#define PHY_OUI_CICADA 0x03f1
439#define PHYID1_OUI_MASK 0x03ff
440#define PHYID1_OUI_SHFT 6
441#define PHYID2_OUI_MASK 0xfc00
442#define PHYID2_OUI_SHFT 10
443#define PHY_INIT1 0x0f000
444#define PHY_INIT2 0x0e00
445#define PHY_INIT3 0x01000
446#define PHY_INIT4 0x0200
447#define PHY_INIT5 0x0004
448#define PHY_INIT6 0x02000
449#define PHY_GIGABIT 0x0100
450
451#define PHY_TIMEOUT 0x1
452#define PHY_ERROR 0x2
453
454#define PHY_100 0x1
455#define PHY_1000 0x2
456#define PHY_HALF 0x100
457
458/* FIXME: MII defines that should be added to <linux/mii.h> */
459#define MII_1000BT_CR 0x09
460#define MII_1000BT_SR 0x0a
461#define ADVERTISE_1000FULL 0x0200
462#define ADVERTISE_1000HALF 0x0100
463#define LPA_1000FULL 0x0800
464#define LPA_1000HALF 0x0400
465
466
467/*
468 * SMP locking:
469 * All hardware access under dev->priv->lock, except the performance
470 * critical parts:
471 * - rx is (pseudo-) lockless: it relies on the single-threading provided
472 * by the arch code for interrupts.
473 * - tx setup is lockless: it relies on dev->xmit_lock. Actual submission
474 * needs dev->priv->lock :-(
475 * - set_multicast_list: preparation lockless, relies on dev->xmit_lock.
476 */
477
478/* in dev: base, irq */
479struct fe_priv {
480 spinlock_t lock;
481
482 /* General data:
483 * Locking: spin_lock(&np->lock); */
484 struct net_device_stats stats;
485 int in_shutdown;
486 u32 linkspeed;
487 int duplex;
488 int autoneg;
489 int fixed_mode;
490 int phyaddr;
491 int wolenabled;
492 unsigned int phy_oui;
493 u16 gigabit;
494
495 /* General data: RO fields */
496 dma_addr_t ring_addr;
497 struct pci_dev *pci_dev;
498 u32 orig_mac[2];
499 u32 irqmask;
500 u32 desc_ver;
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400501 u32 txrxctl_bits;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700502
503 void __iomem *base;
504
505 /* rx specific fields.
506 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
507 */
Manfred Spraulee733622005-07-31 18:32:26 +0200508 ring_type rx_ring;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700509 unsigned int cur_rx, refill_rx;
510 struct sk_buff *rx_skbuff[RX_RING];
511 dma_addr_t rx_dma[RX_RING];
512 unsigned int rx_buf_sz;
Manfred Sprauld81c0982005-07-31 18:20:30 +0200513 unsigned int pkt_limit;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700514 struct timer_list oom_kick;
515 struct timer_list nic_poll;
516
517 /* media detection workaround.
518 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
519 */
520 int need_linktimer;
521 unsigned long link_timeout;
522 /*
523 * tx specific fields.
524 */
Manfred Spraulee733622005-07-31 18:32:26 +0200525 ring_type tx_ring;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700526 unsigned int next_tx, nic_tx;
527 struct sk_buff *tx_skbuff[TX_RING];
528 dma_addr_t tx_dma[TX_RING];
529 u32 tx_flags;
530};
531
532/*
533 * Maximum number of loops until we assume that a bit in the irq mask
534 * is stuck. Overridable with module param.
535 */
536static int max_interrupt_work = 5;
537
538static inline struct fe_priv *get_nvpriv(struct net_device *dev)
539{
540 return netdev_priv(dev);
541}
542
543static inline u8 __iomem *get_hwbase(struct net_device *dev)
544{
545 return get_nvpriv(dev)->base;
546}
547
548static inline void pci_push(u8 __iomem *base)
549{
550 /* force out pending posted writes */
551 readl(base);
552}
553
554static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
555{
556 return le32_to_cpu(prd->FlagLen)
557 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
558}
559
Manfred Spraulee733622005-07-31 18:32:26 +0200560static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
561{
562 return le32_to_cpu(prd->FlagLen) & LEN_MASK_V2;
563}
564
Linus Torvalds1da177e2005-04-16 15:20:36 -0700565static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
566 int delay, int delaymax, const char *msg)
567{
568 u8 __iomem *base = get_hwbase(dev);
569
570 pci_push(base);
571 do {
572 udelay(delay);
573 delaymax -= delay;
574 if (delaymax < 0) {
575 if (msg)
576 printk(msg);
577 return 1;
578 }
579 } while ((readl(base + offset) & mask) != target);
580 return 0;
581}
582
583#define MII_READ (-1)
584/* mii_rw: read/write a register on the PHY.
585 *
586 * Caller must guarantee serialization
587 */
588static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
589{
590 u8 __iomem *base = get_hwbase(dev);
591 u32 reg;
592 int retval;
593
594 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
595
596 reg = readl(base + NvRegMIIControl);
597 if (reg & NVREG_MIICTL_INUSE) {
598 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
599 udelay(NV_MIIBUSY_DELAY);
600 }
601
602 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
603 if (value != MII_READ) {
604 writel(value, base + NvRegMIIData);
605 reg |= NVREG_MIICTL_WRITE;
606 }
607 writel(reg, base + NvRegMIIControl);
608
609 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
610 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
611 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
612 dev->name, miireg, addr);
613 retval = -1;
614 } else if (value != MII_READ) {
615 /* it was a write operation - fewer failures are detectable */
616 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
617 dev->name, value, miireg, addr);
618 retval = 0;
619 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
620 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
621 dev->name, miireg, addr);
622 retval = -1;
623 } else {
624 retval = readl(base + NvRegMIIData);
625 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
626 dev->name, miireg, addr, retval);
627 }
628
629 return retval;
630}
631
632static int phy_reset(struct net_device *dev)
633{
634 struct fe_priv *np = get_nvpriv(dev);
635 u32 miicontrol;
636 unsigned int tries = 0;
637
638 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
639 miicontrol |= BMCR_RESET;
640 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
641 return -1;
642 }
643
644 /* wait for 500ms */
645 msleep(500);
646
647 /* must wait till reset is deasserted */
648 while (miicontrol & BMCR_RESET) {
649 msleep(10);
650 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
651 /* FIXME: 100 tries seem excessive */
652 if (tries++ > 100)
653 return -1;
654 }
655 return 0;
656}
657
658static int phy_init(struct net_device *dev)
659{
660 struct fe_priv *np = get_nvpriv(dev);
661 u8 __iomem *base = get_hwbase(dev);
662 u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
663
664 /* set advertise register */
665 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
666 reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|0x800|0x400);
667 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
668 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
669 return PHY_ERROR;
670 }
671
672 /* get phy interface type */
673 phyinterface = readl(base + NvRegPhyInterface);
674
675 /* see if gigabit phy */
676 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
677 if (mii_status & PHY_GIGABIT) {
678 np->gigabit = PHY_GIGABIT;
679 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
680 mii_control_1000 &= ~ADVERTISE_1000HALF;
681 if (phyinterface & PHY_RGMII)
682 mii_control_1000 |= ADVERTISE_1000FULL;
683 else
684 mii_control_1000 &= ~ADVERTISE_1000FULL;
685
686 if (mii_rw(dev, np->phyaddr, MII_1000BT_CR, mii_control_1000)) {
687 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
688 return PHY_ERROR;
689 }
690 }
691 else
692 np->gigabit = 0;
693
694 /* reset the phy */
695 if (phy_reset(dev)) {
696 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
697 return PHY_ERROR;
698 }
699
700 /* phy vendor specific configuration */
701 if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
702 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
703 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
704 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
705 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
706 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
707 return PHY_ERROR;
708 }
709 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
710 phy_reserved |= PHY_INIT5;
711 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
712 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
713 return PHY_ERROR;
714 }
715 }
716 if (np->phy_oui == PHY_OUI_CICADA) {
717 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
718 phy_reserved |= PHY_INIT6;
719 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
720 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
721 return PHY_ERROR;
722 }
723 }
724
725 /* restart auto negotiation */
726 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
727 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
728 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
729 return PHY_ERROR;
730 }
731
732 return 0;
733}
734
735static void nv_start_rx(struct net_device *dev)
736{
737 struct fe_priv *np = get_nvpriv(dev);
738 u8 __iomem *base = get_hwbase(dev);
739
740 dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
741 /* Already running? Stop it. */
742 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
743 writel(0, base + NvRegReceiverControl);
744 pci_push(base);
745 }
746 writel(np->linkspeed, base + NvRegLinkSpeed);
747 pci_push(base);
748 writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
749 dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
750 dev->name, np->duplex, np->linkspeed);
751 pci_push(base);
752}
753
754static void nv_stop_rx(struct net_device *dev)
755{
756 u8 __iomem *base = get_hwbase(dev);
757
758 dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
759 writel(0, base + NvRegReceiverControl);
760 reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
761 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
762 KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
763
764 udelay(NV_RXSTOP_DELAY2);
765 writel(0, base + NvRegLinkSpeed);
766}
767
768static void nv_start_tx(struct net_device *dev)
769{
770 u8 __iomem *base = get_hwbase(dev);
771
772 dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
773 writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
774 pci_push(base);
775}
776
777static void nv_stop_tx(struct net_device *dev)
778{
779 u8 __iomem *base = get_hwbase(dev);
780
781 dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
782 writel(0, base + NvRegTransmitterControl);
783 reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
784 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
785 KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
786
787 udelay(NV_TXSTOP_DELAY2);
788 writel(0, base + NvRegUnknownTransmitterReg);
789}
790
791static void nv_txrx_reset(struct net_device *dev)
792{
793 struct fe_priv *np = get_nvpriv(dev);
794 u8 __iomem *base = get_hwbase(dev);
795
796 dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400797 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700798 pci_push(base);
799 udelay(NV_TXRX_RESET_DELAY);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400800 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700801 pci_push(base);
802}
803
804/*
805 * nv_get_stats: dev->get_stats function
806 * Get latest stats value from the nic.
807 * Called with read_lock(&dev_base_lock) held for read -
808 * only synchronized against unregister_netdevice.
809 */
810static struct net_device_stats *nv_get_stats(struct net_device *dev)
811{
812 struct fe_priv *np = get_nvpriv(dev);
813
814 /* It seems that the nic always generates interrupts and doesn't
815 * accumulate errors internally. Thus the current values in np->stats
816 * are already up to date.
817 */
818 return &np->stats;
819}
820
821/*
822 * nv_alloc_rx: fill rx ring entries.
823 * Return 1 if the allocations for the skbs failed and the
824 * rx engine is without Available descriptors
825 */
826static int nv_alloc_rx(struct net_device *dev)
827{
828 struct fe_priv *np = get_nvpriv(dev);
829 unsigned int refill_rx = np->refill_rx;
830 int nr;
831
832 while (np->cur_rx != refill_rx) {
833 struct sk_buff *skb;
834
835 nr = refill_rx % RX_RING;
836 if (np->rx_skbuff[nr] == NULL) {
837
Manfred Sprauld81c0982005-07-31 18:20:30 +0200838 skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700839 if (!skb)
840 break;
841
842 skb->dev = dev;
843 np->rx_skbuff[nr] = skb;
844 } else {
845 skb = np->rx_skbuff[nr];
846 }
847 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data, skb->len,
848 PCI_DMA_FROMDEVICE);
Manfred Spraulee733622005-07-31 18:32:26 +0200849 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
850 np->rx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]);
851 wmb();
852 np->rx_ring.orig[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
853 } else {
854 np->rx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->rx_dma[nr]) >> 32;
855 np->rx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->rx_dma[nr]) & 0x0FFFFFFFF;
856 wmb();
857 np->rx_ring.ex[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
858 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700859 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
860 dev->name, refill_rx);
861 refill_rx++;
862 }
863 np->refill_rx = refill_rx;
864 if (np->cur_rx - refill_rx == RX_RING)
865 return 1;
866 return 0;
867}
868
869static void nv_do_rx_refill(unsigned long data)
870{
871 struct net_device *dev = (struct net_device *) data;
872 struct fe_priv *np = get_nvpriv(dev);
873
874 disable_irq(dev->irq);
875 if (nv_alloc_rx(dev)) {
876 spin_lock(&np->lock);
877 if (!np->in_shutdown)
878 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
879 spin_unlock(&np->lock);
880 }
881 enable_irq(dev->irq);
882}
883
Manfred Sprauld81c0982005-07-31 18:20:30 +0200884static void nv_init_rx(struct net_device *dev)
885{
886 struct fe_priv *np = get_nvpriv(dev);
887 int i;
888
889 np->cur_rx = RX_RING;
890 np->refill_rx = 0;
891 for (i = 0; i < RX_RING; i++)
Manfred Spraulee733622005-07-31 18:32:26 +0200892 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
893 np->rx_ring.orig[i].FlagLen = 0;
894 else
895 np->rx_ring.ex[i].FlagLen = 0;
Manfred Sprauld81c0982005-07-31 18:20:30 +0200896}
897
898static void nv_init_tx(struct net_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700899{
900 struct fe_priv *np = get_nvpriv(dev);
901 int i;
902
903 np->next_tx = np->nic_tx = 0;
904 for (i = 0; i < TX_RING; i++)
Manfred Spraulee733622005-07-31 18:32:26 +0200905 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
906 np->tx_ring.orig[i].FlagLen = 0;
907 else
908 np->tx_ring.ex[i].FlagLen = 0;
Manfred Sprauld81c0982005-07-31 18:20:30 +0200909}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700910
Manfred Sprauld81c0982005-07-31 18:20:30 +0200911static int nv_init_ring(struct net_device *dev)
912{
913 nv_init_tx(dev);
914 nv_init_rx(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700915 return nv_alloc_rx(dev);
916}
917
918static void nv_drain_tx(struct net_device *dev)
919{
920 struct fe_priv *np = get_nvpriv(dev);
921 int i;
922 for (i = 0; i < TX_RING; i++) {
Manfred Spraulee733622005-07-31 18:32:26 +0200923 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
924 np->tx_ring.orig[i].FlagLen = 0;
925 else
926 np->tx_ring.ex[i].FlagLen = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700927 if (np->tx_skbuff[i]) {
928 pci_unmap_single(np->pci_dev, np->tx_dma[i],
929 np->tx_skbuff[i]->len,
930 PCI_DMA_TODEVICE);
931 dev_kfree_skb(np->tx_skbuff[i]);
932 np->tx_skbuff[i] = NULL;
933 np->stats.tx_dropped++;
934 }
935 }
936}
937
938static void nv_drain_rx(struct net_device *dev)
939{
940 struct fe_priv *np = get_nvpriv(dev);
941 int i;
942 for (i = 0; i < RX_RING; i++) {
Manfred Spraulee733622005-07-31 18:32:26 +0200943 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
944 np->rx_ring.orig[i].FlagLen = 0;
945 else
946 np->rx_ring.ex[i].FlagLen = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700947 wmb();
948 if (np->rx_skbuff[i]) {
949 pci_unmap_single(np->pci_dev, np->rx_dma[i],
950 np->rx_skbuff[i]->len,
951 PCI_DMA_FROMDEVICE);
952 dev_kfree_skb(np->rx_skbuff[i]);
953 np->rx_skbuff[i] = NULL;
954 }
955 }
956}
957
958static void drain_ring(struct net_device *dev)
959{
960 nv_drain_tx(dev);
961 nv_drain_rx(dev);
962}
963
964/*
965 * nv_start_xmit: dev->hard_start_xmit function
966 * Called with dev->xmit_lock held.
967 */
968static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
969{
970 struct fe_priv *np = get_nvpriv(dev);
971 int nr = np->next_tx % TX_RING;
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400972 u32 tx_checksum = (skb->ip_summed == CHECKSUM_HW ? (NV_TX2_CHECKSUM_L3|NV_TX2_CHECKSUM_L4) : 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700973
974 np->tx_skbuff[nr] = skb;
975 np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data,skb->len,
976 PCI_DMA_TODEVICE);
977
Manfred Spraulee733622005-07-31 18:32:26 +0200978 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
979 np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
980 else {
981 np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
982 np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
983 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700984
985 spin_lock_irq(&np->lock);
986 wmb();
Manfred Spraulee733622005-07-31 18:32:26 +0200987 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400988 np->tx_ring.orig[nr].FlagLen = cpu_to_le32( (skb->len-1) | np->tx_flags | tx_checksum);
Manfred Spraulee733622005-07-31 18:32:26 +0200989 else
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400990 np->tx_ring.ex[nr].FlagLen = cpu_to_le32( (skb->len-1) | np->tx_flags | tx_checksum);
991 dprintk(KERN_DEBUG "%s: nv_start_xmit: packet packet %d queued for transmission\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700992 dev->name, np->next_tx);
993 {
994 int j;
995 for (j=0; j<64; j++) {
996 if ((j%16) == 0)
997 dprintk("\n%03x:", j);
998 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
999 }
1000 dprintk("\n");
1001 }
1002
1003 np->next_tx++;
1004
1005 dev->trans_start = jiffies;
1006 if (np->next_tx - np->nic_tx >= TX_LIMIT_STOP)
1007 netif_stop_queue(dev);
1008 spin_unlock_irq(&np->lock);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04001009 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001010 pci_push(get_hwbase(dev));
1011 return 0;
1012}
1013
1014/*
1015 * nv_tx_done: check for completed packets, release the skbs.
1016 *
1017 * Caller must own np->lock.
1018 */
1019static void nv_tx_done(struct net_device *dev)
1020{
1021 struct fe_priv *np = get_nvpriv(dev);
1022 u32 Flags;
1023 int i;
1024
1025 while (np->nic_tx != np->next_tx) {
1026 i = np->nic_tx % TX_RING;
1027
Manfred Spraulee733622005-07-31 18:32:26 +02001028 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1029 Flags = le32_to_cpu(np->tx_ring.orig[i].FlagLen);
1030 else
1031 Flags = le32_to_cpu(np->tx_ring.ex[i].FlagLen);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001032
1033 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n",
1034 dev->name, np->nic_tx, Flags);
1035 if (Flags & NV_TX_VALID)
1036 break;
1037 if (np->desc_ver == DESC_VER_1) {
1038 if (Flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
1039 NV_TX_UNDERFLOW|NV_TX_ERROR)) {
1040 if (Flags & NV_TX_UNDERFLOW)
1041 np->stats.tx_fifo_errors++;
1042 if (Flags & NV_TX_CARRIERLOST)
1043 np->stats.tx_carrier_errors++;
1044 np->stats.tx_errors++;
1045 } else {
1046 np->stats.tx_packets++;
1047 np->stats.tx_bytes += np->tx_skbuff[i]->len;
1048 }
1049 } else {
1050 if (Flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
1051 NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
1052 if (Flags & NV_TX2_UNDERFLOW)
1053 np->stats.tx_fifo_errors++;
1054 if (Flags & NV_TX2_CARRIERLOST)
1055 np->stats.tx_carrier_errors++;
1056 np->stats.tx_errors++;
1057 } else {
1058 np->stats.tx_packets++;
1059 np->stats.tx_bytes += np->tx_skbuff[i]->len;
1060 }
1061 }
1062 pci_unmap_single(np->pci_dev, np->tx_dma[i],
1063 np->tx_skbuff[i]->len,
1064 PCI_DMA_TODEVICE);
1065 dev_kfree_skb_irq(np->tx_skbuff[i]);
1066 np->tx_skbuff[i] = NULL;
1067 np->nic_tx++;
1068 }
1069 if (np->next_tx - np->nic_tx < TX_LIMIT_START)
1070 netif_wake_queue(dev);
1071}
1072
1073/*
1074 * nv_tx_timeout: dev->tx_timeout function
1075 * Called with dev->xmit_lock held.
1076 */
1077static void nv_tx_timeout(struct net_device *dev)
1078{
1079 struct fe_priv *np = get_nvpriv(dev);
1080 u8 __iomem *base = get_hwbase(dev);
1081
Manfred Spraulc2dba062005-07-31 18:29:47 +02001082 printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001083 readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK);
1084
Manfred Spraulc2dba062005-07-31 18:29:47 +02001085 {
1086 int i;
1087
1088 printk(KERN_INFO "%s: Ring at %lx: next %d nic %d\n",
1089 dev->name, (unsigned long)np->ring_addr,
1090 np->next_tx, np->nic_tx);
1091 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
1092 for (i=0;i<0x400;i+= 32) {
1093 printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1094 i,
1095 readl(base + i + 0), readl(base + i + 4),
1096 readl(base + i + 8), readl(base + i + 12),
1097 readl(base + i + 16), readl(base + i + 20),
1098 readl(base + i + 24), readl(base + i + 28));
1099 }
1100 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
1101 for (i=0;i<TX_RING;i+= 4) {
Manfred Spraulee733622005-07-31 18:32:26 +02001102 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1103 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1104 i,
1105 le32_to_cpu(np->tx_ring.orig[i].PacketBuffer),
1106 le32_to_cpu(np->tx_ring.orig[i].FlagLen),
1107 le32_to_cpu(np->tx_ring.orig[i+1].PacketBuffer),
1108 le32_to_cpu(np->tx_ring.orig[i+1].FlagLen),
1109 le32_to_cpu(np->tx_ring.orig[i+2].PacketBuffer),
1110 le32_to_cpu(np->tx_ring.orig[i+2].FlagLen),
1111 le32_to_cpu(np->tx_ring.orig[i+3].PacketBuffer),
1112 le32_to_cpu(np->tx_ring.orig[i+3].FlagLen));
1113 } else {
1114 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
1115 i,
1116 le32_to_cpu(np->tx_ring.ex[i].PacketBufferHigh),
1117 le32_to_cpu(np->tx_ring.ex[i].PacketBufferLow),
1118 le32_to_cpu(np->tx_ring.ex[i].FlagLen),
1119 le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferHigh),
1120 le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferLow),
1121 le32_to_cpu(np->tx_ring.ex[i+1].FlagLen),
1122 le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferHigh),
1123 le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferLow),
1124 le32_to_cpu(np->tx_ring.ex[i+2].FlagLen),
1125 le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferHigh),
1126 le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferLow),
1127 le32_to_cpu(np->tx_ring.ex[i+3].FlagLen));
1128 }
Manfred Spraulc2dba062005-07-31 18:29:47 +02001129 }
1130 }
1131
Linus Torvalds1da177e2005-04-16 15:20:36 -07001132 spin_lock_irq(&np->lock);
1133
1134 /* 1) stop tx engine */
1135 nv_stop_tx(dev);
1136
1137 /* 2) check that the packets were not sent already: */
1138 nv_tx_done(dev);
1139
1140 /* 3) if there are dead entries: clear everything */
1141 if (np->next_tx != np->nic_tx) {
1142 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1143 nv_drain_tx(dev);
1144 np->next_tx = np->nic_tx = 0;
Manfred Spraulee733622005-07-31 18:32:26 +02001145 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1146 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1147 else
1148 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001149 netif_wake_queue(dev);
1150 }
1151
1152 /* 4) restart tx engine */
1153 nv_start_tx(dev);
1154 spin_unlock_irq(&np->lock);
1155}
1156
Manfred Spraul22c6d142005-04-19 21:17:09 +02001157/*
1158 * Called when the nic notices a mismatch between the actual data len on the
1159 * wire and the len indicated in the 802 header
1160 */
1161static int nv_getlen(struct net_device *dev, void *packet, int datalen)
1162{
1163 int hdrlen; /* length of the 802 header */
1164 int protolen; /* length as stored in the proto field */
1165
1166 /* 1) calculate len according to header */
1167 if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == __constant_htons(ETH_P_8021Q)) {
1168 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
1169 hdrlen = VLAN_HLEN;
1170 } else {
1171 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
1172 hdrlen = ETH_HLEN;
1173 }
1174 dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1175 dev->name, datalen, protolen, hdrlen);
1176 if (protolen > ETH_DATA_LEN)
1177 return datalen; /* Value in proto field not a len, no checks possible */
1178
1179 protolen += hdrlen;
1180 /* consistency checks: */
1181 if (datalen > ETH_ZLEN) {
1182 if (datalen >= protolen) {
1183 /* more data on wire than in 802 header, trim of
1184 * additional data.
1185 */
1186 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1187 dev->name, protolen);
1188 return protolen;
1189 } else {
1190 /* less data on wire than mentioned in header.
1191 * Discard the packet.
1192 */
1193 dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
1194 dev->name);
1195 return -1;
1196 }
1197 } else {
1198 /* short packet. Accept only if 802 values are also short */
1199 if (protolen > ETH_ZLEN) {
1200 dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
1201 dev->name);
1202 return -1;
1203 }
1204 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1205 dev->name, datalen);
1206 return datalen;
1207 }
1208}
1209
Linus Torvalds1da177e2005-04-16 15:20:36 -07001210static void nv_rx_process(struct net_device *dev)
1211{
1212 struct fe_priv *np = get_nvpriv(dev);
1213 u32 Flags;
1214
1215 for (;;) {
1216 struct sk_buff *skb;
1217 int len;
1218 int i;
1219 if (np->cur_rx - np->refill_rx >= RX_RING)
1220 break; /* we scanned the whole ring - do not continue */
1221
1222 i = np->cur_rx % RX_RING;
Manfred Spraulee733622005-07-31 18:32:26 +02001223 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1224 Flags = le32_to_cpu(np->rx_ring.orig[i].FlagLen);
1225 len = nv_descr_getlength(&np->rx_ring.orig[i], np->desc_ver);
1226 } else {
1227 Flags = le32_to_cpu(np->rx_ring.ex[i].FlagLen);
1228 len = nv_descr_getlength_ex(&np->rx_ring.ex[i], np->desc_ver);
1229 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001230
1231 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n",
1232 dev->name, np->cur_rx, Flags);
1233
1234 if (Flags & NV_RX_AVAIL)
1235 break; /* still owned by hardware, */
1236
1237 /*
1238 * the packet is for us - immediately tear down the pci mapping.
1239 * TODO: check if a prefetch of the first cacheline improves
1240 * the performance.
1241 */
1242 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1243 np->rx_skbuff[i]->len,
1244 PCI_DMA_FROMDEVICE);
1245
1246 {
1247 int j;
1248 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",Flags);
1249 for (j=0; j<64; j++) {
1250 if ((j%16) == 0)
1251 dprintk("\n%03x:", j);
1252 dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]);
1253 }
1254 dprintk("\n");
1255 }
1256 /* look at what we actually got: */
1257 if (np->desc_ver == DESC_VER_1) {
1258 if (!(Flags & NV_RX_DESCRIPTORVALID))
1259 goto next_pkt;
1260
1261 if (Flags & NV_RX_MISSEDFRAME) {
1262 np->stats.rx_missed_errors++;
1263 np->stats.rx_errors++;
1264 goto next_pkt;
1265 }
Manfred Spraul22c6d142005-04-19 21:17:09 +02001266 if (Flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001267 np->stats.rx_errors++;
1268 goto next_pkt;
1269 }
1270 if (Flags & NV_RX_CRCERR) {
1271 np->stats.rx_crc_errors++;
1272 np->stats.rx_errors++;
1273 goto next_pkt;
1274 }
1275 if (Flags & NV_RX_OVERFLOW) {
1276 np->stats.rx_over_errors++;
1277 np->stats.rx_errors++;
1278 goto next_pkt;
1279 }
Manfred Spraul22c6d142005-04-19 21:17:09 +02001280 if (Flags & NV_RX_ERROR4) {
1281 len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1282 if (len < 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001283 np->stats.rx_errors++;
1284 goto next_pkt;
1285 }
1286 }
Manfred Spraul22c6d142005-04-19 21:17:09 +02001287 /* framing errors are soft errors. */
1288 if (Flags & NV_RX_FRAMINGERR) {
1289 if (Flags & NV_RX_SUBSTRACT1) {
1290 len--;
1291 }
1292 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001293 } else {
1294 if (!(Flags & NV_RX2_DESCRIPTORVALID))
1295 goto next_pkt;
1296
Manfred Spraul22c6d142005-04-19 21:17:09 +02001297 if (Flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001298 np->stats.rx_errors++;
1299 goto next_pkt;
1300 }
1301 if (Flags & NV_RX2_CRCERR) {
1302 np->stats.rx_crc_errors++;
1303 np->stats.rx_errors++;
1304 goto next_pkt;
1305 }
1306 if (Flags & NV_RX2_OVERFLOW) {
1307 np->stats.rx_over_errors++;
1308 np->stats.rx_errors++;
1309 goto next_pkt;
1310 }
Manfred Spraul22c6d142005-04-19 21:17:09 +02001311 if (Flags & NV_RX2_ERROR4) {
1312 len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1313 if (len < 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001314 np->stats.rx_errors++;
1315 goto next_pkt;
1316 }
1317 }
Manfred Spraul22c6d142005-04-19 21:17:09 +02001318 /* framing errors are soft errors */
1319 if (Flags & NV_RX2_FRAMINGERR) {
1320 if (Flags & NV_RX2_SUBSTRACT1) {
1321 len--;
1322 }
1323 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001324 Flags &= NV_RX2_CHECKSUMMASK;
1325 if (Flags == NV_RX2_CHECKSUMOK1 ||
1326 Flags == NV_RX2_CHECKSUMOK2 ||
1327 Flags == NV_RX2_CHECKSUMOK3) {
1328 dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
1329 np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY;
1330 } else {
1331 dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
1332 }
1333 }
1334 /* got a valid packet - forward it to the network core */
1335 skb = np->rx_skbuff[i];
1336 np->rx_skbuff[i] = NULL;
1337
1338 skb_put(skb, len);
1339 skb->protocol = eth_type_trans(skb, dev);
1340 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1341 dev->name, np->cur_rx, len, skb->protocol);
1342 netif_rx(skb);
1343 dev->last_rx = jiffies;
1344 np->stats.rx_packets++;
1345 np->stats.rx_bytes += len;
1346next_pkt:
1347 np->cur_rx++;
1348 }
1349}
1350
Manfred Sprauld81c0982005-07-31 18:20:30 +02001351static void set_bufsize(struct net_device *dev)
1352{
1353 struct fe_priv *np = netdev_priv(dev);
1354
1355 if (dev->mtu <= ETH_DATA_LEN)
1356 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
1357 else
1358 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
1359}
1360
Linus Torvalds1da177e2005-04-16 15:20:36 -07001361/*
1362 * nv_change_mtu: dev->change_mtu function
1363 * Called with dev_base_lock held for read.
1364 */
1365static int nv_change_mtu(struct net_device *dev, int new_mtu)
1366{
Manfred Sprauld81c0982005-07-31 18:20:30 +02001367 struct fe_priv *np = get_nvpriv(dev);
1368 int old_mtu;
1369
1370 if (new_mtu < 64 || new_mtu > np->pkt_limit)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001371 return -EINVAL;
Manfred Sprauld81c0982005-07-31 18:20:30 +02001372
1373 old_mtu = dev->mtu;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001374 dev->mtu = new_mtu;
Manfred Sprauld81c0982005-07-31 18:20:30 +02001375
1376 /* return early if the buffer sizes will not change */
1377 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1378 return 0;
1379 if (old_mtu == new_mtu)
1380 return 0;
1381
1382 /* synchronized against open : rtnl_lock() held by caller */
1383 if (netif_running(dev)) {
viro@ftp.linux.org.uk25097d42005-09-06 01:36:58 +01001384 u8 __iomem *base = get_hwbase(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02001385 /*
1386 * It seems that the nic preloads valid ring entries into an
1387 * internal buffer. The procedure for flushing everything is
1388 * guessed, there is probably a simpler approach.
1389 * Changing the MTU is a rare event, it shouldn't matter.
1390 */
1391 disable_irq(dev->irq);
1392 spin_lock_bh(&dev->xmit_lock);
1393 spin_lock(&np->lock);
1394 /* stop engines */
1395 nv_stop_rx(dev);
1396 nv_stop_tx(dev);
1397 nv_txrx_reset(dev);
1398 /* drain rx queue */
1399 nv_drain_rx(dev);
1400 nv_drain_tx(dev);
1401 /* reinit driver view of the rx queue */
1402 nv_init_rx(dev);
1403 nv_init_tx(dev);
1404 /* alloc new rx buffers */
1405 set_bufsize(dev);
1406 if (nv_alloc_rx(dev)) {
1407 if (!np->in_shutdown)
1408 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1409 }
1410 /* reinit nic view of the rx queue */
1411 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
1412 writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
Manfred Spraulee733622005-07-31 18:32:26 +02001413 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1414 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1415 else
1416 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
Manfred Sprauld81c0982005-07-31 18:20:30 +02001417 writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
1418 base + NvRegRingSizes);
1419 pci_push(base);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04001420 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
Manfred Sprauld81c0982005-07-31 18:20:30 +02001421 pci_push(base);
1422
1423 /* restart rx engine */
1424 nv_start_rx(dev);
1425 nv_start_tx(dev);
1426 spin_unlock(&np->lock);
1427 spin_unlock_bh(&dev->xmit_lock);
1428 enable_irq(dev->irq);
1429 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001430 return 0;
1431}
1432
Manfred Spraul72b31782005-07-31 18:33:34 +02001433static void nv_copy_mac_to_hw(struct net_device *dev)
1434{
viro@ftp.linux.org.uk25097d42005-09-06 01:36:58 +01001435 u8 __iomem *base = get_hwbase(dev);
Manfred Spraul72b31782005-07-31 18:33:34 +02001436 u32 mac[2];
1437
1438 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
1439 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
1440 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
1441
1442 writel(mac[0], base + NvRegMacAddrA);
1443 writel(mac[1], base + NvRegMacAddrB);
1444}
1445
1446/*
1447 * nv_set_mac_address: dev->set_mac_address function
1448 * Called with rtnl_lock() held.
1449 */
1450static int nv_set_mac_address(struct net_device *dev, void *addr)
1451{
1452 struct fe_priv *np = get_nvpriv(dev);
1453 struct sockaddr *macaddr = (struct sockaddr*)addr;
1454
1455 if(!is_valid_ether_addr(macaddr->sa_data))
1456 return -EADDRNOTAVAIL;
1457
1458 /* synchronized against open : rtnl_lock() held by caller */
1459 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
1460
1461 if (netif_running(dev)) {
1462 spin_lock_bh(&dev->xmit_lock);
1463 spin_lock_irq(&np->lock);
1464
1465 /* stop rx engine */
1466 nv_stop_rx(dev);
1467
1468 /* set mac address */
1469 nv_copy_mac_to_hw(dev);
1470
1471 /* restart rx engine */
1472 nv_start_rx(dev);
1473 spin_unlock_irq(&np->lock);
1474 spin_unlock_bh(&dev->xmit_lock);
1475 } else {
1476 nv_copy_mac_to_hw(dev);
1477 }
1478 return 0;
1479}
1480
Linus Torvalds1da177e2005-04-16 15:20:36 -07001481/*
1482 * nv_set_multicast: dev->set_multicast function
1483 * Called with dev->xmit_lock held.
1484 */
1485static void nv_set_multicast(struct net_device *dev)
1486{
1487 struct fe_priv *np = get_nvpriv(dev);
1488 u8 __iomem *base = get_hwbase(dev);
1489 u32 addr[2];
1490 u32 mask[2];
1491 u32 pff;
1492
1493 memset(addr, 0, sizeof(addr));
1494 memset(mask, 0, sizeof(mask));
1495
1496 if (dev->flags & IFF_PROMISC) {
1497 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
1498 pff = NVREG_PFF_PROMISC;
1499 } else {
1500 pff = NVREG_PFF_MYADDR;
1501
1502 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
1503 u32 alwaysOff[2];
1504 u32 alwaysOn[2];
1505
1506 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
1507 if (dev->flags & IFF_ALLMULTI) {
1508 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
1509 } else {
1510 struct dev_mc_list *walk;
1511
1512 walk = dev->mc_list;
1513 while (walk != NULL) {
1514 u32 a, b;
1515 a = le32_to_cpu(*(u32 *) walk->dmi_addr);
1516 b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
1517 alwaysOn[0] &= a;
1518 alwaysOff[0] &= ~a;
1519 alwaysOn[1] &= b;
1520 alwaysOff[1] &= ~b;
1521 walk = walk->next;
1522 }
1523 }
1524 addr[0] = alwaysOn[0];
1525 addr[1] = alwaysOn[1];
1526 mask[0] = alwaysOn[0] | alwaysOff[0];
1527 mask[1] = alwaysOn[1] | alwaysOff[1];
1528 }
1529 }
1530 addr[0] |= NVREG_MCASTADDRA_FORCE;
1531 pff |= NVREG_PFF_ALWAYS;
1532 spin_lock_irq(&np->lock);
1533 nv_stop_rx(dev);
1534 writel(addr[0], base + NvRegMulticastAddrA);
1535 writel(addr[1], base + NvRegMulticastAddrB);
1536 writel(mask[0], base + NvRegMulticastMaskA);
1537 writel(mask[1], base + NvRegMulticastMaskB);
1538 writel(pff, base + NvRegPacketFilterFlags);
1539 dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
1540 dev->name);
1541 nv_start_rx(dev);
1542 spin_unlock_irq(&np->lock);
1543}
1544
1545static int nv_update_linkspeed(struct net_device *dev)
1546{
1547 struct fe_priv *np = get_nvpriv(dev);
1548 u8 __iomem *base = get_hwbase(dev);
1549 int adv, lpa;
1550 int newls = np->linkspeed;
1551 int newdup = np->duplex;
1552 int mii_status;
1553 int retval = 0;
1554 u32 control_1000, status_1000, phyreg;
1555
1556 /* BMSR_LSTATUS is latched, read it twice:
1557 * we want the current value.
1558 */
1559 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1560 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1561
1562 if (!(mii_status & BMSR_LSTATUS)) {
1563 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
1564 dev->name);
1565 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1566 newdup = 0;
1567 retval = 0;
1568 goto set_speed;
1569 }
1570
1571 if (np->autoneg == 0) {
1572 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
1573 dev->name, np->fixed_mode);
1574 if (np->fixed_mode & LPA_100FULL) {
1575 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1576 newdup = 1;
1577 } else if (np->fixed_mode & LPA_100HALF) {
1578 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1579 newdup = 0;
1580 } else if (np->fixed_mode & LPA_10FULL) {
1581 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1582 newdup = 1;
1583 } else {
1584 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1585 newdup = 0;
1586 }
1587 retval = 1;
1588 goto set_speed;
1589 }
1590 /* check auto negotiation is complete */
1591 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
1592 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
1593 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1594 newdup = 0;
1595 retval = 0;
1596 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
1597 goto set_speed;
1598 }
1599
1600 retval = 1;
1601 if (np->gigabit == PHY_GIGABIT) {
1602 control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1603 status_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_SR, MII_READ);
1604
1605 if ((control_1000 & ADVERTISE_1000FULL) &&
1606 (status_1000 & LPA_1000FULL)) {
1607 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
1608 dev->name);
1609 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
1610 newdup = 1;
1611 goto set_speed;
1612 }
1613 }
1614
1615 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1616 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
1617 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
1618 dev->name, adv, lpa);
1619
1620 /* FIXME: handle parallel detection properly */
1621 lpa = lpa & adv;
1622 if (lpa & LPA_100FULL) {
1623 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1624 newdup = 1;
1625 } else if (lpa & LPA_100HALF) {
1626 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1627 newdup = 0;
1628 } else if (lpa & LPA_10FULL) {
1629 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1630 newdup = 1;
1631 } else if (lpa & LPA_10HALF) {
1632 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1633 newdup = 0;
1634 } else {
1635 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, lpa);
1636 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1637 newdup = 0;
1638 }
1639
1640set_speed:
1641 if (np->duplex == newdup && np->linkspeed == newls)
1642 return retval;
1643
1644 dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
1645 dev->name, np->linkspeed, np->duplex, newls, newdup);
1646
1647 np->duplex = newdup;
1648 np->linkspeed = newls;
1649
1650 if (np->gigabit == PHY_GIGABIT) {
1651 phyreg = readl(base + NvRegRandomSeed);
1652 phyreg &= ~(0x3FF00);
1653 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
1654 phyreg |= NVREG_RNDSEED_FORCE3;
1655 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
1656 phyreg |= NVREG_RNDSEED_FORCE2;
1657 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
1658 phyreg |= NVREG_RNDSEED_FORCE;
1659 writel(phyreg, base + NvRegRandomSeed);
1660 }
1661
1662 phyreg = readl(base + NvRegPhyInterface);
1663 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
1664 if (np->duplex == 0)
1665 phyreg |= PHY_HALF;
1666 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
1667 phyreg |= PHY_100;
1668 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
1669 phyreg |= PHY_1000;
1670 writel(phyreg, base + NvRegPhyInterface);
1671
1672 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
1673 base + NvRegMisc1);
1674 pci_push(base);
1675 writel(np->linkspeed, base + NvRegLinkSpeed);
1676 pci_push(base);
1677
1678 return retval;
1679}
1680
1681static void nv_linkchange(struct net_device *dev)
1682{
1683 if (nv_update_linkspeed(dev)) {
1684 if (netif_carrier_ok(dev)) {
1685 nv_stop_rx(dev);
1686 } else {
1687 netif_carrier_on(dev);
1688 printk(KERN_INFO "%s: link up.\n", dev->name);
1689 }
1690 nv_start_rx(dev);
1691 } else {
1692 if (netif_carrier_ok(dev)) {
1693 netif_carrier_off(dev);
1694 printk(KERN_INFO "%s: link down.\n", dev->name);
1695 nv_stop_rx(dev);
1696 }
1697 }
1698}
1699
1700static void nv_link_irq(struct net_device *dev)
1701{
1702 u8 __iomem *base = get_hwbase(dev);
1703 u32 miistat;
1704
1705 miistat = readl(base + NvRegMIIStatus);
1706 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1707 dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
1708
1709 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
1710 nv_linkchange(dev);
1711 dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
1712}
1713
1714static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs)
1715{
1716 struct net_device *dev = (struct net_device *) data;
1717 struct fe_priv *np = get_nvpriv(dev);
1718 u8 __iomem *base = get_hwbase(dev);
1719 u32 events;
1720 int i;
1721
1722 dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
1723
1724 for (i=0; ; i++) {
1725 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1726 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1727 pci_push(base);
1728 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
1729 if (!(events & np->irqmask))
1730 break;
1731
Manfred Spraulc2dba062005-07-31 18:29:47 +02001732 if (events & (NVREG_IRQ_TX1|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_ERROR|NVREG_IRQ_TX_ERR)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001733 spin_lock(&np->lock);
1734 nv_tx_done(dev);
1735 spin_unlock(&np->lock);
1736 }
1737
1738 if (events & (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF)) {
1739 nv_rx_process(dev);
1740 if (nv_alloc_rx(dev)) {
1741 spin_lock(&np->lock);
1742 if (!np->in_shutdown)
1743 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1744 spin_unlock(&np->lock);
1745 }
1746 }
1747
1748 if (events & NVREG_IRQ_LINK) {
1749 spin_lock(&np->lock);
1750 nv_link_irq(dev);
1751 spin_unlock(&np->lock);
1752 }
1753 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
1754 spin_lock(&np->lock);
1755 nv_linkchange(dev);
1756 spin_unlock(&np->lock);
1757 np->link_timeout = jiffies + LINK_TIMEOUT;
1758 }
1759 if (events & (NVREG_IRQ_TX_ERR)) {
1760 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
1761 dev->name, events);
1762 }
1763 if (events & (NVREG_IRQ_UNKNOWN)) {
1764 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
1765 dev->name, events);
1766 }
1767 if (i > max_interrupt_work) {
1768 spin_lock(&np->lock);
1769 /* disable interrupts on the nic */
1770 writel(0, base + NvRegIrqMask);
1771 pci_push(base);
1772
1773 if (!np->in_shutdown)
1774 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
1775 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
1776 spin_unlock(&np->lock);
1777 break;
1778 }
1779
1780 }
1781 dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
1782
1783 return IRQ_RETVAL(i);
1784}
1785
1786static void nv_do_nic_poll(unsigned long data)
1787{
1788 struct net_device *dev = (struct net_device *) data;
1789 struct fe_priv *np = get_nvpriv(dev);
1790 u8 __iomem *base = get_hwbase(dev);
1791
1792 disable_irq(dev->irq);
1793 /* FIXME: Do we need synchronize_irq(dev->irq) here? */
1794 /*
1795 * reenable interrupts on the nic, we have to do this before calling
1796 * nv_nic_irq because that may decide to do otherwise
1797 */
1798 writel(np->irqmask, base + NvRegIrqMask);
1799 pci_push(base);
1800 nv_nic_irq((int) 0, (void *) data, (struct pt_regs *) NULL);
1801 enable_irq(dev->irq);
1802}
1803
Michal Schmidt2918c352005-05-12 19:42:06 -04001804#ifdef CONFIG_NET_POLL_CONTROLLER
1805static void nv_poll_controller(struct net_device *dev)
1806{
1807 nv_do_nic_poll((unsigned long) dev);
1808}
1809#endif
1810
Linus Torvalds1da177e2005-04-16 15:20:36 -07001811static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1812{
1813 struct fe_priv *np = get_nvpriv(dev);
1814 strcpy(info->driver, "forcedeth");
1815 strcpy(info->version, FORCEDETH_VERSION);
1816 strcpy(info->bus_info, pci_name(np->pci_dev));
1817}
1818
1819static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
1820{
1821 struct fe_priv *np = get_nvpriv(dev);
1822 wolinfo->supported = WAKE_MAGIC;
1823
1824 spin_lock_irq(&np->lock);
1825 if (np->wolenabled)
1826 wolinfo->wolopts = WAKE_MAGIC;
1827 spin_unlock_irq(&np->lock);
1828}
1829
1830static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
1831{
1832 struct fe_priv *np = get_nvpriv(dev);
1833 u8 __iomem *base = get_hwbase(dev);
1834
1835 spin_lock_irq(&np->lock);
1836 if (wolinfo->wolopts == 0) {
1837 writel(0, base + NvRegWakeUpFlags);
1838 np->wolenabled = 0;
1839 }
1840 if (wolinfo->wolopts & WAKE_MAGIC) {
1841 writel(NVREG_WAKEUPFLAGS_ENABLE, base + NvRegWakeUpFlags);
1842 np->wolenabled = 1;
1843 }
1844 spin_unlock_irq(&np->lock);
1845 return 0;
1846}
1847
1848static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1849{
1850 struct fe_priv *np = netdev_priv(dev);
1851 int adv;
1852
1853 spin_lock_irq(&np->lock);
1854 ecmd->port = PORT_MII;
1855 if (!netif_running(dev)) {
1856 /* We do not track link speed / duplex setting if the
1857 * interface is disabled. Force a link check */
1858 nv_update_linkspeed(dev);
1859 }
1860 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
1861 case NVREG_LINKSPEED_10:
1862 ecmd->speed = SPEED_10;
1863 break;
1864 case NVREG_LINKSPEED_100:
1865 ecmd->speed = SPEED_100;
1866 break;
1867 case NVREG_LINKSPEED_1000:
1868 ecmd->speed = SPEED_1000;
1869 break;
1870 }
1871 ecmd->duplex = DUPLEX_HALF;
1872 if (np->duplex)
1873 ecmd->duplex = DUPLEX_FULL;
1874
1875 ecmd->autoneg = np->autoneg;
1876
1877 ecmd->advertising = ADVERTISED_MII;
1878 if (np->autoneg) {
1879 ecmd->advertising |= ADVERTISED_Autoneg;
1880 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1881 } else {
1882 adv = np->fixed_mode;
1883 }
1884 if (adv & ADVERTISE_10HALF)
1885 ecmd->advertising |= ADVERTISED_10baseT_Half;
1886 if (adv & ADVERTISE_10FULL)
1887 ecmd->advertising |= ADVERTISED_10baseT_Full;
1888 if (adv & ADVERTISE_100HALF)
1889 ecmd->advertising |= ADVERTISED_100baseT_Half;
1890 if (adv & ADVERTISE_100FULL)
1891 ecmd->advertising |= ADVERTISED_100baseT_Full;
1892 if (np->autoneg && np->gigabit == PHY_GIGABIT) {
1893 adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1894 if (adv & ADVERTISE_1000FULL)
1895 ecmd->advertising |= ADVERTISED_1000baseT_Full;
1896 }
1897
1898 ecmd->supported = (SUPPORTED_Autoneg |
1899 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
1900 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
1901 SUPPORTED_MII);
1902 if (np->gigabit == PHY_GIGABIT)
1903 ecmd->supported |= SUPPORTED_1000baseT_Full;
1904
1905 ecmd->phy_address = np->phyaddr;
1906 ecmd->transceiver = XCVR_EXTERNAL;
1907
1908 /* ignore maxtxpkt, maxrxpkt for now */
1909 spin_unlock_irq(&np->lock);
1910 return 0;
1911}
1912
1913static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1914{
1915 struct fe_priv *np = netdev_priv(dev);
1916
1917 if (ecmd->port != PORT_MII)
1918 return -EINVAL;
1919 if (ecmd->transceiver != XCVR_EXTERNAL)
1920 return -EINVAL;
1921 if (ecmd->phy_address != np->phyaddr) {
1922 /* TODO: support switching between multiple phys. Should be
1923 * trivial, but not enabled due to lack of test hardware. */
1924 return -EINVAL;
1925 }
1926 if (ecmd->autoneg == AUTONEG_ENABLE) {
1927 u32 mask;
1928
1929 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1930 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
1931 if (np->gigabit == PHY_GIGABIT)
1932 mask |= ADVERTISED_1000baseT_Full;
1933
1934 if ((ecmd->advertising & mask) == 0)
1935 return -EINVAL;
1936
1937 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
1938 /* Note: autonegotiation disable, speed 1000 intentionally
1939 * forbidden - noone should need that. */
1940
1941 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
1942 return -EINVAL;
1943 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
1944 return -EINVAL;
1945 } else {
1946 return -EINVAL;
1947 }
1948
1949 spin_lock_irq(&np->lock);
1950 if (ecmd->autoneg == AUTONEG_ENABLE) {
1951 int adv, bmcr;
1952
1953 np->autoneg = 1;
1954
1955 /* advertise only what has been requested */
1956 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1957 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
1958 if (ecmd->advertising & ADVERTISED_10baseT_Half)
1959 adv |= ADVERTISE_10HALF;
1960 if (ecmd->advertising & ADVERTISED_10baseT_Full)
1961 adv |= ADVERTISE_10FULL;
1962 if (ecmd->advertising & ADVERTISED_100baseT_Half)
1963 adv |= ADVERTISE_100HALF;
1964 if (ecmd->advertising & ADVERTISED_100baseT_Full)
1965 adv |= ADVERTISE_100FULL;
1966 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
1967
1968 if (np->gigabit == PHY_GIGABIT) {
1969 adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1970 adv &= ~ADVERTISE_1000FULL;
1971 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
1972 adv |= ADVERTISE_1000FULL;
1973 mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv);
1974 }
1975
1976 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1977 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1978 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
1979
1980 } else {
1981 int adv, bmcr;
1982
1983 np->autoneg = 0;
1984
1985 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1986 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
1987 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
1988 adv |= ADVERTISE_10HALF;
1989 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
1990 adv |= ADVERTISE_10FULL;
1991 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
1992 adv |= ADVERTISE_100HALF;
1993 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
1994 adv |= ADVERTISE_100FULL;
1995 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
1996 np->fixed_mode = adv;
1997
1998 if (np->gigabit == PHY_GIGABIT) {
1999 adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
2000 adv &= ~ADVERTISE_1000FULL;
2001 mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv);
2002 }
2003
2004 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
2005 bmcr |= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_FULLDPLX);
2006 if (adv & (ADVERTISE_10FULL|ADVERTISE_100FULL))
2007 bmcr |= BMCR_FULLDPLX;
2008 if (adv & (ADVERTISE_100HALF|ADVERTISE_100FULL))
2009 bmcr |= BMCR_SPEED100;
2010 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
2011
2012 if (netif_running(dev)) {
2013 /* Wait a bit and then reconfigure the nic. */
2014 udelay(10);
2015 nv_linkchange(dev);
2016 }
2017 }
2018 spin_unlock_irq(&np->lock);
2019
2020 return 0;
2021}
2022
Manfred Sprauldc8216c2005-07-31 18:26:05 +02002023#define FORCEDETH_REGS_VER 1
2024#define FORCEDETH_REGS_SIZE 0x400 /* 256 32-bit registers */
2025
2026static int nv_get_regs_len(struct net_device *dev)
2027{
2028 return FORCEDETH_REGS_SIZE;
2029}
2030
2031static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
2032{
2033 struct fe_priv *np = get_nvpriv(dev);
2034 u8 __iomem *base = get_hwbase(dev);
2035 u32 *rbuf = buf;
2036 int i;
2037
2038 regs->version = FORCEDETH_REGS_VER;
2039 spin_lock_irq(&np->lock);
2040 for (i=0;i<FORCEDETH_REGS_SIZE/sizeof(u32);i++)
2041 rbuf[i] = readl(base + i*sizeof(u32));
2042 spin_unlock_irq(&np->lock);
2043}
2044
2045static int nv_nway_reset(struct net_device *dev)
2046{
2047 struct fe_priv *np = get_nvpriv(dev);
2048 int ret;
2049
2050 spin_lock_irq(&np->lock);
2051 if (np->autoneg) {
2052 int bmcr;
2053
2054 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
2055 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
2056 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
2057
2058 ret = 0;
2059 } else {
2060 ret = -EINVAL;
2061 }
2062 spin_unlock_irq(&np->lock);
2063
2064 return ret;
2065}
2066
Linus Torvalds1da177e2005-04-16 15:20:36 -07002067static struct ethtool_ops ops = {
2068 .get_drvinfo = nv_get_drvinfo,
2069 .get_link = ethtool_op_get_link,
2070 .get_wol = nv_get_wol,
2071 .set_wol = nv_set_wol,
2072 .get_settings = nv_get_settings,
2073 .set_settings = nv_set_settings,
Manfred Sprauldc8216c2005-07-31 18:26:05 +02002074 .get_regs_len = nv_get_regs_len,
2075 .get_regs = nv_get_regs,
2076 .nway_reset = nv_nway_reset,
John W. Linvillec704b852005-09-12 10:48:56 -04002077 .get_perm_addr = ethtool_op_get_perm_addr,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002078};
2079
2080static int nv_open(struct net_device *dev)
2081{
2082 struct fe_priv *np = get_nvpriv(dev);
2083 u8 __iomem *base = get_hwbase(dev);
2084 int ret, oom, i;
2085
2086 dprintk(KERN_DEBUG "nv_open: begin\n");
2087
2088 /* 1) erase previous misconfiguration */
2089 /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
2090 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
2091 writel(0, base + NvRegMulticastAddrB);
2092 writel(0, base + NvRegMulticastMaskA);
2093 writel(0, base + NvRegMulticastMaskB);
2094 writel(0, base + NvRegPacketFilterFlags);
2095
2096 writel(0, base + NvRegTransmitterControl);
2097 writel(0, base + NvRegReceiverControl);
2098
2099 writel(0, base + NvRegAdapterControl);
2100
2101 /* 2) initialize descriptor rings */
Manfred Sprauld81c0982005-07-31 18:20:30 +02002102 set_bufsize(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002103 oom = nv_init_ring(dev);
2104
2105 writel(0, base + NvRegLinkSpeed);
2106 writel(0, base + NvRegUnknownTransmitterReg);
2107 nv_txrx_reset(dev);
2108 writel(0, base + NvRegUnknownSetupReg6);
2109
2110 np->in_shutdown = 0;
2111
2112 /* 3) set mac address */
Manfred Spraul72b31782005-07-31 18:33:34 +02002113 nv_copy_mac_to_hw(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002114
2115 /* 4) give hw rings */
2116 writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
Manfred Spraulee733622005-07-31 18:32:26 +02002117 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2118 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
2119 else
2120 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002121 writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
2122 base + NvRegRingSizes);
2123
2124 /* 5) continue setup */
2125 writel(np->linkspeed, base + NvRegLinkSpeed);
2126 writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04002127 writel(np->txrxctl_bits, base + NvRegTxRxControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002128 pci_push(base);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04002129 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002130 reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
2131 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
2132 KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
2133
2134 writel(0, base + NvRegUnknownSetupReg4);
2135 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2136 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
2137
2138 /* 6) continue setup */
2139 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
2140 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
2141 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002142 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002143
2144 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
2145 get_random_bytes(&i, sizeof(i));
2146 writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
2147 writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1);
2148 writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2);
2149 writel(NVREG_POLL_DEFAULT, base + NvRegPollingInterval);
2150 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
2151 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
2152 base + NvRegAdapterControl);
2153 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
2154 writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
2155 writel(NVREG_WAKEUPFLAGS_VAL, base + NvRegWakeUpFlags);
2156
2157 i = readl(base + NvRegPowerState);
2158 if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
2159 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
2160
2161 pci_push(base);
2162 udelay(10);
2163 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
2164
2165 writel(0, base + NvRegIrqMask);
2166 pci_push(base);
2167 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
2168 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2169 pci_push(base);
2170
2171 ret = request_irq(dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev);
2172 if (ret)
2173 goto out_drain;
2174
2175 /* ask for interrupts */
2176 writel(np->irqmask, base + NvRegIrqMask);
2177
2178 spin_lock_irq(&np->lock);
2179 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
2180 writel(0, base + NvRegMulticastAddrB);
2181 writel(0, base + NvRegMulticastMaskA);
2182 writel(0, base + NvRegMulticastMaskB);
2183 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
2184 /* One manual link speed update: Interrupts are enabled, future link
2185 * speed changes cause interrupts and are handled by nv_link_irq().
2186 */
2187 {
2188 u32 miistat;
2189 miistat = readl(base + NvRegMIIStatus);
2190 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
2191 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
2192 }
Manfred Spraul1b1b3c92005-08-06 23:47:55 +02002193 /* set linkspeed to invalid value, thus force nv_update_linkspeed
2194 * to init hw */
2195 np->linkspeed = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002196 ret = nv_update_linkspeed(dev);
2197 nv_start_rx(dev);
2198 nv_start_tx(dev);
2199 netif_start_queue(dev);
2200 if (ret) {
2201 netif_carrier_on(dev);
2202 } else {
2203 printk("%s: no link during initialization.\n", dev->name);
2204 netif_carrier_off(dev);
2205 }
2206 if (oom)
2207 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2208 spin_unlock_irq(&np->lock);
2209
2210 return 0;
2211out_drain:
2212 drain_ring(dev);
2213 return ret;
2214}
2215
2216static int nv_close(struct net_device *dev)
2217{
2218 struct fe_priv *np = get_nvpriv(dev);
2219 u8 __iomem *base;
2220
2221 spin_lock_irq(&np->lock);
2222 np->in_shutdown = 1;
2223 spin_unlock_irq(&np->lock);
2224 synchronize_irq(dev->irq);
2225
2226 del_timer_sync(&np->oom_kick);
2227 del_timer_sync(&np->nic_poll);
2228
2229 netif_stop_queue(dev);
2230 spin_lock_irq(&np->lock);
2231 nv_stop_tx(dev);
2232 nv_stop_rx(dev);
2233 nv_txrx_reset(dev);
2234
2235 /* disable interrupts on the nic or we will lock up */
2236 base = get_hwbase(dev);
2237 writel(0, base + NvRegIrqMask);
2238 pci_push(base);
2239 dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
2240
2241 spin_unlock_irq(&np->lock);
2242
2243 free_irq(dev->irq, dev);
2244
2245 drain_ring(dev);
2246
2247 if (np->wolenabled)
2248 nv_start_rx(dev);
2249
Manfred Spraulb3df9f82005-07-31 18:38:58 +02002250 /* special op: write back the misordered MAC address - otherwise
2251 * the next nv_probe would see a wrong address.
2252 */
2253 writel(np->orig_mac[0], base + NvRegMacAddrA);
2254 writel(np->orig_mac[1], base + NvRegMacAddrB);
2255
Linus Torvalds1da177e2005-04-16 15:20:36 -07002256 /* FIXME: power down nic */
2257
2258 return 0;
2259}
2260
2261static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
2262{
2263 struct net_device *dev;
2264 struct fe_priv *np;
2265 unsigned long addr;
2266 u8 __iomem *base;
2267 int err, i;
2268
2269 dev = alloc_etherdev(sizeof(struct fe_priv));
2270 err = -ENOMEM;
2271 if (!dev)
2272 goto out;
2273
2274 np = get_nvpriv(dev);
2275 np->pci_dev = pci_dev;
2276 spin_lock_init(&np->lock);
2277 SET_MODULE_OWNER(dev);
2278 SET_NETDEV_DEV(dev, &pci_dev->dev);
2279
2280 init_timer(&np->oom_kick);
2281 np->oom_kick.data = (unsigned long) dev;
2282 np->oom_kick.function = &nv_do_rx_refill; /* timer handler */
2283 init_timer(&np->nic_poll);
2284 np->nic_poll.data = (unsigned long) dev;
2285 np->nic_poll.function = &nv_do_nic_poll; /* timer handler */
2286
2287 err = pci_enable_device(pci_dev);
2288 if (err) {
2289 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
2290 err, pci_name(pci_dev));
2291 goto out_free;
2292 }
2293
2294 pci_set_master(pci_dev);
2295
2296 err = pci_request_regions(pci_dev, DRV_NAME);
2297 if (err < 0)
2298 goto out_disable;
2299
2300 err = -EINVAL;
2301 addr = 0;
2302 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
2303 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
2304 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
2305 pci_resource_len(pci_dev, i),
2306 pci_resource_flags(pci_dev, i));
2307 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
2308 pci_resource_len(pci_dev, i) >= NV_PCI_REGSZ) {
2309 addr = pci_resource_start(pci_dev, i);
2310 break;
2311 }
2312 }
2313 if (i == DEVICE_COUNT_RESOURCE) {
2314 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
2315 pci_name(pci_dev));
2316 goto out_relreg;
2317 }
2318
2319 /* handle different descriptor versions */
Manfred Spraulee733622005-07-31 18:32:26 +02002320 if (id->driver_data & DEV_HAS_HIGH_DMA) {
2321 /* packet format 3: supports 40-bit addressing */
2322 np->desc_ver = DESC_VER_3;
2323 if (pci_set_dma_mask(pci_dev, 0x0000007fffffffffULL)) {
2324 printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
2325 pci_name(pci_dev));
2326 }
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04002327 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
Manfred Spraulee733622005-07-31 18:32:26 +02002328 } else if (id->driver_data & DEV_HAS_LARGEDESC) {
2329 /* packet format 2: supports jumbo frames */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002330 np->desc_ver = DESC_VER_2;
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04002331 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
Manfred Spraulee733622005-07-31 18:32:26 +02002332 } else {
2333 /* original packet format */
2334 np->desc_ver = DESC_VER_1;
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04002335 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
Manfred Sprauld81c0982005-07-31 18:20:30 +02002336 }
Manfred Spraulee733622005-07-31 18:32:26 +02002337
2338 np->pkt_limit = NV_PKTLIMIT_1;
2339 if (id->driver_data & DEV_HAS_LARGEDESC)
2340 np->pkt_limit = NV_PKTLIMIT_2;
2341
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04002342 if (id->driver_data & DEV_HAS_CHECKSUM) {
2343 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
2344 dev->features |= NETIF_F_HW_CSUM;
2345 }
2346
Linus Torvalds1da177e2005-04-16 15:20:36 -07002347 err = -ENOMEM;
2348 np->base = ioremap(addr, NV_PCI_REGSZ);
2349 if (!np->base)
2350 goto out_relreg;
2351 dev->base_addr = (unsigned long)np->base;
Manfred Spraulee733622005-07-31 18:32:26 +02002352
Linus Torvalds1da177e2005-04-16 15:20:36 -07002353 dev->irq = pci_dev->irq;
Manfred Spraulee733622005-07-31 18:32:26 +02002354
2355 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
2356 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
2357 sizeof(struct ring_desc) * (RX_RING + TX_RING),
2358 &np->ring_addr);
2359 if (!np->rx_ring.orig)
2360 goto out_unmap;
2361 np->tx_ring.orig = &np->rx_ring.orig[RX_RING];
2362 } else {
2363 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
2364 sizeof(struct ring_desc_ex) * (RX_RING + TX_RING),
2365 &np->ring_addr);
2366 if (!np->rx_ring.ex)
2367 goto out_unmap;
2368 np->tx_ring.ex = &np->rx_ring.ex[RX_RING];
2369 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002370
2371 dev->open = nv_open;
2372 dev->stop = nv_close;
2373 dev->hard_start_xmit = nv_start_xmit;
2374 dev->get_stats = nv_get_stats;
2375 dev->change_mtu = nv_change_mtu;
Manfred Spraul72b31782005-07-31 18:33:34 +02002376 dev->set_mac_address = nv_set_mac_address;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002377 dev->set_multicast_list = nv_set_multicast;
Michal Schmidt2918c352005-05-12 19:42:06 -04002378#ifdef CONFIG_NET_POLL_CONTROLLER
2379 dev->poll_controller = nv_poll_controller;
2380#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002381 SET_ETHTOOL_OPS(dev, &ops);
2382 dev->tx_timeout = nv_tx_timeout;
2383 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
2384
2385 pci_set_drvdata(pci_dev, dev);
2386
2387 /* read the mac address */
2388 base = get_hwbase(dev);
2389 np->orig_mac[0] = readl(base + NvRegMacAddrA);
2390 np->orig_mac[1] = readl(base + NvRegMacAddrB);
2391
2392 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
2393 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
2394 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
2395 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
2396 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
2397 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
John W. Linvillec704b852005-09-12 10:48:56 -04002398 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002399
John W. Linvillec704b852005-09-12 10:48:56 -04002400 if (!is_valid_ether_addr(dev->perm_addr)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002401 /*
2402 * Bad mac address. At least one bios sets the mac address
2403 * to 01:23:45:67:89:ab
2404 */
2405 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
2406 pci_name(pci_dev),
2407 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2408 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2409 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
2410 dev->dev_addr[0] = 0x00;
2411 dev->dev_addr[1] = 0x00;
2412 dev->dev_addr[2] = 0x6c;
2413 get_random_bytes(&dev->dev_addr[3], 3);
2414 }
2415
2416 dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
2417 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2418 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2419
2420 /* disable WOL */
2421 writel(0, base + NvRegWakeUpFlags);
2422 np->wolenabled = 0;
2423
2424 if (np->desc_ver == DESC_VER_1) {
2425 np->tx_flags = NV_TX_LASTPACKET|NV_TX_VALID;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002426 } else {
2427 np->tx_flags = NV_TX2_LASTPACKET|NV_TX2_VALID;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002428 }
Manfred Spraulc2dba062005-07-31 18:29:47 +02002429 np->irqmask = NVREG_IRQMASK_WANTED;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002430 if (id->driver_data & DEV_NEED_TIMERIRQ)
2431 np->irqmask |= NVREG_IRQ_TIMER;
2432 if (id->driver_data & DEV_NEED_LINKTIMER) {
2433 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
2434 np->need_linktimer = 1;
2435 np->link_timeout = jiffies + LINK_TIMEOUT;
2436 } else {
2437 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
2438 np->need_linktimer = 0;
2439 }
2440
2441 /* find a suitable phy */
2442 for (i = 1; i < 32; i++) {
2443 int id1, id2;
2444
2445 spin_lock_irq(&np->lock);
2446 id1 = mii_rw(dev, i, MII_PHYSID1, MII_READ);
2447 spin_unlock_irq(&np->lock);
2448 if (id1 < 0 || id1 == 0xffff)
2449 continue;
2450 spin_lock_irq(&np->lock);
2451 id2 = mii_rw(dev, i, MII_PHYSID2, MII_READ);
2452 spin_unlock_irq(&np->lock);
2453 if (id2 < 0 || id2 == 0xffff)
2454 continue;
2455
2456 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
2457 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
2458 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
2459 pci_name(pci_dev), id1, id2, i);
2460 np->phyaddr = i;
2461 np->phy_oui = id1 | id2;
2462 break;
2463 }
2464 if (i == 32) {
2465 /* PHY in isolate mode? No phy attached and user wants to
2466 * test loopback? Very odd, but can be correct.
2467 */
2468 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
2469 pci_name(pci_dev));
2470 }
2471
2472 if (i != 32) {
2473 /* reset it */
2474 phy_init(dev);
2475 }
2476
2477 /* set default link speed settings */
2478 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2479 np->duplex = 0;
2480 np->autoneg = 1;
2481
2482 err = register_netdev(dev);
2483 if (err) {
2484 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
2485 goto out_freering;
2486 }
2487 printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
2488 dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
2489 pci_name(pci_dev));
2490
2491 return 0;
2492
2493out_freering:
Manfred Spraulee733622005-07-31 18:32:26 +02002494 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2495 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING),
2496 np->rx_ring.orig, np->ring_addr);
2497 else
2498 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (RX_RING + TX_RING),
2499 np->rx_ring.ex, np->ring_addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002500 pci_set_drvdata(pci_dev, NULL);
2501out_unmap:
2502 iounmap(get_hwbase(dev));
2503out_relreg:
2504 pci_release_regions(pci_dev);
2505out_disable:
2506 pci_disable_device(pci_dev);
2507out_free:
2508 free_netdev(dev);
2509out:
2510 return err;
2511}
2512
2513static void __devexit nv_remove(struct pci_dev *pci_dev)
2514{
2515 struct net_device *dev = pci_get_drvdata(pci_dev);
2516 struct fe_priv *np = get_nvpriv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002517
2518 unregister_netdev(dev);
2519
Linus Torvalds1da177e2005-04-16 15:20:36 -07002520 /* free all structures */
Manfred Spraulee733622005-07-31 18:32:26 +02002521 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2522 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING), np->rx_ring.orig, np->ring_addr);
2523 else
2524 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (RX_RING + TX_RING), np->rx_ring.ex, np->ring_addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002525 iounmap(get_hwbase(dev));
2526 pci_release_regions(pci_dev);
2527 pci_disable_device(pci_dev);
2528 free_netdev(dev);
2529 pci_set_drvdata(pci_dev, NULL);
2530}
2531
2532static struct pci_device_id pci_tbl[] = {
2533 { /* nForce Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02002534 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
Manfred Spraulc2dba062005-07-31 18:29:47 +02002535 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002536 },
2537 { /* nForce2 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02002538 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
Manfred Spraulc2dba062005-07-31 18:29:47 +02002539 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002540 },
2541 { /* nForce3 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02002542 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
Manfred Spraulc2dba062005-07-31 18:29:47 +02002543 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002544 },
2545 { /* nForce3 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02002546 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04002547 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002548 },
2549 { /* nForce3 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02002550 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04002551 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002552 },
2553 { /* nForce3 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02002554 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04002555 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002556 },
2557 { /* nForce3 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02002558 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04002559 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002560 },
2561 { /* CK804 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02002562 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04002563 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002564 },
2565 { /* CK804 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02002566 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04002567 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002568 },
2569 { /* MCP04 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02002570 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04002571 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002572 },
2573 { /* MCP04 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02002574 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04002575 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
Manfred Sprauldc8216c2005-07-31 18:26:05 +02002576 },
2577 { /* MCP51 Ethernet Controller */
2578 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
Manfred Spraulee733622005-07-31 18:32:26 +02002579 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002580 },
Manfred Spraul9992d4a2005-06-05 17:36:11 +02002581 { /* MCP51 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02002582 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
Manfred Spraulee733622005-07-31 18:32:26 +02002583 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA,
Manfred Spraul9992d4a2005-06-05 17:36:11 +02002584 },
Manfred Spraulf49d16e2005-06-26 11:36:52 +02002585 { /* MCP55 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02002586 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04002587 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
Manfred Spraulf49d16e2005-06-26 11:36:52 +02002588 },
2589 { /* MCP55 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02002590 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04002591 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
Manfred Spraulf49d16e2005-06-26 11:36:52 +02002592 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07002593 {0,},
2594};
2595
2596static struct pci_driver driver = {
2597 .name = "forcedeth",
2598 .id_table = pci_tbl,
2599 .probe = nv_probe,
2600 .remove = __devexit_p(nv_remove),
2601};
2602
2603
2604static int __init init_nic(void)
2605{
2606 printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
2607 return pci_module_init(&driver);
2608}
2609
2610static void __exit exit_nic(void)
2611{
2612 pci_unregister_driver(&driver);
2613}
2614
2615module_param(max_interrupt_work, int, 0);
2616MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
2617
2618MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
2619MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
2620MODULE_LICENSE("GPL");
2621
2622MODULE_DEVICE_TABLE(pci, pci_tbl);
2623
2624module_init(init_nic);
2625module_exit(exit_nic);