| Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * linux/include/asm-arm/arch-realview/platform.h |
| 3 | * |
| 4 | * Copyright (c) ARM Limited 2003. All rights reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 19 | */ |
| 20 | |
| 21 | #ifndef __address_h |
| 22 | #define __address_h 1 |
| 23 | |
| 24 | /* |
| 25 | * Memory definitions |
| 26 | */ |
| 27 | #define REALVIEW_BOOT_ROM_LO 0x30000000 /* DoC Base (64Mb)...*/ |
| 28 | #define REALVIEW_BOOT_ROM_HI 0x30000000 |
| 29 | #define REALVIEW_BOOT_ROM_BASE REALVIEW_BOOT_ROM_HI /* Normal position */ |
| 30 | #define REALVIEW_BOOT_ROM_SIZE SZ_64M |
| 31 | |
| 32 | #define REALVIEW_SSRAM_BASE /* REALVIEW_SSMC_BASE ? */ |
| 33 | #define REALVIEW_SSRAM_SIZE SZ_2M |
| 34 | |
| 35 | #define REALVIEW_FLASH_BASE 0x40000000 |
| 36 | #define REALVIEW_FLASH_SIZE SZ_64M |
| 37 | |
| 38 | /* |
| 39 | * SDRAM |
| 40 | */ |
| 41 | #define REALVIEW_SDRAM_BASE 0x00000000 |
| 42 | |
| 43 | /* |
| 44 | * Logic expansion modules |
| 45 | * |
| 46 | */ |
| 47 | |
| 48 | |
| 49 | /* ------------------------------------------------------------------------ |
| 50 | * RealView Registers |
| 51 | * ------------------------------------------------------------------------ |
| 52 | * |
| 53 | */ |
| 54 | #define REALVIEW_SYS_ID_OFFSET 0x00 |
| 55 | #define REALVIEW_SYS_SW_OFFSET 0x04 |
| 56 | #define REALVIEW_SYS_LED_OFFSET 0x08 |
| 57 | #define REALVIEW_SYS_OSC0_OFFSET 0x0C |
| 58 | |
| 59 | #define REALVIEW_SYS_OSC1_OFFSET 0x10 |
| 60 | #define REALVIEW_SYS_OSC2_OFFSET 0x14 |
| 61 | #define REALVIEW_SYS_OSC3_OFFSET 0x18 |
| 62 | #define REALVIEW_SYS_OSC4_OFFSET 0x1C /* OSC1 for RealView/AB */ |
| 63 | |
| 64 | #define REALVIEW_SYS_LOCK_OFFSET 0x20 |
| 65 | #define REALVIEW_SYS_100HZ_OFFSET 0x24 |
| 66 | #define REALVIEW_SYS_CFGDATA1_OFFSET 0x28 |
| 67 | #define REALVIEW_SYS_CFGDATA2_OFFSET 0x2C |
| 68 | #define REALVIEW_SYS_FLAGS_OFFSET 0x30 |
| 69 | #define REALVIEW_SYS_FLAGSSET_OFFSET 0x30 |
| 70 | #define REALVIEW_SYS_FLAGSCLR_OFFSET 0x34 |
| 71 | #define REALVIEW_SYS_NVFLAGS_OFFSET 0x38 |
| 72 | #define REALVIEW_SYS_NVFLAGSSET_OFFSET 0x38 |
| 73 | #define REALVIEW_SYS_NVFLAGSCLR_OFFSET 0x3C |
| 74 | #define REALVIEW_SYS_RESETCTL_OFFSET 0x40 |
| 75 | #define REALVIEW_SYS_PCICTL_OFFSET 0x44 |
| 76 | #define REALVIEW_SYS_MCI_OFFSET 0x48 |
| 77 | #define REALVIEW_SYS_FLASH_OFFSET 0x4C |
| 78 | #define REALVIEW_SYS_CLCD_OFFSET 0x50 |
| 79 | #define REALVIEW_SYS_CLCDSER_OFFSET 0x54 |
| 80 | #define REALVIEW_SYS_BOOTCS_OFFSET 0x58 |
| 81 | #define REALVIEW_SYS_24MHz_OFFSET 0x5C |
| 82 | #define REALVIEW_SYS_MISC_OFFSET 0x60 |
| 83 | #define REALVIEW_SYS_IOSEL_OFFSET 0x70 |
| 84 | #define REALVIEW_SYS_TEST_OSC0_OFFSET 0x80 |
| 85 | #define REALVIEW_SYS_TEST_OSC1_OFFSET 0x84 |
| 86 | #define REALVIEW_SYS_TEST_OSC2_OFFSET 0x88 |
| 87 | #define REALVIEW_SYS_TEST_OSC3_OFFSET 0x8C |
| 88 | #define REALVIEW_SYS_TEST_OSC4_OFFSET 0x90 |
| 89 | |
| 90 | #define REALVIEW_SYS_BASE 0x10000000 |
| 91 | #define REALVIEW_SYS_ID (REALVIEW_SYS_BASE + REALVIEW_SYS_ID_OFFSET) |
| 92 | #define REALVIEW_SYS_SW (REALVIEW_SYS_BASE + REALVIEW_SYS_SW_OFFSET) |
| 93 | #define REALVIEW_SYS_LED (REALVIEW_SYS_BASE + REALVIEW_SYS_LED_OFFSET) |
| 94 | #define REALVIEW_SYS_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC0_OFFSET) |
| 95 | #define REALVIEW_SYS_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC1_OFFSET) |
| 96 | |
| 97 | #define REALVIEW_SYS_LOCK (REALVIEW_SYS_BASE + REALVIEW_SYS_LOCK_OFFSET) |
| 98 | #define REALVIEW_SYS_100HZ (REALVIEW_SYS_BASE + REALVIEW_SYS_100HZ_OFFSET) |
| 99 | #define REALVIEW_SYS_CFGDATA1 (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA1_OFFSET) |
| 100 | #define REALVIEW_SYS_CFGDATA2 (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA2_OFFSET) |
| 101 | #define REALVIEW_SYS_FLAGS (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGS_OFFSET) |
| 102 | #define REALVIEW_SYS_FLAGSSET (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSSET_OFFSET) |
| 103 | #define REALVIEW_SYS_FLAGSCLR (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSCLR_OFFSET) |
| 104 | #define REALVIEW_SYS_NVFLAGS (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGS_OFFSET) |
| 105 | #define REALVIEW_SYS_NVFLAGSSET (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSSET_OFFSET) |
| 106 | #define REALVIEW_SYS_NVFLAGSCLR (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSCLR_OFFSET) |
| 107 | #define REALVIEW_SYS_RESETCTL (REALVIEW_SYS_BASE + REALVIEW_SYS_RESETCTL_OFFSET) |
| 108 | #define REALVIEW_SYS_PCICTL (REALVIEW_SYS_BASE + REALVIEW_SYS_PCICTL_OFFSET) |
| 109 | #define REALVIEW_SYS_MCI (REALVIEW_SYS_BASE + REALVIEW_SYS_MCI_OFFSET) |
| 110 | #define REALVIEW_SYS_FLASH (REALVIEW_SYS_BASE + REALVIEW_SYS_FLASH_OFFSET) |
| 111 | #define REALVIEW_SYS_CLCD (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCD_OFFSET) |
| 112 | #define REALVIEW_SYS_CLCDSER (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCDSER_OFFSET) |
| 113 | #define REALVIEW_SYS_BOOTCS (REALVIEW_SYS_BASE + REALVIEW_SYS_BOOTCS_OFFSET) |
| 114 | #define REALVIEW_SYS_24MHz (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET) |
| 115 | #define REALVIEW_SYS_MISC (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET) |
| 116 | #define REALVIEW_SYS_IOSEL (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET) |
| 117 | #define REALVIEW_SYS_TEST_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET) |
| 118 | #define REALVIEW_SYS_TEST_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC1_OFFSET) |
| 119 | #define REALVIEW_SYS_TEST_OSC2 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC2_OFFSET) |
| 120 | #define REALVIEW_SYS_TEST_OSC3 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC3_OFFSET) |
| 121 | #define REALVIEW_SYS_TEST_OSC4 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC4_OFFSET) |
| 122 | |
| 123 | /* |
| 124 | * Values for REALVIEW_SYS_RESET_CTRL |
| 125 | */ |
| 126 | #define REALVIEW_SYS_CTRL_RESET_CONFIGCLR 0x01 |
| 127 | #define REALVIEW_SYS_CTRL_RESET_CONFIGINIT 0x02 |
| 128 | #define REALVIEW_SYS_CTRL_RESET_DLLRESET 0x03 |
| 129 | #define REALVIEW_SYS_CTRL_RESET_PLLRESET 0x04 |
| 130 | #define REALVIEW_SYS_CTRL_RESET_POR 0x05 |
| 131 | #define REALVIEW_SYS_CTRL_RESET_DoC 0x06 |
| 132 | |
| 133 | #define REALVIEW_SYS_CTRL_LED (1 << 0) |
| 134 | |
| 135 | |
| 136 | /* ------------------------------------------------------------------------ |
| 137 | * RealView control registers |
| 138 | * ------------------------------------------------------------------------ |
| 139 | */ |
| 140 | |
| 141 | /* |
| 142 | * REALVIEW_IDFIELD |
| 143 | * |
| 144 | * 31:24 = manufacturer (0x41 = ARM) |
| 145 | * 23:16 = architecture (0x08 = AHB system bus, ASB processor bus) |
| 146 | * 15:12 = FPGA (0x3 = XVC600 or XVC600E) |
| 147 | * 11:4 = build value |
| 148 | * 3:0 = revision number (0x1 = rev B (AHB)) |
| 149 | */ |
| 150 | |
| 151 | /* |
| 152 | * REALVIEW_SYS_LOCK |
| 153 | * control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL, |
| 154 | * SYS_CLD, SYS_BOOTCS |
| 155 | */ |
| 156 | #define REALVIEW_SYS_LOCK_LOCKED (1 << 16) |
| 157 | #define REALVIEW_SYS_LOCKVAL_MASK 0xFFFF /* write 0xA05F to enable write access */ |
| 158 | |
| 159 | /* |
| 160 | * REALVIEW_SYS_FLASH |
| 161 | */ |
| 162 | #define REALVIEW_FLASHPROG_FLVPPEN (1 << 0) /* Enable writing to flash */ |
| 163 | |
| 164 | /* |
| 165 | * REALVIEW_INTREG |
| 166 | * - used to acknowledge and control MMCI and UART interrupts |
| 167 | */ |
| 168 | #define REALVIEW_INTREG_WPROT 0x00 /* MMC protection status (no interrupt generated) */ |
| 169 | #define REALVIEW_INTREG_RI0 0x01 /* Ring indicator UART0 is asserted, */ |
| 170 | #define REALVIEW_INTREG_CARDIN 0x08 /* MMCI card in detect */ |
| 171 | /* write 1 to acknowledge and clear */ |
| 172 | #define REALVIEW_INTREG_RI1 0x02 /* Ring indicator UART1 is asserted, */ |
| 173 | #define REALVIEW_INTREG_CARDINSERT 0x03 /* Signal insertion of MMC card */ |
| 174 | |
| 175 | /* |
| 176 | * REALVIEW peripheral addresses |
| 177 | */ |
| 178 | #define REALVIEW_SCTL_BASE 0x10001000 /* System controller */ |
| 179 | #define REALVIEW_I2C_BASE 0x10002000 /* I2C control */ |
| 180 | /* Reserved 0x10003000 */ |
| 181 | #define REALVIEW_AACI_BASE 0x10004000 /* Audio */ |
| 182 | #define REALVIEW_MMCI0_BASE 0x10005000 /* MMC interface */ |
| 183 | #define REALVIEW_KMI0_BASE 0x10006000 /* KMI interface */ |
| 184 | #define REALVIEW_KMI1_BASE 0x10007000 /* KMI 2nd interface */ |
| 185 | #define REALVIEW_CHAR_LCD_BASE 0x10008000 /* Character LCD */ |
| 186 | #define REALVIEW_UART0_BASE 0x10009000 /* UART 0 */ |
| 187 | #define REALVIEW_UART1_BASE 0x1000A000 /* UART 1 */ |
| 188 | #define REALVIEW_UART2_BASE 0x1000B000 /* UART 2 */ |
| 189 | #define REALVIEW_UART3_BASE 0x1000C000 /* UART 3 */ |
| 190 | #define REALVIEW_SSP_BASE 0x1000D000 /* Synchronous Serial Port */ |
| 191 | #define REALVIEW_SCI_BASE 0x1000E000 /* Smart card controller */ |
| 192 | /* Reserved 0x1000F000 */ |
| 193 | #define REALVIEW_WATCHDOG_BASE 0x10010000 /* watchdog interface */ |
| 194 | #define REALVIEW_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */ |
| 195 | #define REALVIEW_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */ |
| 196 | #define REALVIEW_GPIO0_BASE 0x10013000 /* GPIO port 0 */ |
| 197 | #define REALVIEW_GPIO1_BASE 0x10014000 /* GPIO port 1 */ |
| 198 | #define REALVIEW_GPIO2_BASE 0x10015000 /* GPIO port 2 */ |
| 199 | /* Reserved 0x10016000 */ |
| 200 | #define REALVIEW_RTC_BASE 0x10017000 /* Real Time Clock */ |
| 201 | #define REALVIEW_DMC_BASE 0x10018000 /* DMC configuration */ |
| 202 | #define REALVIEW_PCI_CORE_BASE 0x10019000 /* PCI configuration */ |
| 203 | /* Reserved 0x1001A000 - 0x1001FFFF */ |
| 204 | #define REALVIEW_CLCD_BASE 0x10020000 /* CLCD */ |
| 205 | #define REALVIEW_DMAC_BASE 0x10030000 /* DMA controller */ |
| 206 | #define REALVIEW_GIC_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */ |
| 207 | #define REALVIEW_GIC_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */ |
| 208 | #define REALVIEW_SMC_BASE 0x10080000 /* SMC */ |
| 209 | /* Reserved 0x10090000 - 0x100EFFFF */ |
| 210 | |
| 211 | #define REALVIEW_ETH_BASE 0x4E000000 /* Ethernet */ |
| 212 | |
| 213 | /* PCI space */ |
| 214 | #define REALVIEW_PCI_BASE 0x41000000 /* PCI Interface */ |
| 215 | #define REALVIEW_PCI_CFG_BASE 0x42000000 |
| 216 | #define REALVIEW_PCI_MEM_BASE0 0x44000000 |
| 217 | #define REALVIEW_PCI_MEM_BASE1 0x50000000 |
| 218 | #define REALVIEW_PCI_MEM_BASE2 0x60000000 |
| 219 | /* Sizes of above maps */ |
| 220 | #define REALVIEW_PCI_BASE_SIZE 0x01000000 |
| 221 | #define REALVIEW_PCI_CFG_BASE_SIZE 0x02000000 |
| 222 | #define REALVIEW_PCI_MEM_BASE0_SIZE 0x0c000000 /* 32Mb */ |
| 223 | #define REALVIEW_PCI_MEM_BASE1_SIZE 0x10000000 /* 256Mb */ |
| 224 | #define REALVIEW_PCI_MEM_BASE2_SIZE 0x10000000 /* 256Mb */ |
| 225 | |
| 226 | #define REALVIEW_SDRAM67_BASE 0x70000000 /* SDRAM banks 6 and 7 */ |
| 227 | #define REALVIEW_LT_BASE 0x80000000 /* Logic Tile expansion */ |
| 228 | |
| 229 | /* |
| 230 | * Disk on Chip |
| 231 | */ |
| 232 | #define REALVIEW_DOC_BASE 0x2C000000 |
| 233 | #define REALVIEW_DOC_SIZE (16 << 20) |
| 234 | #define REALVIEW_DOC_PAGE_SIZE 512 |
| 235 | #define REALVIEW_DOC_TOTAL_PAGES (DOC_SIZE / PAGE_SIZE) |
| 236 | |
| 237 | #define ERASE_UNIT_PAGES 32 |
| 238 | #define START_PAGE 0x80 |
| 239 | |
| 240 | /* |
| 241 | * LED settings, bits [7:0] |
| 242 | */ |
| 243 | #define REALVIEW_SYS_LED0 (1 << 0) |
| 244 | #define REALVIEW_SYS_LED1 (1 << 1) |
| 245 | #define REALVIEW_SYS_LED2 (1 << 2) |
| 246 | #define REALVIEW_SYS_LED3 (1 << 3) |
| 247 | #define REALVIEW_SYS_LED4 (1 << 4) |
| 248 | #define REALVIEW_SYS_LED5 (1 << 5) |
| 249 | #define REALVIEW_SYS_LED6 (1 << 6) |
| 250 | #define REALVIEW_SYS_LED7 (1 << 7) |
| 251 | |
| 252 | #define ALL_LEDS 0xFF |
| 253 | |
| 254 | #define LED_BANK REALVIEW_SYS_LED |
| 255 | |
| 256 | /* |
| 257 | * Control registers |
| 258 | */ |
| 259 | #define REALVIEW_IDFIELD_OFFSET 0x0 /* RealView build information */ |
| 260 | #define REALVIEW_FLASHPROG_OFFSET 0x4 /* Flash devices */ |
| 261 | #define REALVIEW_INTREG_OFFSET 0x8 /* Interrupt control */ |
| 262 | #define REALVIEW_DECODE_OFFSET 0xC /* Fitted logic modules */ |
| 263 | |
| 264 | /* ------------------------------------------------------------------------ |
| 265 | * Interrupts - bit assignment (primary) |
| 266 | * ------------------------------------------------------------------------ |
| 267 | */ |
| 268 | #define INT_WDOGINT 0 /* Watchdog timer */ |
| 269 | #define INT_SOFTINT 1 /* Software interrupt */ |
| 270 | #define INT_COMMRx 2 /* Debug Comm Rx interrupt */ |
| 271 | #define INT_COMMTx 3 /* Debug Comm Tx interrupt */ |
| 272 | #define INT_TIMERINT0_1 4 /* Timer 0 and 1 */ |
| 273 | #define INT_TIMERINT2_3 5 /* Timer 2 and 3 */ |
| 274 | #define INT_GPIOINT0 6 /* GPIO 0 */ |
| 275 | #define INT_GPIOINT1 7 /* GPIO 1 */ |
| 276 | #define INT_GPIOINT2 8 /* GPIO 2 */ |
| 277 | /* 9 reserved */ |
| 278 | #define INT_RTCINT 10 /* Real Time Clock */ |
| 279 | #define INT_SSPINT 11 /* Synchronous Serial Port */ |
| 280 | #define INT_UARTINT0 12 /* UART 0 on development chip */ |
| 281 | #define INT_UARTINT1 13 /* UART 1 on development chip */ |
| 282 | #define INT_UARTINT2 14 /* UART 2 on development chip */ |
| 283 | #define INT_UARTINT3 15 /* UART 3 on development chip */ |
| 284 | #define INT_SCIINT 16 /* Smart Card Interface */ |
| 285 | #define INT_MMCI0A 17 /* Multimedia Card 0A */ |
| 286 | #define INT_MMCI0B 18 /* Multimedia Card 0B */ |
| 287 | #define INT_AACI 19 /* Audio Codec */ |
| 288 | #define INT_KMI0 20 /* Keyboard/Mouse port 0 */ |
| 289 | #define INT_KMI1 21 /* Keyboard/Mouse port 1 */ |
| 290 | #define INT_CHARLCD 22 /* Character LCD */ |
| 291 | #define INT_CLCDINT 23 /* CLCD controller */ |
| 292 | #define INT_DMAINT 24 /* DMA controller */ |
| 293 | #define INT_PWRFAILINT 25 /* Power failure */ |
| 294 | #define INT_PISMO 26 |
| 295 | #define INT_DoC 27 /* Disk on Chip memory controller */ |
| 296 | #define INT_ETH 28 /* Ethernet controller */ |
| 297 | #define INT_USB 29 /* USB controller */ |
| 298 | #define INT_TSPENINT 30 /* Touchscreen pen */ |
| 299 | #define INT_TSKPADINT 31 /* Touchscreen keypad */ |
| 300 | |
| 301 | /* |
| 302 | * Interrupt bit positions |
| 303 | * |
| 304 | */ |
| 305 | #define INTMASK_WDOGINT (1 << INT_WDOGINT) |
| 306 | #define INTMASK_SOFTINT (1 << INT_SOFTINT) |
| 307 | #define INTMASK_COMMRx (1 << INT_COMMRx) |
| 308 | #define INTMASK_COMMTx (1 << INT_COMMTx) |
| 309 | #define INTMASK_TIMERINT0_1 (1 << INT_TIMERINT0_1) |
| 310 | #define INTMASK_TIMERINT2_3 (1 << INT_TIMERINT2_3) |
| 311 | #define INTMASK_GPIOINT0 (1 << INT_GPIOINT0) |
| 312 | #define INTMASK_GPIOINT1 (1 << INT_GPIOINT1) |
| 313 | #define INTMASK_GPIOINT2 (1 << INT_GPIOINT2) |
| 314 | #define INTMASK_RTCINT (1 << INT_RTCINT) |
| 315 | #define INTMASK_SSPINT (1 << INT_SSPINT) |
| 316 | #define INTMASK_UARTINT0 (1 << INT_UARTINT0) |
| 317 | #define INTMASK_UARTINT1 (1 << INT_UARTINT1) |
| 318 | #define INTMASK_UARTINT2 (1 << INT_UARTINT2) |
| 319 | #define INTMASK_UARTINT3 (1 << INT_UARTINT3) |
| 320 | #define INTMASK_SCIINT (1 << INT_SCIINT) |
| 321 | #define INTMASK_MMCI0A (1 << INT_MMCI0A) |
| 322 | #define INTMASK_MMCI0B (1 << INT_MMCI0B) |
| 323 | #define INTMASK_AACI (1 << INT_AACI) |
| 324 | #define INTMASK_KMI0 (1 << INT_KMI0) |
| 325 | #define INTMASK_KMI1 (1 << INT_KMI1) |
| 326 | #define INTMASK_CHARLCD (1 << INT_CHARLCD) |
| 327 | #define INTMASK_CLCDINT (1 << INT_CLCDINT) |
| 328 | #define INTMASK_DMAINT (1 << INT_DMAINT) |
| 329 | #define INTMASK_PWRFAILINT (1 << INT_PWRFAILINT) |
| 330 | #define INTMASK_PISMO (1 << INT_PISMO) |
| 331 | #define INTMASK_DoC (1 << INT_DoC) |
| 332 | #define INTMASK_ETH (1 << INT_ETH) |
| 333 | #define INTMASK_USB (1 << INT_USB) |
| 334 | #define INTMASK_TSPENINT (1 << INT_TSPENINT) |
| 335 | #define INTMASK_TSKPADINT (1 << INT_TSKPADINT) |
| 336 | |
| 337 | #define MAXIRQNUM 31 |
| 338 | #define MAXFIQNUM 31 |
| 339 | #define MAXSWINUM 31 |
| 340 | |
| 341 | /* |
| 342 | * Application Flash |
| 343 | * |
| 344 | */ |
| 345 | #define FLASH_BASE REALVIEW_FLASH_BASE |
| 346 | #define FLASH_SIZE REALVIEW_FLASH_SIZE |
| 347 | #define FLASH_END (FLASH_BASE + FLASH_SIZE - 1) |
| 348 | #define FLASH_BLOCK_SIZE SZ_128K |
| 349 | |
| 350 | /* |
| 351 | * Boot Flash |
| 352 | * |
| 353 | */ |
| 354 | #define EPROM_BASE REALVIEW_BOOT_ROM_HI |
| 355 | #define EPROM_SIZE REALVIEW_BOOT_ROM_SIZE |
| 356 | #define EPROM_END (EPROM_BASE + EPROM_SIZE - 1) |
| 357 | |
| 358 | /* |
| 359 | * Clean base - dummy |
| 360 | * |
| 361 | */ |
| 362 | #define CLEAN_BASE EPROM_BASE |
| 363 | |
| 364 | /* |
| 365 | * System controller bit assignment |
| 366 | */ |
| 367 | #define REALVIEW_REFCLK 0 |
| 368 | #define REALVIEW_TIMCLK 1 |
| 369 | |
| 370 | #define REALVIEW_TIMER1_EnSel 15 |
| 371 | #define REALVIEW_TIMER2_EnSel 17 |
| 372 | #define REALVIEW_TIMER3_EnSel 19 |
| 373 | #define REALVIEW_TIMER4_EnSel 21 |
| 374 | |
| 375 | |
| 376 | #define MAX_TIMER 2 |
| 377 | #define MAX_PERIOD 699050 |
| 378 | #define TICKS_PER_uSEC 1 |
| 379 | |
| 380 | /* |
| 381 | * These are useconds NOT ticks. |
| 382 | * |
| 383 | */ |
| 384 | #define mSEC_1 1000 |
| 385 | #define mSEC_5 (mSEC_1 * 5) |
| 386 | #define mSEC_10 (mSEC_1 * 10) |
| 387 | #define mSEC_25 (mSEC_1 * 25) |
| 388 | #define SEC_1 (mSEC_1 * 1000) |
| 389 | |
| 390 | #define REALVIEW_CSR_BASE 0x10000000 |
| 391 | #define REALVIEW_CSR_SIZE 0x10000000 |
| 392 | |
| 393 | #endif |
| 394 | |
| 395 | /* END */ |