blob: bd9e3205674b5bae4ae3bd7d55fa551d8cd6a689 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8#include <linux/config.h>
David S. Millerc4bce902006-02-11 21:57:54 -08009#include <linux/module.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070010#include <linux/kernel.h>
11#include <linux/sched.h>
12#include <linux/string.h>
13#include <linux/init.h>
14#include <linux/bootmem.h>
15#include <linux/mm.h>
16#include <linux/hugetlb.h>
17#include <linux/slab.h>
18#include <linux/initrd.h>
19#include <linux/swap.h>
20#include <linux/pagemap.h>
21#include <linux/fs.h>
22#include <linux/seq_file.h>
Prasanna S Panchamukhi05e14cb2005-09-06 15:19:30 -070023#include <linux/kprobes.h>
David S. Miller1ac4f5e2005-09-21 21:49:32 -070024#include <linux/cache.h>
David S. Miller13edad72005-09-29 17:58:26 -070025#include <linux/sort.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070026
27#include <asm/head.h>
28#include <asm/system.h>
29#include <asm/page.h>
30#include <asm/pgalloc.h>
31#include <asm/pgtable.h>
32#include <asm/oplib.h>
33#include <asm/iommu.h>
34#include <asm/io.h>
35#include <asm/uaccess.h>
36#include <asm/mmu_context.h>
37#include <asm/tlbflush.h>
38#include <asm/dma.h>
39#include <asm/starfire.h>
40#include <asm/tlb.h>
41#include <asm/spitfire.h>
42#include <asm/sections.h>
David S. Miller517af332006-02-01 15:55:21 -080043#include <asm/tsb.h>
David S. Miller481295f2006-02-07 21:51:08 -080044#include <asm/hypervisor.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070045
46extern void device_scan(void);
47
David S. Miller13edad72005-09-29 17:58:26 -070048#define MAX_BANKS 32
David S. Miller10147572005-09-28 21:46:43 -070049
David S. Miller13edad72005-09-29 17:58:26 -070050static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
51static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
52static int pavail_ents __initdata;
53static int pavail_rescan_ents __initdata;
David S. Miller10147572005-09-28 21:46:43 -070054
David S. Miller13edad72005-09-29 17:58:26 -070055static int cmp_p64(const void *a, const void *b)
56{
57 const struct linux_prom64_registers *x = a, *y = b;
58
59 if (x->phys_addr > y->phys_addr)
60 return 1;
61 if (x->phys_addr < y->phys_addr)
62 return -1;
63 return 0;
64}
65
66static void __init read_obp_memory(const char *property,
67 struct linux_prom64_registers *regs,
68 int *num_ents)
69{
70 int node = prom_finddevice("/memory");
71 int prop_size = prom_getproplen(node, property);
72 int ents, ret, i;
73
74 ents = prop_size / sizeof(struct linux_prom64_registers);
75 if (ents > MAX_BANKS) {
76 prom_printf("The machine has more %s property entries than "
77 "this kernel can support (%d).\n",
78 property, MAX_BANKS);
79 prom_halt();
80 }
81
82 ret = prom_getproperty(node, property, (char *) regs, prop_size);
83 if (ret == -1) {
84 prom_printf("Couldn't get %s property from /memory.\n");
85 prom_halt();
86 }
87
88 *num_ents = ents;
89
90 /* Sanitize what we got from the firmware, by page aligning
91 * everything.
92 */
93 for (i = 0; i < ents; i++) {
94 unsigned long base, size;
95
96 base = regs[i].phys_addr;
97 size = regs[i].reg_size;
98
99 size &= PAGE_MASK;
100 if (base & ~PAGE_MASK) {
101 unsigned long new_base = PAGE_ALIGN(base);
102
103 size -= new_base - base;
104 if ((long) size < 0L)
105 size = 0UL;
106 base = new_base;
107 }
108 regs[i].phys_addr = base;
109 regs[i].reg_size = size;
110 }
David S. Millerc9c10832005-10-12 12:22:46 -0700111 sort(regs, ents, sizeof(struct linux_prom64_registers),
David S. Miller13edad72005-09-29 17:58:26 -0700112 cmp_p64, NULL);
113}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700114
David S. Miller2bdb3cb2005-09-22 01:08:57 -0700115unsigned long *sparc64_valid_addr_bitmap __read_mostly;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700116
117/* Ugly, but necessary... -DaveM */
David S. Miller1ac4f5e2005-09-21 21:49:32 -0700118unsigned long phys_base __read_mostly;
119unsigned long kern_base __read_mostly;
120unsigned long kern_size __read_mostly;
121unsigned long pfn_base __read_mostly;
David S. Millerc4bce902006-02-11 21:57:54 -0800122unsigned long kern_linear_pte_xor __read_mostly;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700123
Linus Torvalds1da177e2005-04-16 15:20:36 -0700124/* get_new_mmu_context() uses "cache + 1". */
125DEFINE_SPINLOCK(ctx_alloc_lock);
126unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
127#define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
128unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
129
130/* References to special section boundaries */
131extern char _start[], _end[];
132
133/* Initial ramdisk setup */
134extern unsigned long sparc_ramdisk_image64;
135extern unsigned int sparc_ramdisk_image;
136extern unsigned int sparc_ramdisk_size;
137
David S. Miller1ac4f5e2005-09-21 21:49:32 -0700138struct page *mem_map_zero __read_mostly;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700139
David S. Miller0835ae02005-10-04 15:23:20 -0700140unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
141
142unsigned long sparc64_kern_pri_context __read_mostly;
143unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
144unsigned long sparc64_kern_sec_context __read_mostly;
145
Linus Torvalds1da177e2005-04-16 15:20:36 -0700146int bigkernel = 0;
147
David S. Miller3c936462006-01-31 18:30:27 -0800148kmem_cache_t *pgtable_cache __read_mostly;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700149
David S. Miller3c936462006-01-31 18:30:27 -0800150static void zero_ctor(void *addr, kmem_cache_t *cache, unsigned long flags)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700151{
David S. Miller3c936462006-01-31 18:30:27 -0800152 clear_page(addr);
153}
154
155void pgtable_cache_init(void)
156{
157 pgtable_cache = kmem_cache_create("pgtable_cache",
158 PAGE_SIZE, PAGE_SIZE,
159 SLAB_HWCACHE_ALIGN |
160 SLAB_MUST_HWCACHE_ALIGN,
161 zero_ctor,
162 NULL);
163 if (!pgtable_cache) {
164 prom_printf("pgtable_cache_init(): Could not create!\n");
165 prom_halt();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700166 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700167}
168
169#ifdef CONFIG_DEBUG_DCFLUSH
170atomic_t dcpage_flushes = ATOMIC_INIT(0);
171#ifdef CONFIG_SMP
172atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
173#endif
174#endif
175
176__inline__ void flush_dcache_page_impl(struct page *page)
177{
178#ifdef CONFIG_DEBUG_DCFLUSH
179 atomic_inc(&dcpage_flushes);
180#endif
181
182#ifdef DCACHE_ALIASING_POSSIBLE
183 __flush_dcache_page(page_address(page),
184 ((tlb_type == spitfire) &&
185 page_mapping(page) != NULL));
186#else
187 if (page_mapping(page) != NULL &&
188 tlb_type == spitfire)
189 __flush_icache_page(__pa(page_address(page)));
190#endif
191}
192
193#define PG_dcache_dirty PG_arch_1
David S. Miller48b0e542005-07-27 16:08:44 -0700194#define PG_dcache_cpu_shift 24
195#define PG_dcache_cpu_mask (256 - 1)
196
197#if NR_CPUS > 256
198#error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus
199#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700200
201#define dcache_dirty_cpu(page) \
David S. Miller48b0e542005-07-27 16:08:44 -0700202 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700203
204static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
205{
206 unsigned long mask = this_cpu;
David S. Miller48b0e542005-07-27 16:08:44 -0700207 unsigned long non_cpu_bits;
208
209 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
210 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
211
Linus Torvalds1da177e2005-04-16 15:20:36 -0700212 __asm__ __volatile__("1:\n\t"
213 "ldx [%2], %%g7\n\t"
214 "and %%g7, %1, %%g1\n\t"
215 "or %%g1, %0, %%g1\n\t"
216 "casx [%2], %%g7, %%g1\n\t"
217 "cmp %%g7, %%g1\n\t"
David S. Millerb445e262005-06-27 15:42:04 -0700218 "membar #StoreLoad | #StoreStore\n\t"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700219 "bne,pn %%xcc, 1b\n\t"
David S. Millerb445e262005-06-27 15:42:04 -0700220 " nop"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700221 : /* no outputs */
222 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
223 : "g1", "g7");
224}
225
226static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
227{
228 unsigned long mask = (1UL << PG_dcache_dirty);
229
230 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
231 "1:\n\t"
232 "ldx [%2], %%g7\n\t"
David S. Miller48b0e542005-07-27 16:08:44 -0700233 "srlx %%g7, %4, %%g1\n\t"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700234 "and %%g1, %3, %%g1\n\t"
235 "cmp %%g1, %0\n\t"
236 "bne,pn %%icc, 2f\n\t"
237 " andn %%g7, %1, %%g1\n\t"
238 "casx [%2], %%g7, %%g1\n\t"
239 "cmp %%g7, %%g1\n\t"
David S. Millerb445e262005-06-27 15:42:04 -0700240 "membar #StoreLoad | #StoreStore\n\t"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700241 "bne,pn %%xcc, 1b\n\t"
David S. Millerb445e262005-06-27 15:42:04 -0700242 " nop\n"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700243 "2:"
244 : /* no outputs */
245 : "r" (cpu), "r" (mask), "r" (&page->flags),
David S. Miller48b0e542005-07-27 16:08:44 -0700246 "i" (PG_dcache_cpu_mask),
247 "i" (PG_dcache_cpu_shift)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700248 : "g1", "g7");
249}
250
David S. Miller517af332006-02-01 15:55:21 -0800251static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
252{
253 unsigned long tsb_addr = (unsigned long) ent;
254
David S. Miller3b3ab2e2006-02-17 09:54:42 -0800255 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
David S. Miller517af332006-02-01 15:55:21 -0800256 tsb_addr = __pa(tsb_addr);
257
258 __tsb_insert(tsb_addr, tag, pte);
259}
260
David S. Millerc4bce902006-02-11 21:57:54 -0800261unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
262unsigned long _PAGE_SZBITS __read_mostly;
263
Linus Torvalds1da177e2005-04-16 15:20:36 -0700264void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
265{
David S. Millerbd407912006-01-31 18:31:38 -0800266 struct mm_struct *mm;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700267 struct page *page;
268 unsigned long pfn;
269 unsigned long pg_flags;
270
271 pfn = pte_pfn(pte);
272 if (pfn_valid(pfn) &&
273 (page = pfn_to_page(pfn), page_mapping(page)) &&
274 ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
David S. Miller48b0e542005-07-27 16:08:44 -0700275 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
276 PG_dcache_cpu_mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700277 int this_cpu = get_cpu();
278
279 /* This is just to optimize away some function calls
280 * in the SMP case.
281 */
282 if (cpu == this_cpu)
283 flush_dcache_page_impl(page);
284 else
285 smp_flush_dcache_page_impl(page, cpu);
286
287 clear_dcache_dirty_cpu(page, cpu);
288
289 put_cpu();
290 }
David S. Millerbd407912006-01-31 18:31:38 -0800291
292 mm = vma->vm_mm;
David S. Millerb70c0fa2006-01-31 18:32:04 -0800293 if ((pte_val(pte) & _PAGE_ALL_SZ_BITS) == _PAGE_SZBITS) {
294 struct tsb *tsb;
295 unsigned long tag;
296
297 tsb = &mm->context.tsb[(address >> PAGE_SHIFT) &
298 (mm->context.tsb_nentries - 1UL)];
299 tag = (address >> 22UL) | CTX_HWBITS(mm->context) << 48UL;
300 tsb_insert(tsb, tag, pte_val(pte));
301 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700302}
303
304void flush_dcache_page(struct page *page)
305{
David S. Millera9546f52005-04-17 18:03:09 -0700306 struct address_space *mapping;
307 int this_cpu;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700308
David S. Millera9546f52005-04-17 18:03:09 -0700309 /* Do not bother with the expensive D-cache flush if it
310 * is merely the zero page. The 'bigcore' testcase in GDB
311 * causes this case to run millions of times.
312 */
313 if (page == ZERO_PAGE(0))
314 return;
315
316 this_cpu = get_cpu();
317
318 mapping = page_mapping(page);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700319 if (mapping && !mapping_mapped(mapping)) {
David S. Millera9546f52005-04-17 18:03:09 -0700320 int dirty = test_bit(PG_dcache_dirty, &page->flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700321 if (dirty) {
David S. Millera9546f52005-04-17 18:03:09 -0700322 int dirty_cpu = dcache_dirty_cpu(page);
323
Linus Torvalds1da177e2005-04-16 15:20:36 -0700324 if (dirty_cpu == this_cpu)
325 goto out;
326 smp_flush_dcache_page_impl(page, dirty_cpu);
327 }
328 set_dcache_dirty(page, this_cpu);
329 } else {
330 /* We could delay the flush for the !page_mapping
331 * case too. But that case is for exec env/arg
332 * pages and those are %99 certainly going to get
333 * faulted into the tlb (and thus flushed) anyways.
334 */
335 flush_dcache_page_impl(page);
336 }
337
338out:
339 put_cpu();
340}
341
Prasanna S Panchamukhi05e14cb2005-09-06 15:19:30 -0700342void __kprobes flush_icache_range(unsigned long start, unsigned long end)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700343{
David S. Millera43fe0e2006-02-04 03:10:53 -0800344 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700345 if (tlb_type == spitfire) {
346 unsigned long kaddr;
347
348 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
349 __flush_icache_page(__get_phys(kaddr));
350 }
351}
352
353unsigned long page_to_pfn(struct page *page)
354{
355 return (unsigned long) ((page - mem_map) + pfn_base);
356}
357
358struct page *pfn_to_page(unsigned long pfn)
359{
360 return (mem_map + (pfn - pfn_base));
361}
362
363void show_mem(void)
364{
365 printk("Mem-info:\n");
366 show_free_areas();
367 printk("Free swap: %6ldkB\n",
368 nr_swap_pages << (PAGE_SHIFT-10));
369 printk("%ld pages of RAM\n", num_physpages);
370 printk("%d free pages\n", nr_free_pages());
Linus Torvalds1da177e2005-04-16 15:20:36 -0700371}
372
373void mmu_info(struct seq_file *m)
374{
375 if (tlb_type == cheetah)
376 seq_printf(m, "MMU Type\t: Cheetah\n");
377 else if (tlb_type == cheetah_plus)
378 seq_printf(m, "MMU Type\t: Cheetah+\n");
379 else if (tlb_type == spitfire)
380 seq_printf(m, "MMU Type\t: Spitfire\n");
David S. Millera43fe0e2006-02-04 03:10:53 -0800381 else if (tlb_type == hypervisor)
382 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700383 else
384 seq_printf(m, "MMU Type\t: ???\n");
385
386#ifdef CONFIG_DEBUG_DCFLUSH
387 seq_printf(m, "DCPageFlushes\t: %d\n",
388 atomic_read(&dcpage_flushes));
389#ifdef CONFIG_SMP
390 seq_printf(m, "DCPageFlushesXC\t: %d\n",
391 atomic_read(&dcpage_flushes_xcall));
392#endif /* CONFIG_SMP */
393#endif /* CONFIG_DEBUG_DCFLUSH */
394}
395
396struct linux_prom_translation {
397 unsigned long virt;
398 unsigned long size;
399 unsigned long data;
400};
David S. Millerc9c10832005-10-12 12:22:46 -0700401
402/* Exported for kernel TLB miss handling in ktlb.S */
403struct linux_prom_translation prom_trans[512] __read_mostly;
404unsigned int prom_trans_ents __read_mostly;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700405
Linus Torvalds1da177e2005-04-16 15:20:36 -0700406/* Exported for SMP bootup purposes. */
407unsigned long kern_locked_tte_data;
408
David S. Miller405599b2005-09-22 00:12:35 -0700409/* The obp translations are saved based on 8k pagesize, since obp can
410 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
David S. Miller74bf4312006-01-31 18:29:18 -0800411 * HI_OBP_ADDRESS range are handled in ktlb.S.
David S. Miller405599b2005-09-22 00:12:35 -0700412 */
David S. Miller5085b4a2005-09-22 00:45:41 -0700413static inline int in_obp_range(unsigned long vaddr)
414{
415 return (vaddr >= LOW_OBP_ADDRESS &&
416 vaddr < HI_OBP_ADDRESS);
417}
418
David S. Millerc9c10832005-10-12 12:22:46 -0700419static int cmp_ptrans(const void *a, const void *b)
David S. Miller405599b2005-09-22 00:12:35 -0700420{
David S. Millerc9c10832005-10-12 12:22:46 -0700421 const struct linux_prom_translation *x = a, *y = b;
David S. Miller405599b2005-09-22 00:12:35 -0700422
David S. Millerc9c10832005-10-12 12:22:46 -0700423 if (x->virt > y->virt)
424 return 1;
425 if (x->virt < y->virt)
426 return -1;
427 return 0;
David S. Miller405599b2005-09-22 00:12:35 -0700428}
429
David S. Millerc9c10832005-10-12 12:22:46 -0700430/* Read OBP translations property into 'prom_trans[]'. */
David S. Miller9ad98c52005-10-05 15:12:00 -0700431static void __init read_obp_translations(void)
David S. Miller405599b2005-09-22 00:12:35 -0700432{
David S. Millerc9c10832005-10-12 12:22:46 -0700433 int n, node, ents, first, last, i;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700434
435 node = prom_finddevice("/virtual-memory");
436 n = prom_getproplen(node, "translations");
David S. Miller405599b2005-09-22 00:12:35 -0700437 if (unlikely(n == 0 || n == -1)) {
David S. Millerb206fc42005-09-21 22:31:13 -0700438 prom_printf("prom_mappings: Couldn't get size.\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700439 prom_halt();
440 }
David S. Miller405599b2005-09-22 00:12:35 -0700441 if (unlikely(n > sizeof(prom_trans))) {
442 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700443 prom_halt();
444 }
David S. Miller405599b2005-09-22 00:12:35 -0700445
David S. Millerb206fc42005-09-21 22:31:13 -0700446 if ((n = prom_getproperty(node, "translations",
David S. Miller405599b2005-09-22 00:12:35 -0700447 (char *)&prom_trans[0],
448 sizeof(prom_trans))) == -1) {
David S. Millerb206fc42005-09-21 22:31:13 -0700449 prom_printf("prom_mappings: Couldn't get property.\n");
450 prom_halt();
451 }
David S. Miller9ad98c52005-10-05 15:12:00 -0700452
David S. Millerb206fc42005-09-21 22:31:13 -0700453 n = n / sizeof(struct linux_prom_translation);
David S. Miller9ad98c52005-10-05 15:12:00 -0700454
David S. Millerc9c10832005-10-12 12:22:46 -0700455 ents = n;
456
457 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
458 cmp_ptrans, NULL);
459
460 /* Now kick out all the non-OBP entries. */
461 for (i = 0; i < ents; i++) {
462 if (in_obp_range(prom_trans[i].virt))
463 break;
464 }
465 first = i;
466 for (; i < ents; i++) {
467 if (!in_obp_range(prom_trans[i].virt))
468 break;
469 }
470 last = i;
471
472 for (i = 0; i < (last - first); i++) {
473 struct linux_prom_translation *src = &prom_trans[i + first];
474 struct linux_prom_translation *dest = &prom_trans[i];
475
476 *dest = *src;
477 }
478 for (; i < ents; i++) {
479 struct linux_prom_translation *dest = &prom_trans[i];
480 dest->virt = dest->size = dest->data = 0x0UL;
481 }
482
483 prom_trans_ents = last - first;
484
485 if (tlb_type == spitfire) {
486 /* Clear diag TTE bits. */
487 for (i = 0; i < prom_trans_ents; i++)
488 prom_trans[i].data &= ~0x0003fe0000000000UL;
489 }
David S. Miller405599b2005-09-22 00:12:35 -0700490}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700491
David S. Millerd82ace72006-02-09 02:52:44 -0800492static void __init hypervisor_tlb_lock(unsigned long vaddr,
493 unsigned long pte,
494 unsigned long mmu)
495{
David S. Miller164c2202006-02-09 22:57:21 -0800496 register unsigned long func asm("%o5");
497 register unsigned long arg0 asm("%o0");
498 register unsigned long arg1 asm("%o1");
499 register unsigned long arg2 asm("%o2");
500 register unsigned long arg3 asm("%o3");
David S. Millerd82ace72006-02-09 02:52:44 -0800501
502 func = HV_FAST_MMU_MAP_PERM_ADDR;
503 arg0 = vaddr;
504 arg1 = 0;
505 arg2 = pte;
506 arg3 = mmu;
507 __asm__ __volatile__("ta 0x80"
508 : "=&r" (func), "=&r" (arg0),
509 "=&r" (arg1), "=&r" (arg2),
510 "=&r" (arg3)
511 : "0" (func), "1" (arg0), "2" (arg1),
512 "3" (arg2), "4" (arg3));
David S. Miller12e126a2006-02-17 14:40:30 -0800513 if (arg0 != 0) {
514 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
515 "errors with %lx\n", vaddr, 0, pte, mmu, arg0);
516 prom_halt();
517 }
David S. Millerd82ace72006-02-09 02:52:44 -0800518}
519
David S. Millerc4bce902006-02-11 21:57:54 -0800520static unsigned long kern_large_tte(unsigned long paddr);
521
David S. Miller898cf0e2005-09-23 11:59:44 -0700522static void __init remap_kernel(void)
David S. Miller405599b2005-09-22 00:12:35 -0700523{
524 unsigned long phys_page, tte_vaddr, tte_data;
David S. Miller405599b2005-09-22 00:12:35 -0700525 int tlb_ent = sparc64_highest_locked_tlbent();
526
Linus Torvalds1da177e2005-04-16 15:20:36 -0700527 tte_vaddr = (unsigned long) KERNBASE;
David S. Millerbff06d52005-09-22 20:11:33 -0700528 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
David S. Millerc4bce902006-02-11 21:57:54 -0800529 tte_data = kern_large_tte(phys_page);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700530
531 kern_locked_tte_data = tte_data;
532
David S. Millerd82ace72006-02-09 02:52:44 -0800533 /* Now lock us into the TLBs via Hypervisor or OBP. */
534 if (tlb_type == hypervisor) {
535 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
536 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
537 if (bigkernel) {
538 tte_vaddr += 0x400000;
539 tte_data += 0x400000;
540 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
541 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
542 }
543 } else {
544 prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
545 prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
546 if (bigkernel) {
547 tlb_ent -= 1;
548 prom_dtlb_load(tlb_ent,
549 tte_data + 0x400000,
550 tte_vaddr + 0x400000);
551 prom_itlb_load(tlb_ent,
552 tte_data + 0x400000,
553 tte_vaddr + 0x400000);
554 }
555 sparc64_highest_unlocked_tlb_ent = tlb_ent - 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700556 }
David S. Miller0835ae02005-10-04 15:23:20 -0700557 if (tlb_type == cheetah_plus) {
558 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
559 CTX_CHEETAH_PLUS_NUC);
560 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
561 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
562 }
David S. Miller405599b2005-09-22 00:12:35 -0700563}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700564
David S. Miller405599b2005-09-22 00:12:35 -0700565
David S. Millerc9c10832005-10-12 12:22:46 -0700566static void __init inherit_prom_mappings(void)
David S. Miller9ad98c52005-10-05 15:12:00 -0700567{
568 read_obp_translations();
David S. Miller405599b2005-09-22 00:12:35 -0700569
570 /* Now fixup OBP's idea about where we really are mapped. */
571 prom_printf("Remapping the kernel... ");
572 remap_kernel();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700573 prom_printf("done.\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700574}
575
Linus Torvalds1da177e2005-04-16 15:20:36 -0700576void prom_world(int enter)
577{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700578 if (!enter)
579 set_fs((mm_segment_t) { get_thread_current_ds() });
580
David S. Miller3487d1d2006-01-31 18:33:25 -0800581 __asm__ __volatile__("flushw");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700582}
583
584#ifdef DCACHE_ALIASING_POSSIBLE
585void __flush_dcache_range(unsigned long start, unsigned long end)
586{
587 unsigned long va;
588
589 if (tlb_type == spitfire) {
590 int n = 0;
591
592 for (va = start; va < end; va += 32) {
593 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
594 if (++n >= 512)
595 break;
596 }
David S. Millera43fe0e2006-02-04 03:10:53 -0800597 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700598 start = __pa(start);
599 end = __pa(end);
600 for (va = start; va < end; va += 32)
601 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
602 "membar #Sync"
603 : /* no outputs */
604 : "r" (va),
605 "i" (ASI_DCACHE_INVALIDATE));
606 }
607}
608#endif /* DCACHE_ALIASING_POSSIBLE */
609
Linus Torvalds1da177e2005-04-16 15:20:36 -0700610/* Caller does TLB context flushing on local CPU if necessary.
611 * The caller also ensures that CTX_VALID(mm->context) is false.
612 *
613 * We must be careful about boundary cases so that we never
614 * let the user have CTX 0 (nucleus) or we ever use a CTX
615 * version of zero (and thus NO_CONTEXT would not be caught
616 * by version mis-match tests in mmu_context.h).
617 */
618void get_new_mmu_context(struct mm_struct *mm)
619{
620 unsigned long ctx, new_ctx;
621 unsigned long orig_pgsz_bits;
622
623
624 spin_lock(&ctx_alloc_lock);
625 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
626 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
627 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
628 if (new_ctx >= (1 << CTX_NR_BITS)) {
629 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
630 if (new_ctx >= ctx) {
631 int i;
632 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
633 CTX_FIRST_VERSION;
634 if (new_ctx == 1)
635 new_ctx = CTX_FIRST_VERSION;
636
637 /* Don't call memset, for 16 entries that's just
638 * plain silly...
639 */
640 mmu_context_bmap[0] = 3;
641 mmu_context_bmap[1] = 0;
642 mmu_context_bmap[2] = 0;
643 mmu_context_bmap[3] = 0;
644 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
645 mmu_context_bmap[i + 0] = 0;
646 mmu_context_bmap[i + 1] = 0;
647 mmu_context_bmap[i + 2] = 0;
648 mmu_context_bmap[i + 3] = 0;
649 }
650 goto out;
651 }
652 }
653 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
654 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
655out:
656 tlb_context_cache = new_ctx;
657 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
658 spin_unlock(&ctx_alloc_lock);
659}
660
Linus Torvalds1da177e2005-04-16 15:20:36 -0700661void sparc_ultra_dump_itlb(void)
662{
663 int slot;
664
665 if (tlb_type == spitfire) {
666 printk ("Contents of itlb: ");
667 for (slot = 0; slot < 14; slot++) printk (" ");
668 printk ("%2x:%016lx,%016lx\n",
669 0,
670 spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
671 for (slot = 1; slot < 64; slot+=3) {
672 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
673 slot,
674 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
675 slot+1,
676 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
677 slot+2,
678 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
679 }
680 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
681 printk ("Contents of itlb0:\n");
682 for (slot = 0; slot < 16; slot+=2) {
683 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
684 slot,
685 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
686 slot+1,
687 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
688 }
689 printk ("Contents of itlb2:\n");
690 for (slot = 0; slot < 128; slot+=2) {
691 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
692 slot,
693 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
694 slot+1,
695 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
696 }
697 }
698}
699
700void sparc_ultra_dump_dtlb(void)
701{
702 int slot;
703
704 if (tlb_type == spitfire) {
705 printk ("Contents of dtlb: ");
706 for (slot = 0; slot < 14; slot++) printk (" ");
707 printk ("%2x:%016lx,%016lx\n", 0,
708 spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
709 for (slot = 1; slot < 64; slot+=3) {
710 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
711 slot,
712 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
713 slot+1,
714 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
715 slot+2,
716 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
717 }
718 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
719 printk ("Contents of dtlb0:\n");
720 for (slot = 0; slot < 16; slot+=2) {
721 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
722 slot,
723 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
724 slot+1,
725 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
726 }
727 printk ("Contents of dtlb2:\n");
728 for (slot = 0; slot < 512; slot+=2) {
729 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
730 slot,
731 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
732 slot+1,
733 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
734 }
735 if (tlb_type == cheetah_plus) {
736 printk ("Contents of dtlb3:\n");
737 for (slot = 0; slot < 512; slot+=2) {
738 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
739 slot,
740 cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
741 slot+1,
742 cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
743 }
744 }
745 }
746}
747
748extern unsigned long cmdline_memory_size;
749
750unsigned long __init bootmem_init(unsigned long *pages_avail)
751{
752 unsigned long bootmap_size, start_pfn, end_pfn;
753 unsigned long end_of_phys_memory = 0UL;
754 unsigned long bootmap_pfn, bytes_avail, size;
755 int i;
756
757#ifdef CONFIG_DEBUG_BOOTMEM
David S. Miller13edad72005-09-29 17:58:26 -0700758 prom_printf("bootmem_init: Scan pavail, ");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700759#endif
760
761 bytes_avail = 0UL;
David S. Miller13edad72005-09-29 17:58:26 -0700762 for (i = 0; i < pavail_ents; i++) {
763 end_of_phys_memory = pavail[i].phys_addr +
764 pavail[i].reg_size;
765 bytes_avail += pavail[i].reg_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700766 if (cmdline_memory_size) {
767 if (bytes_avail > cmdline_memory_size) {
768 unsigned long slack = bytes_avail - cmdline_memory_size;
769
770 bytes_avail -= slack;
771 end_of_phys_memory -= slack;
772
David S. Miller13edad72005-09-29 17:58:26 -0700773 pavail[i].reg_size -= slack;
774 if ((long)pavail[i].reg_size <= 0L) {
775 pavail[i].phys_addr = 0xdeadbeefUL;
776 pavail[i].reg_size = 0UL;
777 pavail_ents = i;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700778 } else {
David S. Miller13edad72005-09-29 17:58:26 -0700779 pavail[i+1].reg_size = 0Ul;
780 pavail[i+1].phys_addr = 0xdeadbeefUL;
781 pavail_ents = i + 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700782 }
783 break;
784 }
785 }
786 }
787
788 *pages_avail = bytes_avail >> PAGE_SHIFT;
789
790 /* Start with page aligned address of last symbol in kernel
791 * image. The kernel is hard mapped below PAGE_OFFSET in a
792 * 4MB locked TLB translation.
793 */
794 start_pfn = PAGE_ALIGN(kern_base + kern_size) >> PAGE_SHIFT;
795
796 bootmap_pfn = start_pfn;
797
798 end_pfn = end_of_phys_memory >> PAGE_SHIFT;
799
800#ifdef CONFIG_BLK_DEV_INITRD
801 /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
802 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
803 unsigned long ramdisk_image = sparc_ramdisk_image ?
804 sparc_ramdisk_image : sparc_ramdisk_image64;
805 if (ramdisk_image >= (unsigned long)_end - 2 * PAGE_SIZE)
806 ramdisk_image -= KERNBASE;
807 initrd_start = ramdisk_image + phys_base;
808 initrd_end = initrd_start + sparc_ramdisk_size;
809 if (initrd_end > end_of_phys_memory) {
810 printk(KERN_CRIT "initrd extends beyond end of memory "
811 "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
812 initrd_end, end_of_phys_memory);
813 initrd_start = 0;
814 }
815 if (initrd_start) {
816 if (initrd_start >= (start_pfn << PAGE_SHIFT) &&
817 initrd_start < (start_pfn << PAGE_SHIFT) + 2 * PAGE_SIZE)
818 bootmap_pfn = PAGE_ALIGN (initrd_end) >> PAGE_SHIFT;
819 }
820 }
821#endif
822 /* Initialize the boot-time allocator. */
823 max_pfn = max_low_pfn = end_pfn;
824 min_low_pfn = pfn_base;
825
826#ifdef CONFIG_DEBUG_BOOTMEM
827 prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
828 min_low_pfn, bootmap_pfn, max_low_pfn);
829#endif
830 bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn, pfn_base, end_pfn);
831
Linus Torvalds1da177e2005-04-16 15:20:36 -0700832 /* Now register the available physical memory with the
833 * allocator.
834 */
David S. Miller13edad72005-09-29 17:58:26 -0700835 for (i = 0; i < pavail_ents; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700836#ifdef CONFIG_DEBUG_BOOTMEM
David S. Miller13edad72005-09-29 17:58:26 -0700837 prom_printf("free_bootmem(pavail:%d): base[%lx] size[%lx]\n",
838 i, pavail[i].phys_addr, pavail[i].reg_size);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700839#endif
David S. Miller13edad72005-09-29 17:58:26 -0700840 free_bootmem(pavail[i].phys_addr, pavail[i].reg_size);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700841 }
842
843#ifdef CONFIG_BLK_DEV_INITRD
844 if (initrd_start) {
845 size = initrd_end - initrd_start;
846
847 /* Resert the initrd image area. */
848#ifdef CONFIG_DEBUG_BOOTMEM
849 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
850 initrd_start, initrd_end);
851#endif
852 reserve_bootmem(initrd_start, size);
853 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
854
855 initrd_start += PAGE_OFFSET;
856 initrd_end += PAGE_OFFSET;
857 }
858#endif
859 /* Reserve the kernel text/data/bss. */
860#ifdef CONFIG_DEBUG_BOOTMEM
861 prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
862#endif
863 reserve_bootmem(kern_base, kern_size);
864 *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
865
866 /* Reserve the bootmem map. We do not account for it
867 * in pages_avail because we will release that memory
868 * in free_all_bootmem.
869 */
870 size = bootmap_size;
871#ifdef CONFIG_DEBUG_BOOTMEM
872 prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
873 (bootmap_pfn << PAGE_SHIFT), size);
874#endif
875 reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
876 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
877
878 return end_pfn;
879}
880
David S. Miller56425302005-09-25 16:46:57 -0700881#ifdef CONFIG_DEBUG_PAGEALLOC
882static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend, pgprot_t prot)
883{
884 unsigned long vstart = PAGE_OFFSET + pstart;
885 unsigned long vend = PAGE_OFFSET + pend;
886 unsigned long alloc_bytes = 0UL;
887
888 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
David S. Miller13edad72005-09-29 17:58:26 -0700889 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
David S. Miller56425302005-09-25 16:46:57 -0700890 vstart, vend);
891 prom_halt();
892 }
893
894 while (vstart < vend) {
895 unsigned long this_end, paddr = __pa(vstart);
896 pgd_t *pgd = pgd_offset_k(vstart);
897 pud_t *pud;
898 pmd_t *pmd;
899 pte_t *pte;
900
901 pud = pud_offset(pgd, vstart);
902 if (pud_none(*pud)) {
903 pmd_t *new;
904
905 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
906 alloc_bytes += PAGE_SIZE;
907 pud_populate(&init_mm, pud, new);
908 }
909
910 pmd = pmd_offset(pud, vstart);
911 if (!pmd_present(*pmd)) {
912 pte_t *new;
913
914 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
915 alloc_bytes += PAGE_SIZE;
916 pmd_populate_kernel(&init_mm, pmd, new);
917 }
918
919 pte = pte_offset_kernel(pmd, vstart);
920 this_end = (vstart + PMD_SIZE) & PMD_MASK;
921 if (this_end > vend)
922 this_end = vend;
923
924 while (vstart < this_end) {
925 pte_val(*pte) = (paddr | pgprot_val(prot));
926
927 vstart += PAGE_SIZE;
928 paddr += PAGE_SIZE;
929 pte++;
930 }
931 }
932
933 return alloc_bytes;
934}
935
David S. Miller13edad72005-09-29 17:58:26 -0700936static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
937static int pall_ents __initdata;
938
David S. Miller56425302005-09-25 16:46:57 -0700939extern unsigned int kvmap_linear_patch[1];
940
941static void __init kernel_physical_mapping_init(void)
942{
David S. Miller13edad72005-09-29 17:58:26 -0700943 unsigned long i, mem_alloced = 0UL;
David S. Miller56425302005-09-25 16:46:57 -0700944
David S. Miller13edad72005-09-29 17:58:26 -0700945 read_obp_memory("reg", &pall[0], &pall_ents);
946
947 for (i = 0; i < pall_ents; i++) {
David S. Miller56425302005-09-25 16:46:57 -0700948 unsigned long phys_start, phys_end;
949
David S. Miller13edad72005-09-29 17:58:26 -0700950 phys_start = pall[i].phys_addr;
951 phys_end = phys_start + pall[i].reg_size;
David S. Miller56425302005-09-25 16:46:57 -0700952 mem_alloced += kernel_map_range(phys_start, phys_end,
953 PAGE_KERNEL);
David S. Miller56425302005-09-25 16:46:57 -0700954 }
955
956 printk("Allocated %ld bytes for kernel page tables.\n",
957 mem_alloced);
958
959 kvmap_linear_patch[0] = 0x01000000; /* nop */
960 flushi(&kvmap_linear_patch[0]);
961
962 __flush_tlb_all();
963}
964
965void kernel_map_pages(struct page *page, int numpages, int enable)
966{
967 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
968 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
969
970 kernel_map_range(phys_start, phys_end,
971 (enable ? PAGE_KERNEL : __pgprot(0)));
972
David S. Miller74bf4312006-01-31 18:29:18 -0800973 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
974 PAGE_OFFSET + phys_end);
975
David S. Miller56425302005-09-25 16:46:57 -0700976 /* we should perform an IPI and flush all tlbs,
977 * but that can deadlock->flush only current cpu.
978 */
979 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
980 PAGE_OFFSET + phys_end);
981}
982#endif
983
David S. Miller10147572005-09-28 21:46:43 -0700984unsigned long __init find_ecache_flush_span(unsigned long size)
985{
David S. Miller13edad72005-09-29 17:58:26 -0700986 int i;
David S. Miller10147572005-09-28 21:46:43 -0700987
David S. Miller13edad72005-09-29 17:58:26 -0700988 for (i = 0; i < pavail_ents; i++) {
989 if (pavail[i].reg_size >= size)
990 return pavail[i].phys_addr;
David S. Miller10147572005-09-28 21:46:43 -0700991 }
992
993 return ~0UL;
994}
995
David S. Miller517af332006-02-01 15:55:21 -0800996static void __init tsb_phys_patch(void)
997{
David S. Millerd257d5d2006-02-06 23:44:37 -0800998 struct tsb_ldquad_phys_patch_entry *pquad;
David S. Miller517af332006-02-01 15:55:21 -0800999 struct tsb_phys_patch_entry *p;
1000
David S. Millerd257d5d2006-02-06 23:44:37 -08001001 pquad = &__tsb_ldquad_phys_patch;
1002 while (pquad < &__tsb_ldquad_phys_patch_end) {
1003 unsigned long addr = pquad->addr;
1004
1005 if (tlb_type == hypervisor)
1006 *(unsigned int *) addr = pquad->sun4v_insn;
1007 else
1008 *(unsigned int *) addr = pquad->sun4u_insn;
1009 wmb();
1010 __asm__ __volatile__("flush %0"
1011 : /* no outputs */
1012 : "r" (addr));
1013
1014 pquad++;
1015 }
1016
David S. Miller517af332006-02-01 15:55:21 -08001017 p = &__tsb_phys_patch;
1018 while (p < &__tsb_phys_patch_end) {
1019 unsigned long addr = p->addr;
1020
1021 *(unsigned int *) addr = p->insn;
1022 wmb();
1023 __asm__ __volatile__("flush %0"
1024 : /* no outputs */
1025 : "r" (addr));
1026
1027 p++;
1028 }
1029}
1030
David S. Miller490384e2006-02-11 14:41:18 -08001031/* Don't mark as init, we give this to the Hypervisor. */
1032static struct hv_tsb_descr ktsb_descr[2];
1033extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1034
1035static void __init sun4v_ktsb_init(void)
1036{
1037 unsigned long ktsb_pa;
1038
1039 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1040
1041 switch (PAGE_SIZE) {
1042 case 8 * 1024:
1043 default:
1044 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1045 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1046 break;
1047
1048 case 64 * 1024:
1049 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1050 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1051 break;
1052
1053 case 512 * 1024:
1054 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1055 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1056 break;
1057
1058 case 4 * 1024 * 1024:
1059 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1060 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1061 break;
1062 };
1063
David S. Miller3f19a842006-02-17 12:03:20 -08001064 ktsb_descr[0].assoc = 1;
David S. Miller490384e2006-02-11 14:41:18 -08001065 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1066 ktsb_descr[0].ctx_idx = 0;
1067 ktsb_descr[0].tsb_base = ktsb_pa;
1068 ktsb_descr[0].resv = 0;
1069
1070 /* XXX When we have a kernel large page size TSB, describe
1071 * XXX it in ktsb_descr[1] here.
1072 */
1073}
1074
1075void __cpuinit sun4v_ktsb_register(void)
1076{
1077 register unsigned long func asm("%o5");
1078 register unsigned long arg0 asm("%o0");
1079 register unsigned long arg1 asm("%o1");
1080 unsigned long pa;
1081
1082 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1083
1084 func = HV_FAST_MMU_TSB_CTX0;
1085 /* XXX set arg0 to 2 when we use ktsb_descr[1], see above XXX */
1086 arg0 = 1;
1087 arg1 = pa;
1088 __asm__ __volatile__("ta %6"
1089 : "=&r" (func), "=&r" (arg0), "=&r" (arg1)
1090 : "0" (func), "1" (arg0), "2" (arg1),
1091 "i" (HV_FAST_TRAP));
1092}
1093
Linus Torvalds1da177e2005-04-16 15:20:36 -07001094/* paging_init() sets up the page tables */
1095
1096extern void cheetah_ecache_flush_init(void);
David S. Millerd257d5d2006-02-06 23:44:37 -08001097extern void sun4v_patch_tlb_handlers(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001098
1099static unsigned long last_valid_pfn;
David S. Miller56425302005-09-25 16:46:57 -07001100pgd_t swapper_pg_dir[2048];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001101
David S. Millerc4bce902006-02-11 21:57:54 -08001102static void sun4u_pgprot_init(void);
1103static void sun4v_pgprot_init(void);
1104
Linus Torvalds1da177e2005-04-16 15:20:36 -07001105void __init paging_init(void)
1106{
David S. Miller2bdb3cb2005-09-22 01:08:57 -07001107 unsigned long end_pfn, pages_avail, shift;
David S. Miller0836a0e2005-09-28 21:38:08 -07001108 unsigned long real_end, i;
1109
David S. Miller481295f2006-02-07 21:51:08 -08001110 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1111 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1112
David S. Millerc4bce902006-02-11 21:57:54 -08001113 if (tlb_type == hypervisor)
1114 sun4v_pgprot_init();
1115 else
1116 sun4u_pgprot_init();
1117
David S. Millerd257d5d2006-02-06 23:44:37 -08001118 if (tlb_type == cheetah_plus ||
1119 tlb_type == hypervisor)
David S. Miller517af332006-02-01 15:55:21 -08001120 tsb_phys_patch();
1121
David S. Miller490384e2006-02-11 14:41:18 -08001122 if (tlb_type == hypervisor) {
David S. Millerd257d5d2006-02-06 23:44:37 -08001123 sun4v_patch_tlb_handlers();
David S. Miller490384e2006-02-11 14:41:18 -08001124 sun4v_ktsb_init();
1125 }
David S. Millerd257d5d2006-02-06 23:44:37 -08001126
David S. Miller13edad72005-09-29 17:58:26 -07001127 /* Find available physical memory... */
1128 read_obp_memory("available", &pavail[0], &pavail_ents);
David S. Miller0836a0e2005-09-28 21:38:08 -07001129
1130 phys_base = 0xffffffffffffffffUL;
David S. Miller13edad72005-09-29 17:58:26 -07001131 for (i = 0; i < pavail_ents; i++)
1132 phys_base = min(phys_base, pavail[i].phys_addr);
David S. Miller0836a0e2005-09-28 21:38:08 -07001133
David S. Miller0836a0e2005-09-28 21:38:08 -07001134 pfn_base = phys_base >> PAGE_SHIFT;
1135
Linus Torvalds1da177e2005-04-16 15:20:36 -07001136 set_bit(0, mmu_context_bmap);
1137
David S. Miller2bdb3cb2005-09-22 01:08:57 -07001138 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1139
Linus Torvalds1da177e2005-04-16 15:20:36 -07001140 real_end = (unsigned long)_end;
1141 if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1142 bigkernel = 1;
David S. Miller2bdb3cb2005-09-22 01:08:57 -07001143 if ((real_end > ((unsigned long)KERNBASE + 0x800000))) {
1144 prom_printf("paging_init: Kernel > 8MB, too large.\n");
1145 prom_halt();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001146 }
David S. Miller2bdb3cb2005-09-22 01:08:57 -07001147
1148 /* Set kernel pgd to upper alias so physical page computations
Linus Torvalds1da177e2005-04-16 15:20:36 -07001149 * work.
1150 */
1151 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1152
David S. Miller56425302005-09-25 16:46:57 -07001153 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001154
1155 /* Now can init the kernel/bad page tables. */
1156 pud_set(pud_offset(&swapper_pg_dir[0], 0),
David S. Miller56425302005-09-25 16:46:57 -07001157 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001158
David S. Millerc9c10832005-10-12 12:22:46 -07001159 inherit_prom_mappings();
David S. Miller5085b4a2005-09-22 00:45:41 -07001160
David S. Millera8b900d2006-01-31 18:33:37 -08001161 /* Ok, we can use our TLB miss and window trap handlers safely. */
1162 setup_tba();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001163
David S. Millerc9c10832005-10-12 12:22:46 -07001164 __flush_tlb_all();
David S. Miller9ad98c52005-10-05 15:12:00 -07001165
David S. Miller490384e2006-02-11 14:41:18 -08001166 if (tlb_type == hypervisor)
1167 sun4v_ktsb_register();
1168
David S. Miller2bdb3cb2005-09-22 01:08:57 -07001169 /* Setup bootmem... */
1170 pages_avail = 0;
1171 last_valid_pfn = end_pfn = bootmem_init(&pages_avail);
1172
David S. Miller56425302005-09-25 16:46:57 -07001173#ifdef CONFIG_DEBUG_PAGEALLOC
1174 kernel_physical_mapping_init();
1175#endif
1176
Linus Torvalds1da177e2005-04-16 15:20:36 -07001177 {
1178 unsigned long zones_size[MAX_NR_ZONES];
1179 unsigned long zholes_size[MAX_NR_ZONES];
1180 unsigned long npages;
1181 int znum;
1182
1183 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1184 zones_size[znum] = zholes_size[znum] = 0;
1185
1186 npages = end_pfn - pfn_base;
1187 zones_size[ZONE_DMA] = npages;
1188 zholes_size[ZONE_DMA] = npages - pages_avail;
1189
1190 free_area_init_node(0, &contig_page_data, zones_size,
1191 phys_base >> PAGE_SHIFT, zholes_size);
1192 }
1193
1194 device_scan();
1195}
1196
Linus Torvalds1da177e2005-04-16 15:20:36 -07001197static void __init taint_real_pages(void)
1198{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001199 int i;
1200
David S. Miller13edad72005-09-29 17:58:26 -07001201 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001202
David S. Miller13edad72005-09-29 17:58:26 -07001203 /* Find changes discovered in the physmem available rescan and
Linus Torvalds1da177e2005-04-16 15:20:36 -07001204 * reserve the lost portions in the bootmem maps.
1205 */
David S. Miller13edad72005-09-29 17:58:26 -07001206 for (i = 0; i < pavail_ents; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001207 unsigned long old_start, old_end;
1208
David S. Miller13edad72005-09-29 17:58:26 -07001209 old_start = pavail[i].phys_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001210 old_end = old_start +
David S. Miller13edad72005-09-29 17:58:26 -07001211 pavail[i].reg_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001212 while (old_start < old_end) {
1213 int n;
1214
David S. Miller13edad72005-09-29 17:58:26 -07001215 for (n = 0; pavail_rescan_ents; n++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001216 unsigned long new_start, new_end;
1217
David S. Miller13edad72005-09-29 17:58:26 -07001218 new_start = pavail_rescan[n].phys_addr;
1219 new_end = new_start +
1220 pavail_rescan[n].reg_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001221
1222 if (new_start <= old_start &&
1223 new_end >= (old_start + PAGE_SIZE)) {
David S. Miller13edad72005-09-29 17:58:26 -07001224 set_bit(old_start >> 22,
1225 sparc64_valid_addr_bitmap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001226 goto do_next_page;
1227 }
1228 }
1229 reserve_bootmem(old_start, PAGE_SIZE);
1230
1231 do_next_page:
1232 old_start += PAGE_SIZE;
1233 }
1234 }
1235}
1236
1237void __init mem_init(void)
1238{
1239 unsigned long codepages, datapages, initpages;
1240 unsigned long addr, last;
1241 int i;
1242
1243 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1244 i += 1;
David S. Miller2bdb3cb2005-09-22 01:08:57 -07001245 sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001246 if (sparc64_valid_addr_bitmap == NULL) {
1247 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1248 prom_halt();
1249 }
1250 memset(sparc64_valid_addr_bitmap, 0, i << 3);
1251
1252 addr = PAGE_OFFSET + kern_base;
1253 last = PAGE_ALIGN(kern_size) + addr;
1254 while (addr < last) {
1255 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1256 addr += PAGE_SIZE;
1257 }
1258
1259 taint_real_pages();
1260
1261 max_mapnr = last_valid_pfn - pfn_base;
1262 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1263
1264#ifdef CONFIG_DEBUG_BOOTMEM
1265 prom_printf("mem_init: Calling free_all_bootmem().\n");
1266#endif
1267 totalram_pages = num_physpages = free_all_bootmem() - 1;
1268
1269 /*
1270 * Set up the zero page, mark it reserved, so that page count
1271 * is not manipulated when freeing the page from user ptes.
1272 */
1273 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1274 if (mem_map_zero == NULL) {
1275 prom_printf("paging_init: Cannot alloc zero page.\n");
1276 prom_halt();
1277 }
1278 SetPageReserved(mem_map_zero);
1279
1280 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1281 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1282 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1283 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1284 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1285 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1286
1287 printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1288 nr_free_pages() << (PAGE_SHIFT-10),
1289 codepages << (PAGE_SHIFT-10),
1290 datapages << (PAGE_SHIFT-10),
1291 initpages << (PAGE_SHIFT-10),
1292 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1293
1294 if (tlb_type == cheetah || tlb_type == cheetah_plus)
1295 cheetah_ecache_flush_init();
1296}
1297
David S. Miller898cf0e2005-09-23 11:59:44 -07001298void free_initmem(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001299{
1300 unsigned long addr, initend;
1301
1302 /*
1303 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1304 */
1305 addr = PAGE_ALIGN((unsigned long)(__init_begin));
1306 initend = (unsigned long)(__init_end) & PAGE_MASK;
1307 for (; addr < initend; addr += PAGE_SIZE) {
1308 unsigned long page;
1309 struct page *p;
1310
1311 page = (addr +
1312 ((unsigned long) __va(kern_base)) -
1313 ((unsigned long) KERNBASE));
1314 memset((void *)addr, 0xcc, PAGE_SIZE);
1315 p = virt_to_page(page);
1316
1317 ClearPageReserved(p);
1318 set_page_count(p, 1);
1319 __free_page(p);
1320 num_physpages++;
1321 totalram_pages++;
1322 }
1323}
1324
1325#ifdef CONFIG_BLK_DEV_INITRD
1326void free_initrd_mem(unsigned long start, unsigned long end)
1327{
1328 if (start < end)
1329 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1330 for (; start < end; start += PAGE_SIZE) {
1331 struct page *p = virt_to_page(start);
1332
1333 ClearPageReserved(p);
1334 set_page_count(p, 1);
1335 __free_page(p);
1336 num_physpages++;
1337 totalram_pages++;
1338 }
1339}
1340#endif
David S. Millerc4bce902006-02-11 21:57:54 -08001341
David S. Millerc4bce902006-02-11 21:57:54 -08001342#define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
1343#define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
1344#define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
1345#define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
1346#define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
1347#define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
1348
1349pgprot_t PAGE_KERNEL __read_mostly;
1350EXPORT_SYMBOL(PAGE_KERNEL);
1351
1352pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
1353pgprot_t PAGE_COPY __read_mostly;
1354pgprot_t PAGE_EXEC __read_mostly;
1355unsigned long pg_iobits __read_mostly;
1356
1357unsigned long _PAGE_IE __read_mostly;
1358unsigned long _PAGE_E __read_mostly;
1359unsigned long _PAGE_CACHE __read_mostly;
1360
1361static void prot_init_common(unsigned long page_none,
1362 unsigned long page_shared,
1363 unsigned long page_copy,
1364 unsigned long page_readonly,
1365 unsigned long page_exec_bit)
1366{
1367 PAGE_COPY = __pgprot(page_copy);
1368
1369 protection_map[0x0] = __pgprot(page_none);
1370 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
1371 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
1372 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
1373 protection_map[0x4] = __pgprot(page_readonly);
1374 protection_map[0x5] = __pgprot(page_readonly);
1375 protection_map[0x6] = __pgprot(page_copy);
1376 protection_map[0x7] = __pgprot(page_copy);
1377 protection_map[0x8] = __pgprot(page_none);
1378 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
1379 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
1380 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
1381 protection_map[0xc] = __pgprot(page_readonly);
1382 protection_map[0xd] = __pgprot(page_readonly);
1383 protection_map[0xe] = __pgprot(page_shared);
1384 protection_map[0xf] = __pgprot(page_shared);
1385}
1386
1387static void __init sun4u_pgprot_init(void)
1388{
1389 unsigned long page_none, page_shared, page_copy, page_readonly;
1390 unsigned long page_exec_bit;
1391
1392 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1393 _PAGE_CACHE_4U | _PAGE_P_4U |
1394 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1395 _PAGE_EXEC_4U);
1396 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1397 _PAGE_CACHE_4U | _PAGE_P_4U |
1398 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1399 _PAGE_EXEC_4U | _PAGE_L_4U);
1400 PAGE_EXEC = __pgprot(_PAGE_EXEC_4U);
1401
1402 _PAGE_IE = _PAGE_IE_4U;
1403 _PAGE_E = _PAGE_E_4U;
1404 _PAGE_CACHE = _PAGE_CACHE_4U;
1405
1406 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
1407 __ACCESS_BITS_4U | _PAGE_E_4U);
1408
1409 kern_linear_pte_xor = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
1410 0xfffff80000000000;
1411 kern_linear_pte_xor |= (_PAGE_CP_4U | _PAGE_CV_4U |
1412 _PAGE_P_4U | _PAGE_W_4U);
1413
1414 _PAGE_SZBITS = _PAGE_SZBITS_4U;
1415 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
1416 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
1417 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
1418
1419
1420 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
1421 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1422 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
1423 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1424 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1425 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1426 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1427
1428 page_exec_bit = _PAGE_EXEC_4U;
1429
1430 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1431 page_exec_bit);
1432}
1433
1434static void __init sun4v_pgprot_init(void)
1435{
1436 unsigned long page_none, page_shared, page_copy, page_readonly;
1437 unsigned long page_exec_bit;
1438
1439 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
1440 _PAGE_CACHE_4V | _PAGE_P_4V |
1441 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
1442 _PAGE_EXEC_4V);
1443 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
1444 PAGE_EXEC = __pgprot(_PAGE_EXEC_4V);
1445
1446 _PAGE_IE = _PAGE_IE_4V;
1447 _PAGE_E = _PAGE_E_4V;
1448 _PAGE_CACHE = _PAGE_CACHE_4V;
1449
1450 kern_linear_pte_xor = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
1451 0xfffff80000000000;
1452 kern_linear_pte_xor |= (_PAGE_CP_4V | _PAGE_CV_4V |
1453 _PAGE_P_4V | _PAGE_W_4V);
1454
1455 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
1456 __ACCESS_BITS_4V | _PAGE_E_4V);
1457
1458 _PAGE_SZBITS = _PAGE_SZBITS_4V;
1459 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
1460 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
1461 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
1462 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
1463
1464 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
1465 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1466 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
1467 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1468 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1469 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1470 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1471
1472 page_exec_bit = _PAGE_EXEC_4V;
1473
1474 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1475 page_exec_bit);
1476}
1477
1478unsigned long pte_sz_bits(unsigned long sz)
1479{
1480 if (tlb_type == hypervisor) {
1481 switch (sz) {
1482 case 8 * 1024:
1483 default:
1484 return _PAGE_SZ8K_4V;
1485 case 64 * 1024:
1486 return _PAGE_SZ64K_4V;
1487 case 512 * 1024:
1488 return _PAGE_SZ512K_4V;
1489 case 4 * 1024 * 1024:
1490 return _PAGE_SZ4MB_4V;
1491 };
1492 } else {
1493 switch (sz) {
1494 case 8 * 1024:
1495 default:
1496 return _PAGE_SZ8K_4U;
1497 case 64 * 1024:
1498 return _PAGE_SZ64K_4U;
1499 case 512 * 1024:
1500 return _PAGE_SZ512K_4U;
1501 case 4 * 1024 * 1024:
1502 return _PAGE_SZ4MB_4U;
1503 };
1504 }
1505}
1506
1507pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
1508{
1509 pte_t pte;
David S. Millercf627152006-02-12 21:10:07 -08001510
1511 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
David S. Millerc4bce902006-02-11 21:57:54 -08001512 pte_val(pte) |= (((unsigned long)space) << 32);
1513 pte_val(pte) |= pte_sz_bits(page_size);
David S. Millercf627152006-02-12 21:10:07 -08001514
David S. Millerc4bce902006-02-11 21:57:54 -08001515 return pte;
1516}
1517
David S. Millerc4bce902006-02-11 21:57:54 -08001518static unsigned long kern_large_tte(unsigned long paddr)
1519{
1520 unsigned long val;
1521
1522 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
1523 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
1524 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
1525 if (tlb_type == hypervisor)
1526 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
1527 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
1528 _PAGE_EXEC_4V | _PAGE_W_4V);
1529
1530 return val | paddr;
1531}
1532
1533/*
1534 * Translate PROM's mapping we capture at boot time into physical address.
1535 * The second parameter is only set from prom_callback() invocations.
1536 */
1537unsigned long prom_virt_to_phys(unsigned long promva, int *error)
1538{
1539 unsigned long mask;
1540 int i;
1541
1542 mask = _PAGE_PADDR_4U;
1543 if (tlb_type == hypervisor)
1544 mask = _PAGE_PADDR_4V;
1545
1546 for (i = 0; i < prom_trans_ents; i++) {
1547 struct linux_prom_translation *p = &prom_trans[i];
1548
1549 if (promva >= p->virt &&
1550 promva < (p->virt + p->size)) {
1551 unsigned long base = p->data & mask;
1552
1553 if (error)
1554 *error = 0;
1555 return base + (promva & (8192 - 1));
1556 }
1557 }
1558 if (error)
1559 *error = 1;
1560 return 0UL;
1561}
1562
1563/* XXX We should kill off this ugly thing at so me point. XXX */
1564unsigned long sun4u_get_pte(unsigned long addr)
1565{
1566 pgd_t *pgdp;
1567 pud_t *pudp;
1568 pmd_t *pmdp;
1569 pte_t *ptep;
1570 unsigned long mask = _PAGE_PADDR_4U;
1571
1572 if (tlb_type == hypervisor)
1573 mask = _PAGE_PADDR_4V;
1574
1575 if (addr >= PAGE_OFFSET)
1576 return addr & mask;
1577
1578 if ((addr >= LOW_OBP_ADDRESS) && (addr < HI_OBP_ADDRESS))
1579 return prom_virt_to_phys(addr, NULL);
1580
1581 pgdp = pgd_offset_k(addr);
1582 pudp = pud_offset(pgdp, addr);
1583 pmdp = pmd_offset(pudp, addr);
1584 ptep = pte_offset_kernel(pmdp, addr);
1585
1586 return pte_val(*ptep) & mask;
1587}
1588
1589/* If not locked, zap it. */
1590void __flush_tlb_all(void)
1591{
1592 unsigned long pstate;
1593 int i;
1594
1595 __asm__ __volatile__("flushw\n\t"
1596 "rdpr %%pstate, %0\n\t"
1597 "wrpr %0, %1, %%pstate"
1598 : "=r" (pstate)
1599 : "i" (PSTATE_IE));
1600 if (tlb_type == spitfire) {
1601 for (i = 0; i < 64; i++) {
1602 /* Spitfire Errata #32 workaround */
1603 /* NOTE: Always runs on spitfire, so no
1604 * cheetah+ page size encodings.
1605 */
1606 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1607 "flush %%g6"
1608 : /* No outputs */
1609 : "r" (0),
1610 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1611
1612 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
1613 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1614 "membar #Sync"
1615 : /* no outputs */
1616 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
1617 spitfire_put_dtlb_data(i, 0x0UL);
1618 }
1619
1620 /* Spitfire Errata #32 workaround */
1621 /* NOTE: Always runs on spitfire, so no
1622 * cheetah+ page size encodings.
1623 */
1624 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1625 "flush %%g6"
1626 : /* No outputs */
1627 : "r" (0),
1628 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1629
1630 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
1631 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1632 "membar #Sync"
1633 : /* no outputs */
1634 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1635 spitfire_put_itlb_data(i, 0x0UL);
1636 }
1637 }
1638 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1639 cheetah_flush_dtlb_all();
1640 cheetah_flush_itlb_all();
1641 }
1642 __asm__ __volatile__("wrpr %0, 0, %%pstate"
1643 : : "r" (pstate));
1644}