Peter Rosin | fbace43 | 2014-11-08 14:40:17 +0100 | [diff] [blame] | 1 | /* |
| 2 | * tfa9879.h -- driver for NXP Semiconductors TFA9879 |
| 3 | * |
| 4 | * Copyright (C) 2014 Axentia Technologies AB |
| 5 | * Author: Peter Rosin <peda@axentia.se> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms of the GNU General Public License as published by the |
| 9 | * Free Software Foundation; either version 2 of the License, or (at your |
| 10 | * option) any later version. |
| 11 | * |
| 12 | */ |
| 13 | |
| 14 | #ifndef _TFA9879_H |
| 15 | #define _TFA9879_H |
| 16 | |
| 17 | #define TFA9879_DEVICE_CONTROL 0x00 |
| 18 | #define TFA9879_SERIAL_INTERFACE_1 0x01 |
| 19 | #define TFA9879_PCM_IOM2_FORMAT_1 0x02 |
| 20 | #define TFA9879_SERIAL_INTERFACE_2 0x03 |
| 21 | #define TFA9879_PCM_IOM2_FORMAT_2 0x04 |
| 22 | #define TFA9879_EQUALIZER_A1 0x05 |
| 23 | #define TFA9879_EQUALIZER_A2 0x06 |
| 24 | #define TFA9879_EQUALIZER_B1 0x07 |
| 25 | #define TFA9879_EQUALIZER_B2 0x08 |
| 26 | #define TFA9879_EQUALIZER_C1 0x09 |
| 27 | #define TFA9879_EQUALIZER_C2 0x0a |
| 28 | #define TFA9879_EQUALIZER_D1 0x0b |
| 29 | #define TFA9879_EQUALIZER_D2 0x0c |
| 30 | #define TFA9879_EQUALIZER_E1 0x0d |
| 31 | #define TFA9879_EQUALIZER_E2 0x0e |
| 32 | #define TFA9879_BYPASS_CONTROL 0x0f |
| 33 | #define TFA9879_DYNAMIC_RANGE_COMPR 0x10 |
| 34 | #define TFA9879_BASS_TREBLE 0x11 |
| 35 | #define TFA9879_HIGH_PASS_FILTER 0x12 |
| 36 | #define TFA9879_VOLUME_CONTROL 0x13 |
| 37 | #define TFA9879_MISC_CONTROL 0x14 |
| 38 | #define TFA9879_MISC_STATUS 0x15 |
| 39 | |
| 40 | /* TFA9879_DEVICE_CONTROL */ |
| 41 | #define TFA9879_INPUT_SEL_MASK 0x0010 |
| 42 | #define TFA9879_INPUT_SEL_SHIFT 4 |
| 43 | #define TFA9879_OPMODE_MASK 0x0008 |
| 44 | #define TFA9879_OPMODE_SHIFT 3 |
| 45 | #define TFA9879_RESET_MASK 0x0002 |
| 46 | #define TFA9879_RESET_SHIFT 1 |
| 47 | #define TFA9879_POWERUP_MASK 0x0001 |
| 48 | #define TFA9879_POWERUP_SHIFT 0 |
| 49 | |
| 50 | /* TFA9879_SERIAL_INTERFACE */ |
| 51 | #define TFA9879_MONO_SEL_MASK 0x0c00 |
| 52 | #define TFA9879_MONO_SEL_SHIFT 10 |
| 53 | #define TFA9879_MONO_SEL_LEFT 0 |
| 54 | #define TFA9879_MONO_SEL_RIGHT 1 |
| 55 | #define TFA9879_MONO_SEL_BOTH 2 |
| 56 | #define TFA9879_I2S_FS_MASK 0x03c0 |
| 57 | #define TFA9879_I2S_FS_SHIFT 6 |
| 58 | #define TFA9879_I2S_FS_8000 0 |
| 59 | #define TFA9879_I2S_FS_11025 1 |
| 60 | #define TFA9879_I2S_FS_12000 2 |
| 61 | #define TFA9879_I2S_FS_16000 3 |
| 62 | #define TFA9879_I2S_FS_22050 4 |
| 63 | #define TFA9879_I2S_FS_24000 5 |
| 64 | #define TFA9879_I2S_FS_32000 6 |
| 65 | #define TFA9879_I2S_FS_44100 7 |
| 66 | #define TFA9879_I2S_FS_48000 8 |
| 67 | #define TFA9879_I2S_FS_64000 9 |
| 68 | #define TFA9879_I2S_FS_88200 10 |
| 69 | #define TFA9879_I2S_FS_96000 11 |
| 70 | #define TFA9879_I2S_SET_MASK 0x0038 |
| 71 | #define TFA9879_I2S_SET_SHIFT 3 |
| 72 | #define TFA9879_I2S_SET_MSB_J_24 2 |
| 73 | #define TFA9879_I2S_SET_I2S_24 3 |
| 74 | #define TFA9879_I2S_SET_LSB_J_16 4 |
| 75 | #define TFA9879_I2S_SET_LSB_J_18 5 |
| 76 | #define TFA9879_I2S_SET_LSB_J_20 6 |
| 77 | #define TFA9879_I2S_SET_LSB_J_24 7 |
| 78 | #define TFA9879_SCK_POL_MASK 0x0004 |
| 79 | #define TFA9879_SCK_POL_SHIFT 2 |
| 80 | #define TFA9879_SCK_POL_NORMAL 0 |
| 81 | #define TFA9879_SCK_POL_INVERSE 1 |
| 82 | #define TFA9879_I_MODE_MASK 0x0003 |
| 83 | #define TFA9879_I_MODE_SHIFT 0 |
| 84 | #define TFA9879_I_MODE_I2S 0 |
| 85 | #define TFA9879_I_MODE_PCM_IOM2_SHORT 1 |
| 86 | #define TFA9879_I_MODE_PCM_IOM2_LONG 2 |
| 87 | |
| 88 | /* TFA9879_PCM_IOM2_FORMAT */ |
| 89 | #define TFA9879_PCM_FS_MASK 0x0800 |
| 90 | #define TFA9879_PCM_FS_SHIFT 11 |
| 91 | #define TFA9879_A_LAW_MASK 0x0400 |
| 92 | #define TFA9879_A_LAW_SHIFT 10 |
| 93 | #define TFA9879_PCM_COMP_MASK 0x0200 |
| 94 | #define TFA9879_PCM_COMP_SHIFT 9 |
| 95 | #define TFA9879_PCM_DL_MASK 0x0100 |
| 96 | #define TFA9879_PCM_DL_SHIFT 8 |
| 97 | #define TFA9879_D1_SLOT_MASK 0x00f0 |
| 98 | #define TFA9879_D1_SLOT_SHIFT 4 |
| 99 | #define TFA9879_D2_SLOT_MASK 0x000f |
| 100 | #define TFA9879_D2_SLOT_SHIFT 0 |
| 101 | |
| 102 | /* TFA9879_EQUALIZER_X1 */ |
| 103 | #define TFA9879_T1_MASK 0x8000 |
| 104 | #define TFA9879_T1_SHIFT 15 |
| 105 | #define TFA9879_K1M_MASK 0x7ff0 |
| 106 | #define TFA9879_K1M_SHIFT 4 |
| 107 | #define TFA9879_K1E_MASK 0x000f |
| 108 | #define TFA9879_K1E_SHIFT 0 |
| 109 | |
| 110 | /* TFA9879_EQUALIZER_X2 */ |
| 111 | #define TFA9879_T2_MASK 0x8000 |
| 112 | #define TFA9879_T2_SHIFT 15 |
| 113 | #define TFA9879_K2M_MASK 0x7800 |
| 114 | #define TFA9879_K2M_SHIFT 11 |
| 115 | #define TFA9879_K2E_MASK 0x0700 |
| 116 | #define TFA9879_K2E_SHIFT 8 |
| 117 | #define TFA9879_K0_MASK 0x00fe |
| 118 | #define TFA9879_K0_SHIFT 1 |
| 119 | #define TFA9879_S_MASK 0x0001 |
| 120 | #define TFA9879_S_SHIFT 0 |
| 121 | |
| 122 | /* TFA9879_BYPASS_CONTROL */ |
| 123 | #define TFA9879_L_OCP_MASK 0x00c0 |
| 124 | #define TFA9879_L_OCP_SHIFT 6 |
| 125 | #define TFA9879_L_OTP_MASK 0x0030 |
| 126 | #define TFA9879_L_OTP_SHIFT 4 |
| 127 | #define TFA9879_CLIPCTRL_MASK 0x0008 |
| 128 | #define TFA9879_CLIPCTRL_SHIFT 3 |
| 129 | #define TFA9879_HPF_BP_MASK 0x0004 |
| 130 | #define TFA9879_HPF_BP_SHIFT 2 |
| 131 | #define TFA9879_DRC_BP_MASK 0x0002 |
| 132 | #define TFA9879_DRC_BP_SHIFT 1 |
| 133 | #define TFA9879_EQ_BP_MASK 0x0001 |
| 134 | #define TFA9879_EQ_BP_SHIFT 0 |
| 135 | |
| 136 | /* TFA9879_DYNAMIC_RANGE_COMPR */ |
| 137 | #define TFA9879_AT_LVL_MASK 0xf000 |
| 138 | #define TFA9879_AT_LVL_SHIFT 12 |
| 139 | #define TFA9879_AT_RATE_MASK 0x0f00 |
| 140 | #define TFA9879_AT_RATE_SHIFT 8 |
| 141 | #define TFA9879_RL_LVL_MASK 0x00f0 |
| 142 | #define TFA9879_RL_LVL_SHIFT 4 |
| 143 | #define TFA9879_RL_RATE_MASK 0x000f |
| 144 | #define TFA9879_RL_RATE_SHIFT 0 |
| 145 | |
| 146 | /* TFA9879_BASS_TREBLE */ |
| 147 | #define TFA9879_G_TRBLE_MASK 0x3e00 |
| 148 | #define TFA9879_G_TRBLE_SHIFT 9 |
| 149 | #define TFA9879_F_TRBLE_MASK 0x0180 |
| 150 | #define TFA9879_F_TRBLE_SHIFT 7 |
| 151 | #define TFA9879_G_BASS_MASK 0x007c |
| 152 | #define TFA9879_G_BASS_SHIFT 2 |
| 153 | #define TFA9879_F_BASS_MASK 0x0003 |
| 154 | #define TFA9879_F_BASS_SHIFT 0 |
| 155 | |
| 156 | /* TFA9879_HIGH_PASS_FILTER */ |
| 157 | #define TFA9879_HP_CTRL_MASK 0x00ff |
| 158 | #define TFA9879_HP_CTRL_SHIFT 0 |
| 159 | |
| 160 | /* TFA9879_VOLUME_CONTROL */ |
| 161 | #define TFA9879_ZR_CRSS_MASK 0x1000 |
| 162 | #define TFA9879_ZR_CRSS_SHIFT 12 |
| 163 | #define TFA9879_VOL_MASK 0x00ff |
| 164 | #define TFA9879_VOL_SHIFT 0 |
| 165 | |
| 166 | /* TFA9879_MISC_CONTROL */ |
| 167 | #define TFA9879_DE_PHAS_MASK 0x0c00 |
| 168 | #define TFA9879_DE_PHAS_SHIFT 10 |
| 169 | #define TFA9879_H_MUTE_MASK 0x0200 |
| 170 | #define TFA9879_H_MUTE_SHIFT 9 |
| 171 | #define TFA9879_S_MUTE_MASK 0x0100 |
| 172 | #define TFA9879_S_MUTE_SHIFT 8 |
| 173 | #define TFA9879_P_LIM_MASK 0x00ff |
| 174 | #define TFA9879_P_LIM_SHIFT 0 |
| 175 | |
| 176 | /* TFA9879_MISC_STATUS */ |
| 177 | #define TFA9879_PS_MASK 0x4000 |
| 178 | #define TFA9879_PS_SHIFT 14 |
| 179 | #define TFA9879_PORA_MASK 0x2000 |
| 180 | #define TFA9879_PORA_SHIFT 13 |
| 181 | #define TFA9879_AMP_MASK 0x0600 |
| 182 | #define TFA9879_AMP_SHIFT 9 |
| 183 | #define TFA9879_IBP_2_MASK 0x0100 |
| 184 | #define TFA9879_IBP_2_SHIFT 8 |
| 185 | #define TFA9879_OFP_2_MASK 0x0080 |
| 186 | #define TFA9879_OFP_2_SHIFT 7 |
| 187 | #define TFA9879_UFP_2_MASK 0x0040 |
| 188 | #define TFA9879_UFP_2_SHIFT 6 |
| 189 | #define TFA9879_IBP_1_MASK 0x0020 |
| 190 | #define TFA9879_IBP_1_SHIFT 5 |
| 191 | #define TFA9879_OFP_1_MASK 0x0010 |
| 192 | #define TFA9879_OFP_1_SHIFT 4 |
| 193 | #define TFA9879_UFP_1_MASK 0x0008 |
| 194 | #define TFA9879_UFP_1_SHIFT 3 |
| 195 | #define TFA9879_OCPOKA_MASK 0x0004 |
| 196 | #define TFA9879_OCPOKA_SHIFT 2 |
| 197 | #define TFA9879_OCPOKB_MASK 0x0002 |
| 198 | #define TFA9879_OCPOKB_SHIFT 1 |
| 199 | #define TFA9879_OTPOK_MASK 0x0001 |
| 200 | #define TFA9879_OTPOK_SHIFT 0 |
| 201 | |
| 202 | #endif |