blob: 06d1054ca94b9cc525ee4f9516c5363b26d39fa2 [file] [log] [blame]
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001/*-
2 * Copyright (c) 2002-2007 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 * 3. Neither the names of the above-listed copyright holders nor the names
16 * of any contributors may be used to endorse or promote products derived
17 * from this software without specific prior written permission.
18 *
19 * Alternatively, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") version 2 as published by the Free
21 * Software Foundation.
22 *
23 * NO WARRANTY
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34 * THE POSSIBILITY OF SUCH DAMAGES.
35 *
36 */
37
38/*
39 * Defintions for the Atheros Wireless LAN controller driver.
40 */
41#ifndef _DEV_ATH_ATHVAR_H
42#define _DEV_ATH_ATHVAR_H
43
44#include <linux/interrupt.h>
45#include <linux/list.h>
46#include <linux/wireless.h>
47#include <linux/if_ether.h>
Bob Copeland3a078872008-06-25 22:35:28 -040048#include <linux/leds.h>
Jiri Slabyfa1c1142007-08-12 17:33:16 +020049
50#include "ath5k.h"
51#include "debug.h"
52
53#define ATH_RXBUF 40 /* number of RX buffers */
54#define ATH_TXBUF 200 /* number of TX buffers */
55#define ATH_BCBUF 1 /* number of beacon buffers */
56
57struct ath5k_buf {
58 struct list_head list;
Jiri Slaby3a0f2c82008-07-15 17:44:18 +020059 unsigned int flags; /* rx descriptor flags */
Jiri Slabyfa1c1142007-08-12 17:33:16 +020060 struct ath5k_desc *desc; /* virtual addr of desc */
61 dma_addr_t daddr; /* physical addr of desc */
62 struct sk_buff *skb; /* skbuff for buf */
63 dma_addr_t skbaddr;/* physical addr of skb data */
Jiri Slabyfa1c1142007-08-12 17:33:16 +020064};
65
66/*
67 * Data transmit queue state. One of these exists for each
68 * hardware transmit queue. Packets sent to us from above
69 * are assigned to queues based on their priority. Not all
70 * devices support a complete set of hardware transmit queues.
71 * For those devices the array sc_ac2q will map multiple
72 * priorities to fewer hardware queues (typically all to one
73 * hardware queue).
74 */
75struct ath5k_txq {
76 unsigned int qnum; /* hardware q number */
77 u32 *link; /* link ptr in last TX desc */
78 struct list_head q; /* transmit queue */
79 spinlock_t lock; /* lock on q and link */
80 bool setup;
81};
82
Bob Copeland3a078872008-06-25 22:35:28 -040083#define ATH5K_LED_MAX_NAME_LEN 31
84
85/*
86 * State for LED triggers
87 */
88struct ath5k_led
89{
90 char name[ATH5K_LED_MAX_NAME_LEN + 1]; /* name of the LED in sysfs */
91 struct ath5k_softc *sc; /* driver state */
92 struct led_classdev led_dev; /* led classdev */
93};
94
95
Jiri Slabyfa1c1142007-08-12 17:33:16 +020096#if CHAN_DEBUG
97#define ATH_CHAN_MAX (26+26+26+200+200)
98#else
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -050099#define ATH_CHAN_MAX (14+14+14+252+20)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200100#endif
101
102/* Software Carrier, keeps track of the driver state
103 * associated with an instance of a device */
104struct ath5k_softc {
105 struct pci_dev *pdev; /* for dma mapping */
106 void __iomem *iobase; /* address of the device */
107 struct mutex lock; /* dev-level lock */
Johannes Berg57ffc582008-04-29 17:18:59 +0200108 /* FIXME: how many does it really need? */
109 struct ieee80211_tx_queue_stats tx_stats[16];
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200110 struct ieee80211_low_level_stats ll_stats;
111 struct ieee80211_hw *hw; /* IEEE 802.11 common */
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500112 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200113 struct ieee80211_channel channels[ATH_CHAN_MAX];
Bruno Randolf63266a62008-07-30 17:12:58 +0200114 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
115 u8 rate_idx[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
Johannes Berg05c914f2008-09-11 00:01:58 +0200116 enum nl80211_iftype opmode;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200117 struct ath5k_hw *ah; /* Atheros HW */
118
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500119 struct ieee80211_supported_band *curband;
120
Luis R. Rodriguezb4461972008-02-04 10:03:54 -0500121#ifdef CONFIG_ATH5K_DEBUG
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200122 struct ath5k_dbg_info debug; /* debug info */
Luis R. Rodriguezb4461972008-02-04 10:03:54 -0500123#endif /* CONFIG_ATH5K_DEBUG */
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200124
125 struct ath5k_buf *bufptr; /* allocated buffer ptr */
126 struct ath5k_desc *desc; /* TX/RX descriptors */
127 dma_addr_t desc_daddr; /* DMA (physical) address */
128 size_t desc_len; /* size of TX/RX descriptors */
129 u16 cachelsz; /* cache line size */
130
Bob Copeland8bdd5b92008-10-16 11:02:06 -0400131 DECLARE_BITMAP(status, 5);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200132#define ATH_STAT_INVALID 0 /* disable hardware accesses */
133#define ATH_STAT_MRRETRY 1 /* multi-rate retry support */
134#define ATH_STAT_PROMISC 2
Bob Copeland3a078872008-06-25 22:35:28 -0400135#define ATH_STAT_LEDSOFT 3 /* enable LED gpio status */
Bob Copeland8bdd5b92008-10-16 11:02:06 -0400136#define ATH_STAT_STARTED 4 /* opened & irqs enabled */
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200137
138 unsigned int filter_flags; /* HW flags, AR5K_RX_FILTER_* */
139 unsigned int curmode; /* current phy mode */
140 struct ieee80211_channel *curchan; /* current h/w channel */
141
Johannes Berg32bfd352007-12-19 01:31:26 +0100142 struct ieee80211_vif *vif;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200143
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200144 enum ath5k_int imask; /* interrupt mask copy */
145
146 DECLARE_BITMAP(keymap, AR5K_KEYCACHE_SIZE); /* key use bit map */
147
148 u8 bssidmask[ETH_ALEN];
149
150 unsigned int led_pin, /* GPIO pin for driving LED */
151 led_on, /* pin setting for LED on */
152 led_off; /* off time for current blink */
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200153
154 struct tasklet_struct restq; /* reset tasklet */
155
156 unsigned int rxbufsize; /* rx size based on mtu */
157 struct list_head rxbuf; /* receive buffer */
158 spinlock_t rxbuflock;
159 u32 *rxlink; /* link ptr in last RX desc */
160 struct tasklet_struct rxtq; /* rx intr tasklet */
Bob Copeland3a078872008-06-25 22:35:28 -0400161 struct ath5k_led rx_led; /* rx led */
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200162
163 struct list_head txbuf; /* transmit buffer */
164 spinlock_t txbuflock;
165 unsigned int txbuf_len; /* buf count in txbuf list */
166 struct ath5k_txq txqs[2]; /* beacon and tx */
167
168 struct ath5k_txq *txq; /* beacon and tx*/
169 struct tasklet_struct txtq; /* tx intr tasklet */
Bob Copeland3a078872008-06-25 22:35:28 -0400170 struct ath5k_led tx_led; /* tx led */
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200171
Jiri Slaby00482972008-08-18 21:45:27 +0200172 spinlock_t block; /* protects beacon */
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200173 struct ath5k_buf *bbuf; /* beacon buffer */
174 unsigned int bhalq, /* SW q for outgoing beacons */
175 bmisscount, /* missed beacon transmits */
Bruno Randolfe535c1a2008-01-18 21:51:40 +0900176 bintval, /* beacon interval in TU */
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200177 bsent;
Bruno Randolf036cd1e2008-01-19 18:18:21 +0900178 unsigned int nexttbtt; /* next beacon time in TU */
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200179
180 struct timer_list calib_tim; /* calibration timer */
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500181 int power_level; /* Requested tx power in dbm */
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200182};
183
184#define ath5k_hw_hasbssidmask(_ah) \
185 (ath5k_hw_get_capability(_ah, AR5K_CAP_BSSIDMASK, 0, NULL) == 0)
186#define ath5k_hw_hasveol(_ah) \
187 (ath5k_hw_get_capability(_ah, AR5K_CAP_VEOL, 0, NULL) == 0)
188
189#endif