blob: f0af911a096d9a781f318794fff9053416e0f0c5 [file] [log] [blame]
David Vrabelfc4effc2006-03-27 01:17:23 -08001/*
2 * Geode GX display controller.
3 *
4 * Copyright (C) 2005 Arcom Control Systems Ltd.
5 *
6 * Portions from AMD's original 2.4 driver:
7 * Copyright (C) 2004 Advanced Micro Devices, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by * the
11 * Free Software Foundation; either version 2 of the License, or * (at your
12 * option) any later version.
13 */
14#include <linux/spinlock.h>
15#include <linux/fb.h>
16#include <linux/delay.h>
17#include <asm/io.h>
18#include <asm/div64.h>
19#include <asm/delay.h>
Andres Salomonf3a57a62009-12-14 18:00:40 -080020#include <linux/cs5535.h>
David Vrabelfc4effc2006-03-27 01:17:23 -080021
Andres Salomonab06aaf2008-04-28 02:14:58 -070022#include "gxfb.h"
David Vrabelfc4effc2006-03-27 01:17:23 -080023
Jordan Crouse4c1979c2006-12-08 02:40:52 -080024unsigned int gx_frame_buffer_size(void)
David Vrabelfc4effc2006-03-27 01:17:23 -080025{
Jordan Crouse4c1979c2006-12-08 02:40:52 -080026 unsigned int val;
27
Andres Salomonf060f272009-12-14 18:00:40 -080028 if (!cs5535_has_vsa2()) {
Andres Salomonfd967952008-04-28 02:15:30 -070029 uint32_t hi, lo;
30
31 /* The number of pages is (PMAX - PMIN)+1 */
32 rdmsr(MSR_GLIU_P2D_RO0, lo, hi);
33
34 /* PMAX */
35 val = ((hi & 0xff) << 12) | ((lo & 0xfff00000) >> 20);
36 /* PMIN */
37 val -= (lo & 0x000fffff);
38 val += 1;
39
40 /* The page size is 4k */
41 return (val << 12);
42 }
43
44 /* FB size can be obtained from the VSA II */
Jordan Crouse4c1979c2006-12-08 02:40:52 -080045 /* Virtual register class = 0x02 */
46 /* VG_MEM_SIZE(512Kb units) = 0x00 */
47
Andres Salomon61a517a2008-04-28 02:15:30 -070048 outw(VSA_VR_UNLOCK, VSA_VRC_INDEX);
49 outw(VSA_VR_MEM_SIZE, VSA_VRC_INDEX);
Jordan Crouse4c1979c2006-12-08 02:40:52 -080050
Andres Salomon61a517a2008-04-28 02:15:30 -070051 val = (unsigned int)(inw(VSA_VRC_DATA)) & 0xFFl;
Jordan Crouse4c1979c2006-12-08 02:40:52 -080052 return (val << 19);
David Vrabelfc4effc2006-03-27 01:17:23 -080053}
54
55int gx_line_delta(int xres, int bpp)
56{
57 /* Must be a multiple of 8 bytes. */
58 return (xres * (bpp >> 3) + 7) & ~0x7;
59}
60
Andres Salomond1b4cc32008-04-28 02:15:01 -070061void gx_set_mode(struct fb_info *info)
David Vrabelfc4effc2006-03-27 01:17:23 -080062{
Andres Salomond1b4cc32008-04-28 02:15:01 -070063 struct gxfb_par *par = info->par;
David Vrabelfc4effc2006-03-27 01:17:23 -080064 u32 gcfg, dcfg;
65 int hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal;
66 int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;
67
68 /* Unlock the display controller registers. */
Andres Salomond2551142008-04-28 02:14:59 -070069 write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
David Vrabelfc4effc2006-03-27 01:17:23 -080070
Andres Salomonab06aaf2008-04-28 02:14:58 -070071 gcfg = read_dc(par, DC_GENERAL_CFG);
72 dcfg = read_dc(par, DC_DISPLAY_CFG);
David Vrabelfc4effc2006-03-27 01:17:23 -080073
74 /* Disable the timing generator. */
Andres Salomond2551142008-04-28 02:14:59 -070075 dcfg &= ~DC_DISPLAY_CFG_TGEN;
Andres Salomonab06aaf2008-04-28 02:14:58 -070076 write_dc(par, DC_DISPLAY_CFG, dcfg);
David Vrabelfc4effc2006-03-27 01:17:23 -080077
78 /* Wait for pending memory requests before disabling the FIFO load. */
79 udelay(100);
80
81 /* Disable FIFO load and compression. */
Andres Salomond2551142008-04-28 02:14:59 -070082 gcfg &= ~(DC_GENERAL_CFG_DFLE | DC_GENERAL_CFG_CMPE |
83 DC_GENERAL_CFG_DECE);
Andres Salomonab06aaf2008-04-28 02:14:58 -070084 write_dc(par, DC_GENERAL_CFG, gcfg);
David Vrabelfc4effc2006-03-27 01:17:23 -080085
86 /* Setup DCLK and its divisor. */
Andres Salomond1b4cc32008-04-28 02:15:01 -070087 gx_set_dclk_frequency(info);
David Vrabelfc4effc2006-03-27 01:17:23 -080088
89 /*
90 * Setup new mode.
91 */
92
93 /* Clear all unused feature bits. */
Andres Salomond2551142008-04-28 02:14:59 -070094 gcfg &= DC_GENERAL_CFG_YUVM | DC_GENERAL_CFG_VDSE;
David Vrabelfc4effc2006-03-27 01:17:23 -080095 dcfg = 0;
96
97 /* Set FIFO priority (default 6/5) and enable. */
98 /* FIXME: increase fifo priority for 1280x1024 and higher modes? */
Andres Salomond2551142008-04-28 02:14:59 -070099 gcfg |= (6 << DC_GENERAL_CFG_DFHPEL_SHIFT) |
100 (5 << DC_GENERAL_CFG_DFHPSL_SHIFT) | DC_GENERAL_CFG_DFLE;
David Vrabelfc4effc2006-03-27 01:17:23 -0800101
102 /* Framebuffer start offset. */
Andres Salomonab06aaf2008-04-28 02:14:58 -0700103 write_dc(par, DC_FB_ST_OFFSET, 0);
David Vrabelfc4effc2006-03-27 01:17:23 -0800104
105 /* Line delta and line buffer length. */
Andres Salomonab06aaf2008-04-28 02:14:58 -0700106 write_dc(par, DC_GFX_PITCH, info->fix.line_length >> 3);
107 write_dc(par, DC_LINE_SIZE,
108 ((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2);
David Vrabelfc4effc2006-03-27 01:17:23 -0800109
Jordan Crousef3788192006-12-08 02:40:53 -0800110
David Vrabelfc4effc2006-03-27 01:17:23 -0800111 /* Enable graphics and video data and unmask address lines. */
Andres Salomond2551142008-04-28 02:14:59 -0700112 dcfg |= DC_DISPLAY_CFG_GDEN | DC_DISPLAY_CFG_VDEN |
113 DC_DISPLAY_CFG_A20M | DC_DISPLAY_CFG_A18M;
David Vrabelfc4effc2006-03-27 01:17:23 -0800114
115 /* Set pixel format. */
116 switch (info->var.bits_per_pixel) {
117 case 8:
Andres Salomond2551142008-04-28 02:14:59 -0700118 dcfg |= DC_DISPLAY_CFG_DISP_MODE_8BPP;
David Vrabelfc4effc2006-03-27 01:17:23 -0800119 break;
120 case 16:
Andres Salomond2551142008-04-28 02:14:59 -0700121 dcfg |= DC_DISPLAY_CFG_DISP_MODE_16BPP;
David Vrabelfc4effc2006-03-27 01:17:23 -0800122 break;
123 case 32:
Andres Salomond2551142008-04-28 02:14:59 -0700124 dcfg |= DC_DISPLAY_CFG_DISP_MODE_24BPP;
125 dcfg |= DC_DISPLAY_CFG_PALB;
David Vrabelfc4effc2006-03-27 01:17:23 -0800126 break;
127 }
128
129 /* Enable timing generator. */
Andres Salomond2551142008-04-28 02:14:59 -0700130 dcfg |= DC_DISPLAY_CFG_TGEN;
David Vrabelfc4effc2006-03-27 01:17:23 -0800131
132 /* Horizontal and vertical timings. */
133 hactive = info->var.xres;
134 hblankstart = hactive;
135 hsyncstart = hblankstart + info->var.right_margin;
136 hsyncend = hsyncstart + info->var.hsync_len;
137 hblankend = hsyncend + info->var.left_margin;
138 htotal = hblankend;
139
140 vactive = info->var.yres;
141 vblankstart = vactive;
142 vsyncstart = vblankstart + info->var.lower_margin;
143 vsyncend = vsyncstart + info->var.vsync_len;
144 vblankend = vsyncend + info->var.upper_margin;
145 vtotal = vblankend;
146
Andres Salomonab06aaf2008-04-28 02:14:58 -0700147 write_dc(par, DC_H_ACTIVE_TIMING, (hactive - 1) |
148 ((htotal - 1) << 16));
149 write_dc(par, DC_H_BLANK_TIMING, (hblankstart - 1) |
150 ((hblankend - 1) << 16));
151 write_dc(par, DC_H_SYNC_TIMING, (hsyncstart - 1) |
152 ((hsyncend - 1) << 16));
David Vrabelfc4effc2006-03-27 01:17:23 -0800153
Andres Salomonab06aaf2008-04-28 02:14:58 -0700154 write_dc(par, DC_V_ACTIVE_TIMING, (vactive - 1) |
155 ((vtotal - 1) << 16));
156 write_dc(par, DC_V_BLANK_TIMING, (vblankstart - 1) |
157 ((vblankend - 1) << 16));
158 write_dc(par, DC_V_SYNC_TIMING, (vsyncstart - 1) |
159 ((vsyncend - 1) << 16));
David Vrabelfc4effc2006-03-27 01:17:23 -0800160
161 /* Write final register values. */
Andres Salomonab06aaf2008-04-28 02:14:58 -0700162 write_dc(par, DC_DISPLAY_CFG, dcfg);
163 write_dc(par, DC_GENERAL_CFG, gcfg);
David Vrabelfc4effc2006-03-27 01:17:23 -0800164
Andres Salomond1b4cc32008-04-28 02:15:01 -0700165 gx_configure_display(info);
David Vrabelfc4effc2006-03-27 01:17:23 -0800166
167 /* Relock display controller registers */
Andres Salomond2551142008-04-28 02:14:59 -0700168 write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
David Vrabelfc4effc2006-03-27 01:17:23 -0800169}
170
Andres Salomond1b4cc32008-04-28 02:15:01 -0700171void gx_set_hw_palette_reg(struct fb_info *info, unsigned regno,
172 unsigned red, unsigned green, unsigned blue)
David Vrabelfc4effc2006-03-27 01:17:23 -0800173{
Andres Salomond1b4cc32008-04-28 02:15:01 -0700174 struct gxfb_par *par = info->par;
David Vrabelfc4effc2006-03-27 01:17:23 -0800175 int val;
176
177 /* Hardware palette is in RGB 8-8-8 format. */
178 val = (red << 8) & 0xff0000;
179 val |= (green) & 0x00ff00;
180 val |= (blue >> 8) & 0x0000ff;
181
Andres Salomonab06aaf2008-04-28 02:14:58 -0700182 write_dc(par, DC_PAL_ADDRESS, regno);
183 write_dc(par, DC_PAL_DATA, val);
David Vrabelfc4effc2006-03-27 01:17:23 -0800184}