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Marc St-Jean35832e22007-06-14 15:54:47 -06001/*
2 * The generic setup file for PMC-Sierra MSP processors
3 *
4 * Copyright 2005-2007 PMC-Sierra, Inc,
5 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
6 *
Ralf Baechle70342282013-01-22 12:59:30 +01007 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
Marc St-Jean35832e22007-06-14 15:54:47 -06009 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#include <asm/bootinfo.h>
14#include <asm/cacheflush.h>
Ralf Baechlebdc92d742013-05-21 16:59:19 +020015#include <asm/idle.h>
Marc St-Jean35832e22007-06-14 15:54:47 -060016#include <asm/r4kcache.h>
17#include <asm/reboot.h>
Ralf Baechle2fd43102011-06-22 11:14:58 +010018#include <asm/smp-ops.h>
Marc St-Jean35832e22007-06-14 15:54:47 -060019#include <asm/time.h>
20
21#include <msp_prom.h>
22#include <msp_regs.h>
23
24#if defined(CONFIG_PMC_MSP7120_GW)
25#include <msp_regops.h>
Marc St-Jean35832e22007-06-14 15:54:47 -060026#define MSP_BOARD_RESET_GPIO 9
27#endif
28
Marc St-Jean35832e22007-06-14 15:54:47 -060029extern void msp_serial_setup(void);
30extern void pmctwiled_setup(void);
31
32#if defined(CONFIG_PMC_MSP7120_EVAL) || \
33 defined(CONFIG_PMC_MSP7120_GW) || \
34 defined(CONFIG_PMC_MSP7120_FPGA)
35/*
36 * Performs the reset for MSP7120-based boards
37 */
38void msp7120_reset(void)
39{
40 void *start, *end, *iptr;
41 register int i;
42
43 /* Diasble all interrupts */
44 local_irq_disable();
45#ifdef CONFIG_SYS_SUPPORTS_MULTITHREADING
46 dvpe();
47#endif
48
49 /* Cache the reset code of this function */
50 __asm__ __volatile__ (
51 " .set push \n"
52 " .set mips3 \n"
53 " la %0,startpoint \n"
54 " la %1,endpoint \n"
55 " .set pop \n"
56 : "=r" (start), "=r" (end)
57 :
58 );
59
60 for (iptr = (void *)((unsigned int)start & ~(L1_CACHE_BYTES - 1));
61 iptr < end; iptr += L1_CACHE_BYTES)
62 cache_op(Fill, iptr);
63
64 __asm__ __volatile__ (
65 "startpoint: \n"
66 );
67
68 /* Put the DDRC into self-refresh mode */
69 DDRC_INDIRECT_WRITE(DDRC_CTL(10), 0xb, 1 << 16);
70
71 /*
72 * IMPORTANT!
73 * DO NOT do anything from here on out that might even
74 * think about fetching from RAM - i.e., don't call any
75 * non-inlined functions, and be VERY sure that any inline
76 * functions you do call do NOT access any sort of RAM
77 * anywhere!
78 */
79
80 /* Wait a bit for the DDRC to settle */
81 for (i = 0; i < 100000000; i++);
82
83#if defined(CONFIG_PMC_MSP7120_GW)
84 /*
85 * Set GPIO 9 HI, (tied to board reset logic)
86 * GPIO 9 is the 4th GPIO of register 3
87 *
88 * NOTE: We cannot use the higher-level msp_gpio_mode()/out()
89 * as GPIO char driver may not be enabled and it would look up
90 * data inRAM!
91 */
Shane McDonald005076a2009-04-27 23:52:25 -060092 set_value_reg32(GPIO_CFG3_REG, 0xf000, 0x8000);
93 set_reg32(GPIO_DATA3_REG, 8);
Marc St-Jean35832e22007-06-14 15:54:47 -060094
95 /*
96 * In case GPIO9 doesn't reset the board (jumper configurable!)
97 * fallback to device reset below.
98 */
99#endif
100 /* Set bit 1 of the MSP7120 reset register */
101 *RST_SET_REG = 0x00000001;
102
103 __asm__ __volatile__ (
104 "endpoint: \n"
105 );
106}
107#endif
108
109void msp_restart(char *command)
110{
111 printk(KERN_WARNING "Now rebooting .......\n");
112
113#if defined(CONFIG_PMC_MSP7120_EVAL) || \
114 defined(CONFIG_PMC_MSP7120_GW) || \
115 defined(CONFIG_PMC_MSP7120_FPGA)
116 msp7120_reset();
117#else
118 /* No chip-specific reset code, just jump to the ROM reset vector */
119 set_c0_status(ST0_BEV | ST0_ERL);
120 change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
121 flush_cache_all();
122 write_c0_wired(0);
123
124 __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
125#endif
126}
127
128void msp_halt(void)
129{
130 printk(KERN_WARNING "\n** You can safely turn off the power\n");
131 while (1)
132 /* If possible call official function to get CPU WARs */
133 if (cpu_wait)
134 (*cpu_wait)();
135 else
136 __asm__(".set\tmips3\n\t" "wait\n\t" ".set\tmips0");
137}
138
139void msp_power_off(void)
140{
141 msp_halt();
142}
143
144void __init plat_mem_setup(void)
145{
146 _machine_restart = msp_restart;
147 _machine_halt = msp_halt;
148 pm_power_off = msp_power_off;
Marc St-Jean35832e22007-06-14 15:54:47 -0600149}
150
Anoop P A088f3872011-01-25 13:51:03 +0530151extern struct plat_smp_ops msp_smtc_smp_ops;
152
Marc St-Jean35832e22007-06-14 15:54:47 -0600153void __init prom_init(void)
154{
155 unsigned long family;
156 unsigned long revision;
157
158 prom_argc = fw_arg0;
159 prom_argv = (char **)fw_arg1;
160 prom_envp = (char **)fw_arg2;
161
162 /*
163 * Someday we can use this with PMON2000 to get a
164 * platform call prom routines for output etc. without
165 * having to use grody hacks. For now it's unused.
166 *
167 * struct callvectors *cv = (struct callvectors *) fw_arg3;
168 */
169 family = identify_family();
170 revision = identify_revision();
171
Ralf Baechle70342282013-01-22 12:59:30 +0100172 switch (family) {
Marc St-Jean35832e22007-06-14 15:54:47 -0600173 case FAMILY_FPGA:
174 if (FPGA_IS_MSP4200(revision)) {
175 /* Old-style revision ID */
Marc St-Jean35832e22007-06-14 15:54:47 -0600176 mips_machtype = MACH_MSP4200_FPGA;
177 } else {
Marc St-Jean35832e22007-06-14 15:54:47 -0600178 mips_machtype = MACH_MSP_OTHER;
179 }
180 break;
181
182 case FAMILY_MSP4200:
Marc St-Jean35832e22007-06-14 15:54:47 -0600183#if defined(CONFIG_PMC_MSP4200_EVAL)
184 mips_machtype = MACH_MSP4200_EVAL;
185#elif defined(CONFIG_PMC_MSP4200_GW)
186 mips_machtype = MACH_MSP4200_GW;
187#else
188 mips_machtype = MACH_MSP_OTHER;
189#endif
190 break;
191
192 case FAMILY_MSP4200_FPGA:
Marc St-Jean35832e22007-06-14 15:54:47 -0600193 mips_machtype = MACH_MSP4200_FPGA;
194 break;
195
196 case FAMILY_MSP7100:
Marc St-Jean35832e22007-06-14 15:54:47 -0600197#if defined(CONFIG_PMC_MSP7120_EVAL)
198 mips_machtype = MACH_MSP7120_EVAL;
199#elif defined(CONFIG_PMC_MSP7120_GW)
200 mips_machtype = MACH_MSP7120_GW;
201#else
202 mips_machtype = MACH_MSP_OTHER;
203#endif
204 break;
205
206 case FAMILY_MSP7100_FPGA:
Marc St-Jean35832e22007-06-14 15:54:47 -0600207 mips_machtype = MACH_MSP7120_FPGA;
208 break;
209
210 default:
211 /* we don't recognize the machine */
Marc St-Jean35832e22007-06-14 15:54:47 -0600212 mips_machtype = MACH_UNKNOWN;
Ralf Baechleab75dc02011-11-17 15:07:31 +0000213 panic("***Bogosity factor five***, exiting");
Ralf Baechle05dc8c02007-10-11 23:46:08 +0100214 break;
Marc St-Jean35832e22007-06-14 15:54:47 -0600215 }
216
217 prom_init_cmdline();
218
219 prom_meminit();
220
221 /*
222 * Sub-system setup follows.
Ralf Baechle70342282013-01-22 12:59:30 +0100223 * Setup functions can either be called here or using the
Marc St-Jean35832e22007-06-14 15:54:47 -0600224 * subsys_initcall mechanism (i.e. see msp_pci_setup). The
225 * order in which they are called can be changed by using the
226 * link order in arch/mips/pmc-sierra/msp71xx/Makefile.
227 *
228 * NOTE: Please keep sub-system specific initialization code
229 * in separate specific files.
230 */
231 msp_serial_setup();
232
Ralf Baechle852fe312011-05-28 15:27:59 +0100233 if (register_vsmp_smp_ops()) {
Anoop P A088f3872011-01-25 13:51:03 +0530234#ifdef CONFIG_MIPS_MT_SMTC
Ralf Baechle852fe312011-05-28 15:27:59 +0100235 register_smp_ops(&msp_smtc_smp_ops);
Anoop P A088f3872011-01-25 13:51:03 +0530236#endif
Ralf Baechle852fe312011-05-28 15:27:59 +0100237 }
Anoop P A088f3872011-01-25 13:51:03 +0530238
Marc St-Jean35832e22007-06-14 15:54:47 -0600239#ifdef CONFIG_PMCTWILED
240 /*
241 * Setup LED states before the subsys_initcall loads other
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300242 * dependent drivers/modules.
Marc St-Jean35832e22007-06-14 15:54:47 -0600243 */
244 pmctwiled_setup();
245#endif
246}