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gerrit-public.fairphone.software / kernel / msm-4.9 / 8c07a308ec5284fe41aefe48ac2ef4cfcd71ddbf / . / arch / blackfin / mach-bf533 / dma.c
blob: 1f5988d431396816e34bc8c9042453ee655a9a81 [file] [log] [blame]
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]1/*
Robin Getz96f10502009-09-24 14:11:24 +0000[diff] [blame]2 * simple DMA Implementation for Blackfin
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]3 *
Robin Getz96f10502009-09-24 14:11:24 +0000[diff] [blame]4 * Copyright 2007-2009 Analog Devices Inc.
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]5 *
Robin Getz96f10502009-09-24 14:11:24 +0000[diff] [blame]6 * Licensed under the GPL-2 or later.
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]7 */
Robin Getz96f10502009-09-24 14:11:24 +0000[diff] [blame]8
Bernd Schmidtac86a972008-04-24 05:23:31 +0800[diff] [blame]9#include <linux/module.h>
10
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]11#include <asm/blackfin.h>
12#include <asm/dma.h>
13
Mike Frysinger5e3bcf32010-10-25 18:11:09 +0000[diff] [blame]14struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]15 (struct dma_register *) DMA0_NEXT_DESC_PTR,
16 (struct dma_register *) DMA1_NEXT_DESC_PTR,
17 (struct dma_register *) DMA2_NEXT_DESC_PTR,
18 (struct dma_register *) DMA3_NEXT_DESC_PTR,
19 (struct dma_register *) DMA4_NEXT_DESC_PTR,
20 (struct dma_register *) DMA5_NEXT_DESC_PTR,
21 (struct dma_register *) DMA6_NEXT_DESC_PTR,
22 (struct dma_register *) DMA7_NEXT_DESC_PTR,
23 (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
24 (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
25 (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
26 (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
27};
Bernd Schmidt77955662008-04-24 05:31:18 +0800[diff] [blame]28EXPORT_SYMBOL(dma_io_base_addr);
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]29
Mike Frysingerf8ffe652007-06-21 11:34:16 +0800[diff] [blame]30int channel2irq(unsigned int channel)
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]31{
32 int ret_irq = -1;
33
34 switch (channel) {
35 case CH_PPI:
36 ret_irq = IRQ_PPI;
37 break;
38
39 case CH_SPORT0_RX:
40 ret_irq = IRQ_SPORT0_RX;
41 break;
42
43 case CH_SPORT0_TX:
44 ret_irq = IRQ_SPORT0_TX;
45 break;
46
47 case CH_SPORT1_RX:
48 ret_irq = IRQ_SPORT1_RX;
49 break;
50
51 case CH_SPORT1_TX:
52 ret_irq = IRQ_SPORT1_TX;
53 break;
54
55 case CH_SPI:
56 ret_irq = IRQ_SPI;
57 break;
58
Mike Frysinger8d71e072009-07-27 00:44:25 +0000[diff] [blame]59 case CH_UART0_RX:
60 ret_irq = IRQ_UART0_RX;
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]61 break;
62
Mike Frysinger8d71e072009-07-27 00:44:25 +0000[diff] [blame]63 case CH_UART0_TX:
64 ret_irq = IRQ_UART0_TX;
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]65 break;
66
67 case CH_MEM_STREAM0_SRC:
68 case CH_MEM_STREAM0_DEST:
69 ret_irq = IRQ_MEM_DMA0;
70 break;
71
72 case CH_MEM_STREAM1_SRC:
73 case CH_MEM_STREAM1_DEST:
74 ret_irq = IRQ_MEM_DMA1;
75 break;
76 }
77 return ret_irq;
78}