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gerrit-public.fairphone.software / kernel / msm-4.9 / 8cc1a5328b7406063812e3341e8f02718b54e3bc / . / drivers / gpu / drm / radeon / cik.c
blob: 28f68dc96fdb530740e006c3fe15d96185a677a6 [file] [log] [blame]
Alex Deucher8cc1a532013-04-09 12:41:24 -0400[diff] [blame^]1/*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <linux/platform_device.h>
26#include <linux/slab.h>
27#include <linux/module.h>
28#include "drmP.h"
29#include "radeon.h"
30#include "cikd.h"
31#include "atom.h"
32
33/*
34 * Core functions
35 */
36/**
37 * cik_tiling_mode_table_init - init the hw tiling table
38 *
39 * @rdev: radeon_device pointer
40 *
41 * Starting with SI, the tiling setup is done globally in a
42 * set of 32 tiling modes. Rather than selecting each set of
43 * parameters per surface as on older asics, we just select
44 * which index in the tiling table we want to use, and the
45 * surface uses those parameters (CIK).
46 */
47static void cik_tiling_mode_table_init(struct radeon_device *rdev)
48{
49 const u32 num_tile_mode_states = 32;
50 const u32 num_secondary_tile_mode_states = 16;
51 u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
52 u32 num_pipe_configs;
53 u32 num_rbs = rdev->config.cik.max_backends_per_se *
54 rdev->config.cik.max_shader_engines;
55
56 switch (rdev->config.cik.mem_row_size_in_kb) {
57 case 1:
58 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
59 break;
60 case 2:
61 default:
62 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
63 break;
64 case 4:
65 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
66 break;
67 }
68
69 num_pipe_configs = rdev->config.cik.max_tile_pipes;
70 if (num_pipe_configs > 8)
71 num_pipe_configs = 8; /* ??? */
72
73 if (num_pipe_configs == 8) {
74 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
75 switch (reg_offset) {
76 case 0:
77 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
78 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
79 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
80 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
81 break;
82 case 1:
83 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
84 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
85 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
86 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
87 break;
88 case 2:
89 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
90 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
91 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
92 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
93 break;
94 case 3:
95 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
96 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
97 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
98 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
99 break;
100 case 4:
101 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
102 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
103 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
104 TILE_SPLIT(split_equal_to_row_size));
105 break;
106 case 5:
107 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
108 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
109 break;
110 case 6:
111 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
112 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
113 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
114 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
115 break;
116 case 7:
117 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
118 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
119 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
120 TILE_SPLIT(split_equal_to_row_size));
121 break;
122 case 8:
123 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
124 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
125 break;
126 case 9:
127 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
128 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
129 break;
130 case 10:
131 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
132 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
133 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
134 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
135 break;
136 case 11:
137 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
138 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
139 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
140 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
141 break;
142 case 12:
143 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
144 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
145 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
146 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
147 break;
148 case 13:
149 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
150 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
151 break;
152 case 14:
153 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
154 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
155 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
156 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
157 break;
158 case 16:
159 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
160 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
161 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
162 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
163 break;
164 case 17:
165 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
166 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
167 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
168 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
169 break;
170 case 27:
171 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
172 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
173 break;
174 case 28:
175 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
176 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
177 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
178 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
179 break;
180 case 29:
181 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
182 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
183 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
184 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
185 break;
186 case 30:
187 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
188 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
189 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
190 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
191 break;
192 default:
193 gb_tile_moden = 0;
194 break;
195 }
196 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
197 }
198 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
199 switch (reg_offset) {
200 case 0:
201 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
202 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
203 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
204 NUM_BANKS(ADDR_SURF_16_BANK));
205 break;
206 case 1:
207 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
208 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
209 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
210 NUM_BANKS(ADDR_SURF_16_BANK));
211 break;
212 case 2:
213 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
214 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
215 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
216 NUM_BANKS(ADDR_SURF_16_BANK));
217 break;
218 case 3:
219 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
220 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
221 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
222 NUM_BANKS(ADDR_SURF_16_BANK));
223 break;
224 case 4:
225 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
226 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
227 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
228 NUM_BANKS(ADDR_SURF_8_BANK));
229 break;
230 case 5:
231 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
232 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
233 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
234 NUM_BANKS(ADDR_SURF_4_BANK));
235 break;
236 case 6:
237 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
238 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
239 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
240 NUM_BANKS(ADDR_SURF_2_BANK));
241 break;
242 case 8:
243 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
244 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
245 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
246 NUM_BANKS(ADDR_SURF_16_BANK));
247 break;
248 case 9:
249 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
250 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
251 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
252 NUM_BANKS(ADDR_SURF_16_BANK));
253 break;
254 case 10:
255 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
256 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
257 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
258 NUM_BANKS(ADDR_SURF_16_BANK));
259 break;
260 case 11:
261 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
262 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
263 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
264 NUM_BANKS(ADDR_SURF_16_BANK));
265 break;
266 case 12:
267 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
268 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
269 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
270 NUM_BANKS(ADDR_SURF_8_BANK));
271 break;
272 case 13:
273 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
274 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
275 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
276 NUM_BANKS(ADDR_SURF_4_BANK));
277 break;
278 case 14:
279 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
280 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
281 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
282 NUM_BANKS(ADDR_SURF_2_BANK));
283 break;
284 default:
285 gb_tile_moden = 0;
286 break;
287 }
288 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
289 }
290 } else if (num_pipe_configs == 4) {
291 if (num_rbs == 4) {
292 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
293 switch (reg_offset) {
294 case 0:
295 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
296 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
297 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
298 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
299 break;
300 case 1:
301 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
302 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
303 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
304 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
305 break;
306 case 2:
307 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
308 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
309 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
310 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
311 break;
312 case 3:
313 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
314 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
315 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
316 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
317 break;
318 case 4:
319 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
320 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
321 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
322 TILE_SPLIT(split_equal_to_row_size));
323 break;
324 case 5:
325 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
326 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
327 break;
328 case 6:
329 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
330 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
331 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
332 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
333 break;
334 case 7:
335 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
336 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
337 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
338 TILE_SPLIT(split_equal_to_row_size));
339 break;
340 case 8:
341 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
342 PIPE_CONFIG(ADDR_SURF_P4_16x16));
343 break;
344 case 9:
345 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
346 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
347 break;
348 case 10:
349 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
350 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
351 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
352 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
353 break;
354 case 11:
355 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
356 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
357 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
358 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
359 break;
360 case 12:
361 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
362 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
363 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
364 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
365 break;
366 case 13:
367 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
368 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
369 break;
370 case 14:
371 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
372 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
373 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
374 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
375 break;
376 case 16:
377 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
378 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
379 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
380 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
381 break;
382 case 17:
383 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
384 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
385 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
386 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
387 break;
388 case 27:
389 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
390 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
391 break;
392 case 28:
393 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
394 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
395 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
396 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
397 break;
398 case 29:
399 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
400 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
401 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
402 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
403 break;
404 case 30:
405 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
406 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
407 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
408 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
409 break;
410 default:
411 gb_tile_moden = 0;
412 break;
413 }
414 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
415 }
416 } else if (num_rbs < 4) {
417 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
418 switch (reg_offset) {
419 case 0:
420 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
421 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
422 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
423 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
424 break;
425 case 1:
426 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
427 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
428 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
429 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
430 break;
431 case 2:
432 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
433 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
434 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
435 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
436 break;
437 case 3:
438 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
439 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
440 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
441 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
442 break;
443 case 4:
444 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
445 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
446 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
447 TILE_SPLIT(split_equal_to_row_size));
448 break;
449 case 5:
450 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
451 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
452 break;
453 case 6:
454 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
455 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
456 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
457 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
458 break;
459 case 7:
460 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
461 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
462 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
463 TILE_SPLIT(split_equal_to_row_size));
464 break;
465 case 8:
466 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
467 PIPE_CONFIG(ADDR_SURF_P4_8x16));
468 break;
469 case 9:
470 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
471 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
472 break;
473 case 10:
474 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
475 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
476 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
477 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
478 break;
479 case 11:
480 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
481 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
482 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
483 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
484 break;
485 case 12:
486 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
487 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
488 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
489 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
490 break;
491 case 13:
492 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
493 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
494 break;
495 case 14:
496 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
497 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
498 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
499 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
500 break;
501 case 16:
502 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
503 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
504 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
505 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
506 break;
507 case 17:
508 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
509 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
510 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
511 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
512 break;
513 case 27:
514 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
515 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
516 break;
517 case 28:
518 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
519 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
520 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
521 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
522 break;
523 case 29:
524 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
525 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
526 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
527 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
528 break;
529 case 30:
530 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
531 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
532 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
533 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
534 break;
535 default:
536 gb_tile_moden = 0;
537 break;
538 }
539 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
540 }
541 }
542 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
543 switch (reg_offset) {
544 case 0:
545 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
546 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
547 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
548 NUM_BANKS(ADDR_SURF_16_BANK));
549 break;
550 case 1:
551 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
552 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
553 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
554 NUM_BANKS(ADDR_SURF_16_BANK));
555 break;
556 case 2:
557 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
558 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
559 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
560 NUM_BANKS(ADDR_SURF_16_BANK));
561 break;
562 case 3:
563 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
564 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
565 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
566 NUM_BANKS(ADDR_SURF_16_BANK));
567 break;
568 case 4:
569 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
570 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
571 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
572 NUM_BANKS(ADDR_SURF_16_BANK));
573 break;
574 case 5:
575 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
576 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
577 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
578 NUM_BANKS(ADDR_SURF_8_BANK));
579 break;
580 case 6:
581 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
582 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
583 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
584 NUM_BANKS(ADDR_SURF_4_BANK));
585 break;
586 case 8:
587 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
588 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
589 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
590 NUM_BANKS(ADDR_SURF_16_BANK));
591 break;
592 case 9:
593 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
594 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
595 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
596 NUM_BANKS(ADDR_SURF_16_BANK));
597 break;
598 case 10:
599 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
600 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
601 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
602 NUM_BANKS(ADDR_SURF_16_BANK));
603 break;
604 case 11:
605 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
606 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
607 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
608 NUM_BANKS(ADDR_SURF_16_BANK));
609 break;
610 case 12:
611 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
612 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
613 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
614 NUM_BANKS(ADDR_SURF_16_BANK));
615 break;
616 case 13:
617 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
618 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
619 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
620 NUM_BANKS(ADDR_SURF_8_BANK));
621 break;
622 case 14:
623 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
624 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
625 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
626 NUM_BANKS(ADDR_SURF_4_BANK));
627 break;
628 default:
629 gb_tile_moden = 0;
630 break;
631 }
632 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
633 }
634 } else if (num_pipe_configs == 2) {
635 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
636 switch (reg_offset) {
637 case 0:
638 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
639 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
640 PIPE_CONFIG(ADDR_SURF_P2) |
641 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
642 break;
643 case 1:
644 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
645 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
646 PIPE_CONFIG(ADDR_SURF_P2) |
647 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
648 break;
649 case 2:
650 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
651 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
652 PIPE_CONFIG(ADDR_SURF_P2) |
653 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
654 break;
655 case 3:
656 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
657 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
658 PIPE_CONFIG(ADDR_SURF_P2) |
659 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
660 break;
661 case 4:
662 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
663 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
664 PIPE_CONFIG(ADDR_SURF_P2) |
665 TILE_SPLIT(split_equal_to_row_size));
666 break;
667 case 5:
668 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
669 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
670 break;
671 case 6:
672 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
673 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
674 PIPE_CONFIG(ADDR_SURF_P2) |
675 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
676 break;
677 case 7:
678 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
679 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
680 PIPE_CONFIG(ADDR_SURF_P2) |
681 TILE_SPLIT(split_equal_to_row_size));
682 break;
683 case 8:
684 gb_tile_moden = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
685 break;
686 case 9:
687 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
688 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
689 break;
690 case 10:
691 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
692 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
693 PIPE_CONFIG(ADDR_SURF_P2) |
694 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
695 break;
696 case 11:
697 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
698 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
699 PIPE_CONFIG(ADDR_SURF_P2) |
700 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
701 break;
702 case 12:
703 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
704 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
705 PIPE_CONFIG(ADDR_SURF_P2) |
706 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
707 break;
708 case 13:
709 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
710 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
711 break;
712 case 14:
713 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
714 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
715 PIPE_CONFIG(ADDR_SURF_P2) |
716 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
717 break;
718 case 16:
719 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
720 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
721 PIPE_CONFIG(ADDR_SURF_P2) |
722 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
723 break;
724 case 17:
725 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
726 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
727 PIPE_CONFIG(ADDR_SURF_P2) |
728 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
729 break;
730 case 27:
731 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
732 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
733 break;
734 case 28:
735 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
736 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
737 PIPE_CONFIG(ADDR_SURF_P2) |
738 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
739 break;
740 case 29:
741 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
742 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
743 PIPE_CONFIG(ADDR_SURF_P2) |
744 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
745 break;
746 case 30:
747 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
748 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
749 PIPE_CONFIG(ADDR_SURF_P2) |
750 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
751 break;
752 default:
753 gb_tile_moden = 0;
754 break;
755 }
756 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
757 }
758 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
759 switch (reg_offset) {
760 case 0:
761 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
762 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
763 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
764 NUM_BANKS(ADDR_SURF_16_BANK));
765 break;
766 case 1:
767 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
768 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
769 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
770 NUM_BANKS(ADDR_SURF_16_BANK));
771 break;
772 case 2:
773 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
774 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
775 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
776 NUM_BANKS(ADDR_SURF_16_BANK));
777 break;
778 case 3:
779 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
780 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
781 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
782 NUM_BANKS(ADDR_SURF_16_BANK));
783 break;
784 case 4:
785 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
786 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
787 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
788 NUM_BANKS(ADDR_SURF_16_BANK));
789 break;
790 case 5:
791 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
792 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
793 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
794 NUM_BANKS(ADDR_SURF_16_BANK));
795 break;
796 case 6:
797 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
798 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
799 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
800 NUM_BANKS(ADDR_SURF_8_BANK));
801 break;
802 case 8:
803 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
804 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
805 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
806 NUM_BANKS(ADDR_SURF_16_BANK));
807 break;
808 case 9:
809 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
810 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
811 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
812 NUM_BANKS(ADDR_SURF_16_BANK));
813 break;
814 case 10:
815 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
816 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
817 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
818 NUM_BANKS(ADDR_SURF_16_BANK));
819 break;
820 case 11:
821 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
822 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
823 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
824 NUM_BANKS(ADDR_SURF_16_BANK));
825 break;
826 case 12:
827 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
828 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
829 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
830 NUM_BANKS(ADDR_SURF_16_BANK));
831 break;
832 case 13:
833 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
834 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
835 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
836 NUM_BANKS(ADDR_SURF_16_BANK));
837 break;
838 case 14:
839 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
840 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
841 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
842 NUM_BANKS(ADDR_SURF_8_BANK));
843 break;
844 default:
845 gb_tile_moden = 0;
846 break;
847 }
848 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
849 }
850 } else
851 DRM_ERROR("unknown num pipe config: 0x%x\n", num_pipe_configs);
852}
853
854/**
855 * cik_select_se_sh - select which SE, SH to address
856 *
857 * @rdev: radeon_device pointer
858 * @se_num: shader engine to address
859 * @sh_num: sh block to address
860 *
861 * Select which SE, SH combinations to address. Certain
862 * registers are instanced per SE or SH. 0xffffffff means
863 * broadcast to all SEs or SHs (CIK).
864 */
865static void cik_select_se_sh(struct radeon_device *rdev,
866 u32 se_num, u32 sh_num)
867{
868 u32 data = INSTANCE_BROADCAST_WRITES;
869
870 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
871 data = SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
872 else if (se_num == 0xffffffff)
873 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
874 else if (sh_num == 0xffffffff)
875 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
876 else
877 data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
878 WREG32(GRBM_GFX_INDEX, data);
879}
880
881/**
882 * cik_create_bitmask - create a bitmask
883 *
884 * @bit_width: length of the mask
885 *
886 * create a variable length bit mask (CIK).
887 * Returns the bitmask.
888 */
889static u32 cik_create_bitmask(u32 bit_width)
890{
891 u32 i, mask = 0;
892
893 for (i = 0; i < bit_width; i++) {
894 mask <<= 1;
895 mask |= 1;
896 }
897 return mask;
898}
899
900/**
901 * cik_select_se_sh - select which SE, SH to address
902 *
903 * @rdev: radeon_device pointer
904 * @max_rb_num: max RBs (render backends) for the asic
905 * @se_num: number of SEs (shader engines) for the asic
906 * @sh_per_se: number of SH blocks per SE for the asic
907 *
908 * Calculates the bitmask of disabled RBs (CIK).
909 * Returns the disabled RB bitmask.
910 */
911static u32 cik_get_rb_disabled(struct radeon_device *rdev,
912 u32 max_rb_num, u32 se_num,
913 u32 sh_per_se)
914{
915 u32 data, mask;
916
917 data = RREG32(CC_RB_BACKEND_DISABLE);
918 if (data & 1)
919 data &= BACKEND_DISABLE_MASK;
920 else
921 data = 0;
922 data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
923
924 data >>= BACKEND_DISABLE_SHIFT;
925
926 mask = cik_create_bitmask(max_rb_num / se_num / sh_per_se);
927
928 return data & mask;
929}
930
931/**
932 * cik_setup_rb - setup the RBs on the asic
933 *
934 * @rdev: radeon_device pointer
935 * @se_num: number of SEs (shader engines) for the asic
936 * @sh_per_se: number of SH blocks per SE for the asic
937 * @max_rb_num: max RBs (render backends) for the asic
938 *
939 * Configures per-SE/SH RB registers (CIK).
940 */
941static void cik_setup_rb(struct radeon_device *rdev,
942 u32 se_num, u32 sh_per_se,
943 u32 max_rb_num)
944{
945 int i, j;
946 u32 data, mask;
947 u32 disabled_rbs = 0;
948 u32 enabled_rbs = 0;
949
950 for (i = 0; i < se_num; i++) {
951 for (j = 0; j < sh_per_se; j++) {
952 cik_select_se_sh(rdev, i, j);
953 data = cik_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se);
954 disabled_rbs |= data << ((i * sh_per_se + j) * CIK_RB_BITMAP_WIDTH_PER_SH);
955 }
956 }
957 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
958
959 mask = 1;
960 for (i = 0; i < max_rb_num; i++) {
961 if (!(disabled_rbs & mask))
962 enabled_rbs |= mask;
963 mask <<= 1;
964 }
965
966 for (i = 0; i < se_num; i++) {
967 cik_select_se_sh(rdev, i, 0xffffffff);
968 data = 0;
969 for (j = 0; j < sh_per_se; j++) {
970 switch (enabled_rbs & 3) {
971 case 1:
972 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
973 break;
974 case 2:
975 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
976 break;
977 case 3:
978 default:
979 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
980 break;
981 }
982 enabled_rbs >>= 2;
983 }
984 WREG32(PA_SC_RASTER_CONFIG, data);
985 }
986 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
987}
988
989/**
990 * cik_gpu_init - setup the 3D engine
991 *
992 * @rdev: radeon_device pointer
993 *
994 * Configures the 3D engine and tiling configuration
995 * registers so that the 3D engine is usable.
996 */
997static void cik_gpu_init(struct radeon_device *rdev)
998{
999 u32 gb_addr_config = RREG32(GB_ADDR_CONFIG);
1000 u32 mc_shared_chmap, mc_arb_ramcfg;
1001 u32 hdp_host_path_cntl;
1002 u32 tmp;
1003 int i, j;
1004
1005 switch (rdev->family) {
1006 case CHIP_BONAIRE:
1007 rdev->config.cik.max_shader_engines = 2;
1008 rdev->config.cik.max_tile_pipes = 4;
1009 rdev->config.cik.max_cu_per_sh = 7;
1010 rdev->config.cik.max_sh_per_se = 1;
1011 rdev->config.cik.max_backends_per_se = 2;
1012 rdev->config.cik.max_texture_channel_caches = 4;
1013 rdev->config.cik.max_gprs = 256;
1014 rdev->config.cik.max_gs_threads = 32;
1015 rdev->config.cik.max_hw_contexts = 8;
1016
1017 rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
1018 rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
1019 rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
1020 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
1021 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
1022 break;
1023 case CHIP_KAVERI:
1024 /* TODO */
1025 break;
1026 case CHIP_KABINI:
1027 default:
1028 rdev->config.cik.max_shader_engines = 1;
1029 rdev->config.cik.max_tile_pipes = 2;
1030 rdev->config.cik.max_cu_per_sh = 2;
1031 rdev->config.cik.max_sh_per_se = 1;
1032 rdev->config.cik.max_backends_per_se = 1;
1033 rdev->config.cik.max_texture_channel_caches = 2;
1034 rdev->config.cik.max_gprs = 256;
1035 rdev->config.cik.max_gs_threads = 16;
1036 rdev->config.cik.max_hw_contexts = 8;
1037
1038 rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
1039 rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
1040 rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
1041 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
1042 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
1043 break;
1044 }
1045
1046 /* Initialize HDP */
1047 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1048 WREG32((0x2c14 + j), 0x00000000);
1049 WREG32((0x2c18 + j), 0x00000000);
1050 WREG32((0x2c1c + j), 0x00000000);
1051 WREG32((0x2c20 + j), 0x00000000);
1052 WREG32((0x2c24 + j), 0x00000000);
1053 }
1054
1055 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1056
1057 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
1058
1059 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1060 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1061
1062 rdev->config.cik.num_tile_pipes = rdev->config.cik.max_tile_pipes;
1063 rdev->config.cik.mem_max_burst_length_bytes = 256;
1064 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
1065 rdev->config.cik.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1066 if (rdev->config.cik.mem_row_size_in_kb > 4)
1067 rdev->config.cik.mem_row_size_in_kb = 4;
1068 /* XXX use MC settings? */
1069 rdev->config.cik.shader_engine_tile_size = 32;
1070 rdev->config.cik.num_gpus = 1;
1071 rdev->config.cik.multi_gpu_tile_size = 64;
1072
1073 /* fix up row size */
1074 gb_addr_config &= ~ROW_SIZE_MASK;
1075 switch (rdev->config.cik.mem_row_size_in_kb) {
1076 case 1:
1077 default:
1078 gb_addr_config |= ROW_SIZE(0);
1079 break;
1080 case 2:
1081 gb_addr_config |= ROW_SIZE(1);
1082 break;
1083 case 4:
1084 gb_addr_config |= ROW_SIZE(2);
1085 break;
1086 }
1087
1088 /* setup tiling info dword. gb_addr_config is not adequate since it does
1089 * not have bank info, so create a custom tiling dword.
1090 * bits 3:0 num_pipes
1091 * bits 7:4 num_banks
1092 * bits 11:8 group_size
1093 * bits 15:12 row_size
1094 */
1095 rdev->config.cik.tile_config = 0;
1096 switch (rdev->config.cik.num_tile_pipes) {
1097 case 1:
1098 rdev->config.cik.tile_config |= (0 << 0);
1099 break;
1100 case 2:
1101 rdev->config.cik.tile_config |= (1 << 0);
1102 break;
1103 case 4:
1104 rdev->config.cik.tile_config |= (2 << 0);
1105 break;
1106 case 8:
1107 default:
1108 /* XXX what about 12? */
1109 rdev->config.cik.tile_config |= (3 << 0);
1110 break;
1111 }
1112 if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
1113 rdev->config.cik.tile_config |= 1 << 4;
1114 else
1115 rdev->config.cik.tile_config |= 0 << 4;
1116 rdev->config.cik.tile_config |=
1117 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
1118 rdev->config.cik.tile_config |=
1119 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
1120
1121 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1122 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1123 WREG32(DMIF_ADDR_CALC, gb_addr_config);
1124
1125 cik_tiling_mode_table_init(rdev);
1126
1127 cik_setup_rb(rdev, rdev->config.cik.max_shader_engines,
1128 rdev->config.cik.max_sh_per_se,
1129 rdev->config.cik.max_backends_per_se);
1130
1131 /* set HW defaults for 3D engine */
1132 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
1133
1134 WREG32(SX_DEBUG_1, 0x20);
1135
1136 WREG32(TA_CNTL_AUX, 0x00010000);
1137
1138 tmp = RREG32(SPI_CONFIG_CNTL);
1139 tmp |= 0x03000000;
1140 WREG32(SPI_CONFIG_CNTL, tmp);
1141
1142 WREG32(SQ_CONFIG, 1);
1143
1144 WREG32(DB_DEBUG, 0);
1145
1146 tmp = RREG32(DB_DEBUG2) & ~0xf00fffff;
1147 tmp |= 0x00000400;
1148 WREG32(DB_DEBUG2, tmp);
1149
1150 tmp = RREG32(DB_DEBUG3) & ~0x0002021c;
1151 tmp |= 0x00020200;
1152 WREG32(DB_DEBUG3, tmp);
1153
1154 tmp = RREG32(CB_HW_CONTROL) & ~0x00010000;
1155 tmp |= 0x00018208;
1156 WREG32(CB_HW_CONTROL, tmp);
1157
1158 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1159
1160 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_frontend) |
1161 SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_backend) |
1162 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cik.sc_hiz_tile_fifo_size) |
1163 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cik.sc_earlyz_tile_fifo_size)));
1164
1165 WREG32(VGT_NUM_INSTANCES, 1);
1166
1167 WREG32(CP_PERFMON_CNTL, 0);
1168
1169 WREG32(SQ_CONFIG, 0);
1170
1171 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1172 FORCE_EOV_MAX_REZ_CNT(255)));
1173
1174 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
1175 AUTO_INVLD_EN(ES_AND_GS_AUTO));
1176
1177 WREG32(VGT_GS_VERTEX_REUSE, 16);
1178 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1179
1180 tmp = RREG32(HDP_MISC_CNTL);
1181 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
1182 WREG32(HDP_MISC_CNTL, tmp);
1183
1184 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1185 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1186
1187 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1188 WREG32(PA_SC_ENHANCE, ENABLE_PA_SC_OUT_OF_ORDER);
1189
1190 udelay(50);
1191}
1192