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Muralidharan Karicheridd2ceb12009-07-03 05:23:07 -03001/*
2 * Copyright (C) 2005-2009 Texas Instruments Inc
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18#ifndef _DM355_CCDC_REGS_H
19#define _DM355_CCDC_REGS_H
20
21/**************************************************************************\
22* Register OFFSET Definitions
23\**************************************************************************/
24#define SYNCEN 0x00
25#define MODESET 0x04
26#define HDWIDTH 0x08
27#define VDWIDTH 0x0c
28#define PPLN 0x10
29#define LPFR 0x14
30#define SPH 0x18
31#define NPH 0x1c
32#define SLV0 0x20
33#define SLV1 0x24
34#define NLV 0x28
35#define CULH 0x2c
36#define CULV 0x30
37#define HSIZE 0x34
38#define SDOFST 0x38
39#define STADRH 0x3c
40#define STADRL 0x40
41#define CLAMP 0x44
42#define DCSUB 0x48
43#define COLPTN 0x4c
44#define BLKCMP0 0x50
45#define BLKCMP1 0x54
46#define MEDFILT 0x58
47#define RYEGAIN 0x5c
48#define GRCYGAIN 0x60
49#define GBGGAIN 0x64
50#define BMGGAIN 0x68
51#define OFFSET 0x6c
52#define OUTCLIP 0x70
53#define VDINT0 0x74
54#define VDINT1 0x78
55#define RSV0 0x7c
56#define GAMMAWD 0x80
57#define REC656IF 0x84
58#define CCDCFG 0x88
59#define FMTCFG 0x8c
60#define FMTPLEN 0x90
61#define FMTSPH 0x94
62#define FMTLNH 0x98
63#define FMTSLV 0x9c
64#define FMTLNV 0xa0
65#define FMTRLEN 0xa4
66#define FMTHCNT 0xa8
67#define FMT_ADDR_PTR_B 0xac
68#define FMT_ADDR_PTR(i) (FMT_ADDR_PTR_B + (i * 4))
69#define FMTPGM_VF0 0xcc
70#define FMTPGM_VF1 0xd0
71#define FMTPGM_AP0 0xd4
72#define FMTPGM_AP1 0xd8
73#define FMTPGM_AP2 0xdc
74#define FMTPGM_AP3 0xe0
75#define FMTPGM_AP4 0xe4
76#define FMTPGM_AP5 0xe8
77#define FMTPGM_AP6 0xec
78#define FMTPGM_AP7 0xf0
79#define LSCCFG1 0xf4
80#define LSCCFG2 0xf8
81#define LSCH0 0xfc
82#define LSCV0 0x100
83#define LSCKH 0x104
84#define LSCKV 0x108
85#define LSCMEMCTL 0x10c
86#define LSCMEMD 0x110
87#define LSCMEMQ 0x114
88#define DFCCTL 0x118
89#define DFCVSAT 0x11c
90#define DFCMEMCTL 0x120
91#define DFCMEM0 0x124
92#define DFCMEM1 0x128
93#define DFCMEM2 0x12c
94#define DFCMEM3 0x130
95#define DFCMEM4 0x134
96#define CSCCTL 0x138
97#define CSCM0 0x13c
98#define CSCM1 0x140
99#define CSCM2 0x144
100#define CSCM3 0x148
101#define CSCM4 0x14c
102#define CSCM5 0x150
103#define CSCM6 0x154
104#define CSCM7 0x158
105#define DATAOFST 0x15c
106#define CCDC_REG_LAST DATAOFST
107/**************************************************************
108* Define for various register bit mask and shifts for CCDC
109*
110**************************************************************/
111#define CCDC_RAW_IP_MODE 0
112#define CCDC_VDHDOUT_INPUT 0
113#define CCDC_YCINSWP_RAW (0 << 4)
114#define CCDC_EXWEN_DISABLE 0
115#define CCDC_DATAPOL_NORMAL 0
116#define CCDC_CCDCFG_FIDMD_LATCH_VSYNC 0
117#define CCDC_CCDCFG_FIDMD_NO_LATCH_VSYNC (1 << 6)
118#define CCDC_CCDCFG_WENLOG_AND 0
119#define CCDC_CCDCFG_TRGSEL_WEN 0
120#define CCDC_CCDCFG_EXTRG_DISABLE 0
121#define CCDC_CFA_MOSAIC 0
122#define CCDC_Y8POS_SHIFT 11
123
124#define CCDC_VDC_DFCVSAT_MASK 0x3fff
125#define CCDC_DATAOFST_MASK 0x0ff
126#define CCDC_DATAOFST_H_SHIFT 0
127#define CCDC_DATAOFST_V_SHIFT 8
128#define CCDC_GAMMAWD_CFA_MASK 1
129#define CCDC_GAMMAWD_CFA_SHIFT 5
130#define CCDC_GAMMAWD_INPUT_SHIFT 2
131#define CCDC_FID_POL_MASK 1
132#define CCDC_FID_POL_SHIFT 4
133#define CCDC_HD_POL_MASK 1
134#define CCDC_HD_POL_SHIFT 3
135#define CCDC_VD_POL_MASK 1
136#define CCDC_VD_POL_SHIFT 2
137#define CCDC_VD_POL_NEGATIVE (1 << 2)
138#define CCDC_FRM_FMT_MASK 1
139#define CCDC_FRM_FMT_SHIFT 7
140#define CCDC_DATA_SZ_MASK 7
141#define CCDC_DATA_SZ_SHIFT 8
142#define CCDC_VDHDOUT_MASK 1
143#define CCDC_VDHDOUT_SHIFT 0
144#define CCDC_EXWEN_MASK 1
145#define CCDC_EXWEN_SHIFT 5
146#define CCDC_INPUT_MODE_MASK 3
147#define CCDC_INPUT_MODE_SHIFT 12
148#define CCDC_PIX_FMT_MASK 3
149#define CCDC_PIX_FMT_SHIFT 12
150#define CCDC_DATAPOL_MASK 1
151#define CCDC_DATAPOL_SHIFT 6
152#define CCDC_WEN_ENABLE (1 << 1)
153#define CCDC_VDHDEN_ENABLE (1 << 16)
154#define CCDC_LPF_ENABLE (1 << 14)
155#define CCDC_ALAW_ENABLE 1
156#define CCDC_ALAW_GAMA_WD_MASK 7
157#define CCDC_REC656IF_BT656_EN 3
158
159#define CCDC_FMTCFG_FMTMODE_MASK 3
160#define CCDC_FMTCFG_FMTMODE_SHIFT 1
161#define CCDC_FMTCFG_LNUM_MASK 3
162#define CCDC_FMTCFG_LNUM_SHIFT 4
163#define CCDC_FMTCFG_ADDRINC_MASK 7
164#define CCDC_FMTCFG_ADDRINC_SHIFT 8
165
166#define CCDC_CCDCFG_FIDMD_SHIFT 6
167#define CCDC_CCDCFG_WENLOG_SHIFT 8
168#define CCDC_CCDCFG_TRGSEL_SHIFT 9
169#define CCDC_CCDCFG_EXTRG_SHIFT 10
170#define CCDC_CCDCFG_MSBINVI_SHIFT 13
171
172#define CCDC_HSIZE_FLIP_SHIFT 12
173#define CCDC_HSIZE_FLIP_MASK 1
174#define CCDC_HSIZE_VAL_MASK 0xFFF
175#define CCDC_SDOFST_FIELD_INTERLEAVED 0x249
176#define CCDC_SDOFST_INTERLACE_INVERSE 0x4B6D
177#define CCDC_SDOFST_INTERLACE_NORMAL 0x0B6D
178#define CCDC_SDOFST_PROGRESSIVE_INVERSE 0x4000
179#define CCDC_SDOFST_PROGRESSIVE_NORMAL 0
180#define CCDC_START_PX_HOR_MASK 0x7FFF
181#define CCDC_NUM_PX_HOR_MASK 0x7FFF
182#define CCDC_START_VER_ONE_MASK 0x7FFF
183#define CCDC_START_VER_TWO_MASK 0x7FFF
184#define CCDC_NUM_LINES_VER 0x7FFF
185
186#define CCDC_BLK_CLAMP_ENABLE (1 << 15)
187#define CCDC_BLK_SGAIN_MASK 0x1F
188#define CCDC_BLK_ST_PXL_MASK 0x1FFF
189#define CCDC_BLK_SAMPLE_LN_MASK 3
190#define CCDC_BLK_SAMPLE_LN_SHIFT 13
191
192#define CCDC_NUM_LINE_CALC_MASK 3
193#define CCDC_NUM_LINE_CALC_SHIFT 14
194
195#define CCDC_BLK_DC_SUB_MASK 0x3FFF
196#define CCDC_BLK_COMP_MASK 0xFF
197#define CCDC_BLK_COMP_GB_COMP_SHIFT 8
198#define CCDC_BLK_COMP_GR_COMP_SHIFT 0
199#define CCDC_BLK_COMP_R_COMP_SHIFT 8
200#define CCDC_LATCH_ON_VSYNC_DISABLE (1 << 15)
201#define CCDC_LATCH_ON_VSYNC_ENABLE (0 << 15)
202#define CCDC_FPC_ENABLE (1 << 15)
203#define CCDC_FPC_FPC_NUM_MASK 0x7FFF
204#define CCDC_DATA_PACK_ENABLE (1 << 11)
205#define CCDC_FMT_HORZ_FMTLNH_MASK 0x1FFF
206#define CCDC_FMT_HORZ_FMTSPH_MASK 0x1FFF
207#define CCDC_FMT_HORZ_FMTSPH_SHIFT 16
208#define CCDC_FMT_VERT_FMTLNV_MASK 0x1FFF
209#define CCDC_FMT_VERT_FMTSLV_MASK 0x1FFF
210#define CCDC_FMT_VERT_FMTSLV_SHIFT 16
211#define CCDC_VP_OUT_VERT_NUM_MASK 0x3FFF
212#define CCDC_VP_OUT_VERT_NUM_SHIFT 17
213#define CCDC_VP_OUT_HORZ_NUM_MASK 0x1FFF
214#define CCDC_VP_OUT_HORZ_NUM_SHIFT 4
215#define CCDC_VP_OUT_HORZ_ST_MASK 0xF
216
217#define CCDC_CSC_COEF_INTEG_MASK 7
218#define CCDC_CSC_COEF_DECIMAL_MASK 0x1f
219#define CCDC_CSC_COEF_INTEG_SHIFT 5
220#define CCDC_CSCM_MSB_SHIFT 8
221#define CCDC_CSC_ENABLE 1
222#define CCDC_CSC_DEC_MAX 32
223
224#define CCDC_MFILT1_SHIFT 10
225#define CCDC_MFILT2_SHIFT 8
226#define CCDC_MED_FILT_THRESH 0x3FFF
227#define CCDC_LPF_MASK 1
228#define CCDC_LPF_SHIFT 14
229#define CCDC_OFFSET_MASK 0x3FF
230#define CCDC_DATASFT_MASK 7
231#define CCDC_DATASFT_SHIFT 8
232
233#define CCDC_DF_ENABLE 1
234
235#define CCDC_FMTPLEN_P0_MASK 0xF
236#define CCDC_FMTPLEN_P1_MASK 0xF
237#define CCDC_FMTPLEN_P2_MASK 7
238#define CCDC_FMTPLEN_P3_MASK 7
239#define CCDC_FMTPLEN_P0_SHIFT 0
240#define CCDC_FMTPLEN_P1_SHIFT 4
241#define CCDC_FMTPLEN_P2_SHIFT 8
242#define CCDC_FMTPLEN_P3_SHIFT 12
243
244#define CCDC_FMTSPH_MASK 0x1FFF
245#define CCDC_FMTLNH_MASK 0x1FFF
246#define CCDC_FMTSLV_MASK 0x1FFF
247#define CCDC_FMTLNV_MASK 0x7FFF
248#define CCDC_FMTRLEN_MASK 0x1FFF
249#define CCDC_FMTHCNT_MASK 0x1FFF
250
251#define CCDC_ADP_INIT_MASK 0x1FFF
252#define CCDC_ADP_LINE_SHIFT 13
253#define CCDC_ADP_LINE_MASK 3
254#define CCDC_FMTPGN_APTR_MASK 7
255
256#define CCDC_DFCCTL_GDFCEN_MASK 1
257#define CCDC_DFCCTL_VDFCEN_MASK 1
258#define CCDC_DFCCTL_VDFC_DISABLE (0 << 4)
259#define CCDC_DFCCTL_VDFCEN_SHIFT 4
260#define CCDC_DFCCTL_VDFCSL_MASK 3
261#define CCDC_DFCCTL_VDFCSL_SHIFT 5
262#define CCDC_DFCCTL_VDFCUDA_MASK 1
263#define CCDC_DFCCTL_VDFCUDA_SHIFT 7
264#define CCDC_DFCCTL_VDFLSFT_MASK 3
265#define CCDC_DFCCTL_VDFLSFT_SHIFT 8
266#define CCDC_DFCMEMCTL_DFCMARST_MASK 1
267#define CCDC_DFCMEMCTL_DFCMARST_SHIFT 2
268#define CCDC_DFCMEMCTL_DFCMWR_MASK 1
269#define CCDC_DFCMEMCTL_DFCMWR_SHIFT 0
270#define CCDC_DFCMEMCTL_INC_ADDR (0 << 2)
271
272#define CCDC_LSCCFG_GFTSF_MASK 7
273#define CCDC_LSCCFG_GFTSF_SHIFT 1
274#define CCDC_LSCCFG_GFTINV_MASK 0xf
275#define CCDC_LSCCFG_GFTINV_SHIFT 4
276#define CCDC_LSC_GFTABLE_SEL_MASK 3
277#define CCDC_LSC_GFTABLE_EPEL_SHIFT 8
278#define CCDC_LSC_GFTABLE_OPEL_SHIFT 10
279#define CCDC_LSC_GFTABLE_EPOL_SHIFT 12
280#define CCDC_LSC_GFTABLE_OPOL_SHIFT 14
281#define CCDC_LSC_GFMODE_MASK 3
282#define CCDC_LSC_GFMODE_SHIFT 4
283#define CCDC_LSC_DISABLE 0
284#define CCDC_LSC_ENABLE 1
285#define CCDC_LSC_TABLE1_SLC 0
286#define CCDC_LSC_TABLE2_SLC 1
287#define CCDC_LSC_TABLE3_SLC 2
288#define CCDC_LSC_MEMADDR_RESET (1 << 2)
289#define CCDC_LSC_MEMADDR_INCR (0 << 2)
290#define CCDC_LSC_FRAC_MASK_T1 0xFF
291#define CCDC_LSC_INT_MASK 3
292#define CCDC_LSC_FRAC_MASK 0x3FFF
293#define CCDC_LSC_CENTRE_MASK 0x3FFF
294#define CCDC_LSC_COEF_MASK 0xff
295#define CCDC_LSC_COEFL_SHIFT 0
296#define CCDC_LSC_COEFU_SHIFT 8
297#define CCDC_GAIN_MASK 0x7FF
298#define CCDC_SYNCEN_VDHDEN_MASK (1 << 0)
299#define CCDC_SYNCEN_WEN_MASK (1 << 1)
300#define CCDC_SYNCEN_WEN_SHIFT 1
301
302/* Power on Defaults in hardware */
303#define MODESET_DEFAULT 0x200
304#define CULH_DEFAULT 0xFFFF
305#define CULV_DEFAULT 0xFF
306#define GAIN_DEFAULT 256
307#define OUTCLIP_DEFAULT 0x3FFF
308#define LSCCFG2_DEFAULT 0xE
309
310#endif