Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/mach-at91/include/mach/at91_shdwc.h |
| 3 | * |
Andrew Victor | 3d73e89 | 2008-09-18 21:44:20 +0100 | [diff] [blame] | 4 | * Copyright (C) 2007 Andrew Victor |
| 5 | * Copyright (C) 2007 Atmel Corporation. |
| 6 | * |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 7 | * Shutdown Controller (SHDWC) - System peripherals regsters. |
| 8 | * Based on AT91SAM9261 datasheet revision D. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; either version 2 of the License, or |
| 13 | * (at your option) any later version. |
| 14 | */ |
| 15 | |
| 16 | #ifndef AT91_SHDWC_H |
| 17 | #define AT91_SHDWC_H |
| 18 | |
Jean-Christophe PLAGNIOL-VILLARD | f22deee | 2011-11-01 01:23:20 +0800 | [diff] [blame] | 19 | #ifndef __ASSEMBLY__ |
| 20 | extern void __iomem *at91_shdwc_base; |
| 21 | |
| 22 | #define at91_shdwc_read(field) \ |
| 23 | __raw_readl(at91_shdwc_base + field) |
| 24 | |
| 25 | #define at91_shdwc_write(field, value) \ |
Johan Hovold | 3aa630b | 2013-04-07 16:49:59 +0200 | [diff] [blame] | 26 | __raw_writel(value, at91_shdwc_base + field) |
Jean-Christophe PLAGNIOL-VILLARD | f22deee | 2011-11-01 01:23:20 +0800 | [diff] [blame] | 27 | #endif |
| 28 | |
| 29 | #define AT91_SHDW_CR 0x00 /* Shut Down Control Register */ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 30 | #define AT91_SHDW_SHDW (1 << 0) /* Shut Down command */ |
| 31 | #define AT91_SHDW_KEY (0xa5 << 24) /* KEY Password */ |
| 32 | |
Jean-Christophe PLAGNIOL-VILLARD | f22deee | 2011-11-01 01:23:20 +0800 | [diff] [blame] | 33 | #define AT91_SHDW_MR 0x04 /* Shut Down Mode Register */ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 34 | #define AT91_SHDW_WKMODE0 (3 << 0) /* Wake-up 0 Mode Selection */ |
| 35 | #define AT91_SHDW_WKMODE0_NONE 0 |
| 36 | #define AT91_SHDW_WKMODE0_HIGH 1 |
| 37 | #define AT91_SHDW_WKMODE0_LOW 2 |
| 38 | #define AT91_SHDW_WKMODE0_ANYLEVEL 3 |
Jean-Christophe PLAGNIOL-VILLARD | 82015c4 | 2012-03-02 21:01:00 +0800 | [diff] [blame] | 39 | #define AT91_SHDW_CPTWK0_MAX 0xf /* Maximum Counter On Wake Up 0 */ |
| 40 | #define AT91_SHDW_CPTWK0 (AT91_SHDW_CPTWK0_MAX << 4) /* Counter On Wake Up 0 */ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 41 | #define AT91_SHDW_CPTWK0_(x) ((x) << 4) |
| 42 | #define AT91_SHDW_RTTWKEN (1 << 16) /* Real Time Timer Wake-up Enable */ |
Jean-Christophe PLAGNIOL-VILLARD | 82015c4 | 2012-03-02 21:01:00 +0800 | [diff] [blame] | 43 | #define AT91_SHDW_RTCWKEN (1 << 17) /* Real Time Clock Wake-up Enable */ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 44 | |
Jean-Christophe PLAGNIOL-VILLARD | f22deee | 2011-11-01 01:23:20 +0800 | [diff] [blame] | 45 | #define AT91_SHDW_SR 0x08 /* Shut Down Status Register */ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 46 | #define AT91_SHDW_WAKEUP0 (1 << 0) /* Wake-up 0 Status */ |
| 47 | #define AT91_SHDW_RTTWK (1 << 16) /* Real-time Timer Wake-up */ |
| 48 | #define AT91_SHDW_RTCWK (1 << 17) /* Real-time Clock Wake-up [SAM9RL] */ |
| 49 | |
| 50 | #endif |