Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Pierre Ossman | 70f1048 | 2007-07-11 20:04:50 +0200 | [diff] [blame] | 2 | * linux/drivers/mmc/host/mmci.h - ARM PrimeCell MMCI PL180/1 driver |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | */ |
| 10 | #define MMCIPOWER 0x000 |
| 11 | #define MCI_PWR_OFF 0x00 |
| 12 | #define MCI_PWR_UP 0x02 |
| 13 | #define MCI_PWR_ON 0x03 |
| 14 | #define MCI_OD (1 << 6) |
| 15 | #define MCI_ROD (1 << 7) |
| 16 | |
| 17 | #define MMCICLOCK 0x004 |
| 18 | #define MCI_CLK_ENABLE (1 << 8) |
| 19 | #define MCI_CLK_PWRSAVE (1 << 9) |
| 20 | #define MCI_CLK_BYPASS (1 << 10) |
Linus Walleij | 771dc15 | 2010-04-08 07:38:52 +0100 | [diff] [blame] | 21 | #define MCI_4BIT_BUS (1 << 11) |
Linus Walleij | 49ac215 | 2011-03-04 14:54:16 +0100 | [diff] [blame] | 22 | /* |
| 23 | * 8bit wide buses, hardware flow contronl, negative edges and clock inversion |
| 24 | * supported in ST Micro U300 and Ux500 versions |
| 25 | */ |
Linus Walleij | 771dc15 | 2010-04-08 07:38:52 +0100 | [diff] [blame] | 26 | #define MCI_ST_8BIT_BUS (1 << 12) |
Linus Walleij | 49ac215 | 2011-03-04 14:54:16 +0100 | [diff] [blame] | 27 | #define MCI_ST_U300_HWFCEN (1 << 13) |
| 28 | #define MCI_ST_UX500_NEG_EDGE (1 << 13) |
| 29 | #define MCI_ST_UX500_HWFCEN (1 << 14) |
| 30 | #define MCI_ST_UX500_CLK_INV (1 << 15) |
Pawel Moll | 3a37298 | 2013-01-24 14:12:45 +0100 | [diff] [blame] | 31 | /* Modified PL180 on Versatile Express platform */ |
| 32 | #define MCI_ARM_HWFCEN (1 << 12) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 33 | |
| 34 | #define MMCIARGUMENT 0x008 |
| 35 | #define MMCICOMMAND 0x00c |
| 36 | #define MCI_CPSM_RESPONSE (1 << 6) |
| 37 | #define MCI_CPSM_LONGRSP (1 << 7) |
| 38 | #define MCI_CPSM_INTERRUPT (1 << 8) |
| 39 | #define MCI_CPSM_PENDING (1 << 9) |
| 40 | #define MCI_CPSM_ENABLE (1 << 10) |
Linus Walleij | cc30d60 | 2009-01-04 15:18:54 +0100 | [diff] [blame] | 41 | #define MCI_SDIO_SUSP (1 << 11) |
| 42 | #define MCI_ENCMD_COMPL (1 << 12) |
| 43 | #define MCI_NIEN (1 << 13) |
| 44 | #define MCI_CE_ATACMD (1 << 14) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 45 | |
| 46 | #define MMCIRESPCMD 0x010 |
| 47 | #define MMCIRESPONSE0 0x014 |
| 48 | #define MMCIRESPONSE1 0x018 |
| 49 | #define MMCIRESPONSE2 0x01c |
| 50 | #define MMCIRESPONSE3 0x020 |
| 51 | #define MMCIDATATIMER 0x024 |
| 52 | #define MMCIDATALENGTH 0x028 |
| 53 | #define MMCIDATACTRL 0x02c |
| 54 | #define MCI_DPSM_ENABLE (1 << 0) |
| 55 | #define MCI_DPSM_DIRECTION (1 << 1) |
| 56 | #define MCI_DPSM_MODE (1 << 2) |
| 57 | #define MCI_DPSM_DMAENABLE (1 << 3) |
Linus Walleij | cc30d60 | 2009-01-04 15:18:54 +0100 | [diff] [blame] | 58 | #define MCI_DPSM_BLOCKSIZE (1 << 4) |
Linus Walleij | 725343f | 2010-10-09 13:43:21 +0100 | [diff] [blame] | 59 | /* Control register extensions in the ST Micro U300 and Ux500 versions */ |
| 60 | #define MCI_ST_DPSM_RWSTART (1 << 8) |
| 61 | #define MCI_ST_DPSM_RWSTOP (1 << 9) |
| 62 | #define MCI_ST_DPSM_RWMOD (1 << 10) |
| 63 | #define MCI_ST_DPSM_SDIOEN (1 << 11) |
| 64 | /* Control register extensions in the ST Micro Ux500 versions */ |
| 65 | #define MCI_ST_DPSM_DMAREQCTL (1 << 12) |
| 66 | #define MCI_ST_DPSM_DBOOTMODEEN (1 << 13) |
| 67 | #define MCI_ST_DPSM_BUSYMODE (1 << 14) |
| 68 | #define MCI_ST_DPSM_DDRMODE (1 << 15) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 69 | |
| 70 | #define MMCIDATACNT 0x030 |
| 71 | #define MMCISTATUS 0x034 |
| 72 | #define MCI_CMDCRCFAIL (1 << 0) |
| 73 | #define MCI_DATACRCFAIL (1 << 1) |
| 74 | #define MCI_CMDTIMEOUT (1 << 2) |
| 75 | #define MCI_DATATIMEOUT (1 << 3) |
| 76 | #define MCI_TXUNDERRUN (1 << 4) |
| 77 | #define MCI_RXOVERRUN (1 << 5) |
| 78 | #define MCI_CMDRESPEND (1 << 6) |
| 79 | #define MCI_CMDSENT (1 << 7) |
| 80 | #define MCI_DATAEND (1 << 8) |
Linus Walleij | 757df74 | 2011-06-30 15:10:21 +0100 | [diff] [blame] | 81 | #define MCI_STARTBITERR (1 << 9) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 82 | #define MCI_DATABLOCKEND (1 << 10) |
| 83 | #define MCI_CMDACTIVE (1 << 11) |
| 84 | #define MCI_TXACTIVE (1 << 12) |
| 85 | #define MCI_RXACTIVE (1 << 13) |
| 86 | #define MCI_TXFIFOHALFEMPTY (1 << 14) |
| 87 | #define MCI_RXFIFOHALFFULL (1 << 15) |
| 88 | #define MCI_TXFIFOFULL (1 << 16) |
| 89 | #define MCI_RXFIFOFULL (1 << 17) |
| 90 | #define MCI_TXFIFOEMPTY (1 << 18) |
| 91 | #define MCI_RXFIFOEMPTY (1 << 19) |
| 92 | #define MCI_TXDATAAVLBL (1 << 20) |
| 93 | #define MCI_RXDATAAVLBL (1 << 21) |
Linus Walleij | 49ac215 | 2011-03-04 14:54:16 +0100 | [diff] [blame] | 94 | /* Extended status bits for the ST Micro variants */ |
| 95 | #define MCI_ST_SDIOIT (1 << 22) |
| 96 | #define MCI_ST_CEATAEND (1 << 23) |
Ulf Hansson | 0125962 | 2013-05-15 20:53:22 +0100 | [diff] [blame] | 97 | #define MCI_ST_CARDBUSY (1 << 24) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 98 | |
| 99 | #define MMCICLEAR 0x038 |
| 100 | #define MCI_CMDCRCFAILCLR (1 << 0) |
| 101 | #define MCI_DATACRCFAILCLR (1 << 1) |
| 102 | #define MCI_CMDTIMEOUTCLR (1 << 2) |
| 103 | #define MCI_DATATIMEOUTCLR (1 << 3) |
| 104 | #define MCI_TXUNDERRUNCLR (1 << 4) |
| 105 | #define MCI_RXOVERRUNCLR (1 << 5) |
| 106 | #define MCI_CMDRESPENDCLR (1 << 6) |
| 107 | #define MCI_CMDSENTCLR (1 << 7) |
| 108 | #define MCI_DATAENDCLR (1 << 8) |
Linus Walleij | 757df74 | 2011-06-30 15:10:21 +0100 | [diff] [blame] | 109 | #define MCI_STARTBITERRCLR (1 << 9) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 110 | #define MCI_DATABLOCKENDCLR (1 << 10) |
Linus Walleij | 49ac215 | 2011-03-04 14:54:16 +0100 | [diff] [blame] | 111 | /* Extended status bits for the ST Micro variants */ |
| 112 | #define MCI_ST_SDIOITC (1 << 22) |
| 113 | #define MCI_ST_CEATAENDC (1 << 23) |
Ulf Hansson | 0125962 | 2013-05-15 20:53:22 +0100 | [diff] [blame] | 114 | #define MCI_ST_BUSYENDC (1 << 24) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 115 | |
| 116 | #define MMCIMASK0 0x03c |
| 117 | #define MCI_CMDCRCFAILMASK (1 << 0) |
| 118 | #define MCI_DATACRCFAILMASK (1 << 1) |
| 119 | #define MCI_CMDTIMEOUTMASK (1 << 2) |
| 120 | #define MCI_DATATIMEOUTMASK (1 << 3) |
| 121 | #define MCI_TXUNDERRUNMASK (1 << 4) |
| 122 | #define MCI_RXOVERRUNMASK (1 << 5) |
| 123 | #define MCI_CMDRESPENDMASK (1 << 6) |
| 124 | #define MCI_CMDSENTMASK (1 << 7) |
| 125 | #define MCI_DATAENDMASK (1 << 8) |
Linus Walleij | 757df74 | 2011-06-30 15:10:21 +0100 | [diff] [blame] | 126 | #define MCI_STARTBITERRMASK (1 << 9) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 127 | #define MCI_DATABLOCKENDMASK (1 << 10) |
| 128 | #define MCI_CMDACTIVEMASK (1 << 11) |
| 129 | #define MCI_TXACTIVEMASK (1 << 12) |
| 130 | #define MCI_RXACTIVEMASK (1 << 13) |
| 131 | #define MCI_TXFIFOHALFEMPTYMASK (1 << 14) |
| 132 | #define MCI_RXFIFOHALFFULLMASK (1 << 15) |
| 133 | #define MCI_TXFIFOFULLMASK (1 << 16) |
| 134 | #define MCI_RXFIFOFULLMASK (1 << 17) |
| 135 | #define MCI_TXFIFOEMPTYMASK (1 << 18) |
| 136 | #define MCI_RXFIFOEMPTYMASK (1 << 19) |
| 137 | #define MCI_TXDATAAVLBLMASK (1 << 20) |
| 138 | #define MCI_RXDATAAVLBLMASK (1 << 21) |
Linus Walleij | 49ac215 | 2011-03-04 14:54:16 +0100 | [diff] [blame] | 139 | /* Extended status bits for the ST Micro variants */ |
| 140 | #define MCI_ST_SDIOITMASK (1 << 22) |
| 141 | #define MCI_ST_CEATAENDMASK (1 << 23) |
Ulf Hansson | 8d94b54 | 2014-01-13 16:49:31 +0100 | [diff] [blame^] | 142 | #define MCI_ST_BUSYEND (1 << 24) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 143 | |
| 144 | #define MMCIMASK1 0x040 |
| 145 | #define MMCIFIFOCNT 0x048 |
| 146 | #define MMCIFIFO 0x080 /* to 0x0bc */ |
| 147 | |
| 148 | #define MCI_IRQENABLE \ |
| 149 | (MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK| \ |
| 150 | MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \ |
Linus Walleij | 757df74 | 2011-06-30 15:10:21 +0100 | [diff] [blame] | 151 | MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_STARTBITERRMASK) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 152 | |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 153 | /* These interrupts are directed to IRQ1 when two IRQ lines are available */ |
| 154 | #define MCI_IRQ1MASK \ |
| 155 | (MCI_RXFIFOHALFFULLMASK | MCI_RXDATAAVLBLMASK | \ |
| 156 | MCI_TXFIFOHALFEMPTYMASK) |
| 157 | |
Ulf Hansson | 859dd55 | 2011-12-13 16:52:00 +0100 | [diff] [blame] | 158 | #define NR_SG 128 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 159 | |
| 160 | struct clk; |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 161 | struct variant_data; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 162 | struct dma_chan; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 163 | |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 164 | struct mmci_host_next { |
| 165 | struct dma_async_tx_descriptor *dma_desc; |
| 166 | struct dma_chan *dma_chan; |
| 167 | s32 cookie; |
| 168 | }; |
| 169 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 170 | struct mmci_host { |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 171 | phys_addr_t phybase; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 172 | void __iomem *base; |
| 173 | struct mmc_request *mrq; |
| 174 | struct mmc_command *cmd; |
| 175 | struct mmc_data *data; |
| 176 | struct mmc_host *mmc; |
| 177 | struct clk *clk; |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 178 | int gpio_cd; |
| 179 | int gpio_wp; |
Rabin Vincent | 148b8b3 | 2010-08-09 12:55:48 +0100 | [diff] [blame] | 180 | int gpio_cd_irq; |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 181 | bool singleirq; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 182 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 183 | spinlock_t lock; |
| 184 | |
| 185 | unsigned int mclk; |
| 186 | unsigned int cclk; |
Ulf Hansson | 7437cfa | 2012-01-18 09:17:27 +0100 | [diff] [blame] | 187 | u32 pwr_reg; |
| 188 | u32 clk_reg; |
Ulf Hansson | 9cc639a | 2013-05-15 20:48:23 +0100 | [diff] [blame] | 189 | u32 datactrl_reg; |
Ulf Hansson | 8d94b54 | 2014-01-13 16:49:31 +0100 | [diff] [blame^] | 190 | u32 busy_status; |
Ulf Hansson | 7c0136e | 2013-05-14 13:53:10 +0100 | [diff] [blame] | 191 | bool vqmmc_enabled; |
Linus Walleij | 6ef297f | 2009-09-22 14:29:36 +0100 | [diff] [blame] | 192 | struct mmci_platform_data *plat; |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 193 | struct variant_data *variant; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 194 | |
Linus Walleij | cc30d60 | 2009-01-04 15:18:54 +0100 | [diff] [blame] | 195 | u8 hw_designer; |
| 196 | u8 hw_revision:4; |
| 197 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 198 | struct timer_list timer; |
| 199 | unsigned int oldstat; |
| 200 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 201 | /* pio stuff */ |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame] | 202 | struct sg_mapping_iter sg_miter; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 203 | unsigned int size; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 204 | |
| 205 | #ifdef CONFIG_DMA_ENGINE |
| 206 | /* DMA stuff */ |
| 207 | struct dma_chan *dma_current; |
| 208 | struct dma_chan *dma_rx_channel; |
| 209 | struct dma_chan *dma_tx_channel; |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 210 | struct dma_async_tx_descriptor *dma_desc_current; |
| 211 | struct mmci_host_next next_data; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 212 | |
| 213 | #define dma_inprogress(host) ((host)->dma_current) |
| 214 | #else |
| 215 | #define dma_inprogress(host) (0) |
| 216 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 217 | }; |
| 218 | |