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gerrit-public.fairphone.software / kernel / msm-4.9 / 8dfaafd6398ec49797566ecb6992117434376588 / . / drivers / pinctrl / mediatek / pinctrl-mt8127.c
blob: b317b0b664eabd7a8be533f0d2e59a377aa4a75c [file] [log] [blame]
Yingjoe Chen6acdee82015-05-18 20:01:32 -0700[diff] [blame]1/*
2 * Copyright (c) 2015 MediaTek Inc.
3 * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
4 * Yingjoe Chen <yingjoe.chen@mediatek.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/module.h>
17#include <linux/platform_device.h>
18#include <linux/of.h>
19#include <linux/of_device.h>
20#include <linux/pinctrl/pinctrl.h>
21#include <linux/regmap.h>
22#include <dt-bindings/pinctrl/mt65xx.h>
23
24#include "pinctrl-mtk-common.h"
25#include "pinctrl-mtk-mt8127.h"
26
27static const struct mtk_drv_group_desc mt8127_drv_grp[] = {
28 /* 0E4E8SR 4/8/12/16 */
29 MTK_DRV_GRP(4, 16, 1, 2, 4),
30 /* 0E2E4SR 2/4/6/8 */
31 MTK_DRV_GRP(2, 8, 1, 2, 2),
32 /* E8E4E2 2/4/6/8/10/12/14/16 */
33 MTK_DRV_GRP(2, 16, 0, 2, 2)
34};
35
36static const struct mtk_pin_drv_grp mt8127_pin_drv[] = {
37 MTK_PIN_DRV_GRP(0, 0xb00, 0, 1),
38 MTK_PIN_DRV_GRP(1, 0xb00, 0, 1),
39 MTK_PIN_DRV_GRP(2, 0xb00, 0, 1),
40 MTK_PIN_DRV_GRP(3, 0xb00, 0, 1),
41 MTK_PIN_DRV_GRP(4, 0xb00, 0, 1),
42 MTK_PIN_DRV_GRP(5, 0xb00, 0, 1),
43 MTK_PIN_DRV_GRP(6, 0xb00, 0, 1),
44 MTK_PIN_DRV_GRP(7, 0xb00, 12, 1),
45 MTK_PIN_DRV_GRP(8, 0xb00, 12, 1),
46 MTK_PIN_DRV_GRP(9, 0xb00, 12, 1),
47 MTK_PIN_DRV_GRP(10, 0xb00, 8, 1),
48 MTK_PIN_DRV_GRP(11, 0xb00, 8, 1),
49 MTK_PIN_DRV_GRP(12, 0xb00, 8, 1),
50 MTK_PIN_DRV_GRP(13, 0xb00, 8, 1),
51 MTK_PIN_DRV_GRP(14, 0xb10, 4, 0),
52 MTK_PIN_DRV_GRP(15, 0xb10, 4, 0),
53 MTK_PIN_DRV_GRP(16, 0xb10, 4, 0),
54 MTK_PIN_DRV_GRP(17, 0xb10, 4, 0),
55 MTK_PIN_DRV_GRP(18, 0xb10, 8, 0),
56 MTK_PIN_DRV_GRP(19, 0xb10, 8, 0),
57 MTK_PIN_DRV_GRP(20, 0xb10, 8, 0),
58 MTK_PIN_DRV_GRP(21, 0xb10, 8, 0),
59 MTK_PIN_DRV_GRP(22, 0xb20, 0, 0),
60 MTK_PIN_DRV_GRP(23, 0xb20, 0, 0),
61 MTK_PIN_DRV_GRP(24, 0xb20, 0, 0),
62 MTK_PIN_DRV_GRP(25, 0xb20, 0, 0),
63 MTK_PIN_DRV_GRP(26, 0xb20, 0, 0),
64 MTK_PIN_DRV_GRP(27, 0xb20, 4, 0),
65 MTK_PIN_DRV_GRP(28, 0xb20, 4, 0),
66 MTK_PIN_DRV_GRP(29, 0xb20, 4, 0),
67 MTK_PIN_DRV_GRP(30, 0xb20, 4, 0),
68 MTK_PIN_DRV_GRP(31, 0xb20, 4, 0),
69 MTK_PIN_DRV_GRP(32, 0xb20, 4, 0),
70 MTK_PIN_DRV_GRP(33, 0xb30, 4, 1),
71 MTK_PIN_DRV_GRP(34, 0xb30, 8, 1),
72 MTK_PIN_DRV_GRP(35, 0xb30, 8, 1),
73 MTK_PIN_DRV_GRP(36, 0xb30, 8, 1),
74 MTK_PIN_DRV_GRP(37, 0xb30, 8, 1),
75 MTK_PIN_DRV_GRP(38, 0xb30, 8, 1),
76 MTK_PIN_DRV_GRP(39, 0xb30, 12, 1),
77 MTK_PIN_DRV_GRP(40, 0xb30, 12, 1),
78 MTK_PIN_DRV_GRP(41, 0xb30, 12, 1),
79 MTK_PIN_DRV_GRP(42, 0xb30, 12, 1),
80 MTK_PIN_DRV_GRP(43, 0xb40, 12, 0),
81 MTK_PIN_DRV_GRP(44, 0xb40, 12, 0),
82 MTK_PIN_DRV_GRP(45, 0xb40, 12, 0),
83 MTK_PIN_DRV_GRP(46, 0xb50, 0, 2),
84 MTK_PIN_DRV_GRP(47, 0xb50, 0, 2),
85 MTK_PIN_DRV_GRP(48, 0xb50, 0, 2),
86 MTK_PIN_DRV_GRP(49, 0xb50, 0, 2),
87 MTK_PIN_DRV_GRP(50, 0xb70, 0, 1),
88 MTK_PIN_DRV_GRP(51, 0xb70, 0, 1),
89 MTK_PIN_DRV_GRP(52, 0xb70, 0, 1),
90 MTK_PIN_DRV_GRP(53, 0xb50, 12, 1),
91 MTK_PIN_DRV_GRP(54, 0xb50, 12, 1),
92 MTK_PIN_DRV_GRP(55, 0xb50, 12, 1),
93 MTK_PIN_DRV_GRP(56, 0xb50, 12, 1),
94 MTK_PIN_DRV_GRP(59, 0xb40, 4, 1),
95 MTK_PIN_DRV_GRP(60, 0xb40, 0, 1),
96 MTK_PIN_DRV_GRP(61, 0xb40, 0, 1),
97 MTK_PIN_DRV_GRP(62, 0xb40, 0, 1),
98 MTK_PIN_DRV_GRP(63, 0xb40, 4, 1),
99 MTK_PIN_DRV_GRP(64, 0xb40, 4, 1),
100 MTK_PIN_DRV_GRP(65, 0xb40, 4, 1),
101 MTK_PIN_DRV_GRP(66, 0xb40, 8, 1),
102 MTK_PIN_DRV_GRP(67, 0xb40, 8, 1),
103 MTK_PIN_DRV_GRP(68, 0xb40, 8, 1),
104 MTK_PIN_DRV_GRP(69, 0xb40, 8, 1),
105 MTK_PIN_DRV_GRP(70, 0xb40, 8, 1),
106 MTK_PIN_DRV_GRP(71, 0xb40, 8, 1),
107 MTK_PIN_DRV_GRP(72, 0xb50, 4, 1),
108 MTK_PIN_DRV_GRP(73, 0xb50, 4, 1),
109 MTK_PIN_DRV_GRP(74, 0xb50, 4, 1),
110 MTK_PIN_DRV_GRP(79, 0xb50, 8, 1),
111 MTK_PIN_DRV_GRP(80, 0xb50, 8, 1),
112 MTK_PIN_DRV_GRP(81, 0xb50, 8, 1),
113 MTK_PIN_DRV_GRP(82, 0xb50, 8, 1),
114 MTK_PIN_DRV_GRP(83, 0xb50, 8, 1),
115 MTK_PIN_DRV_GRP(84, 0xb50, 8, 1),
116 MTK_PIN_DRV_GRP(85, 0xce0, 0, 2),
117 MTK_PIN_DRV_GRP(86, 0xcd0, 0, 2),
118 MTK_PIN_DRV_GRP(87, 0xcf0, 0, 2),
119 MTK_PIN_DRV_GRP(88, 0xcf0, 0, 2),
120 MTK_PIN_DRV_GRP(89, 0xcf0, 0, 2),
121 MTK_PIN_DRV_GRP(90, 0xcf0, 0, 2),
122 MTK_PIN_DRV_GRP(117, 0xb60, 12, 1),
123 MTK_PIN_DRV_GRP(118, 0xb60, 12, 1),
124 MTK_PIN_DRV_GRP(119, 0xb60, 12, 1),
125 MTK_PIN_DRV_GRP(120, 0xb60, 12, 1),
126 MTK_PIN_DRV_GRP(121, 0xc80, 0, 2),
127 MTK_PIN_DRV_GRP(122, 0xc70, 0, 2),
128 MTK_PIN_DRV_GRP(123, 0xc90, 0, 2),
129 MTK_PIN_DRV_GRP(124, 0xc90, 0, 2),
130 MTK_PIN_DRV_GRP(125, 0xc90, 0, 2),
131 MTK_PIN_DRV_GRP(126, 0xc90, 0, 2),
132 MTK_PIN_DRV_GRP(127, 0xc20, 0, 2),
133 MTK_PIN_DRV_GRP(128, 0xc20, 0, 2),
134 MTK_PIN_DRV_GRP(129, 0xc20, 0, 2),
135 MTK_PIN_DRV_GRP(130, 0xc20, 0, 2),
136 MTK_PIN_DRV_GRP(131, 0xc20, 0, 2),
137 MTK_PIN_DRV_GRP(132, 0xc10, 0, 2),
138 MTK_PIN_DRV_GRP(133, 0xc00, 0, 2),
139 MTK_PIN_DRV_GRP(134, 0xc20, 0, 2),
140 MTK_PIN_DRV_GRP(135, 0xc20, 0, 2),
141 MTK_PIN_DRV_GRP(136, 0xc20, 0, 2),
142 MTK_PIN_DRV_GRP(137, 0xc20, 0, 2),
143 MTK_PIN_DRV_GRP(142, 0xb50, 0, 2),
144};
145
146static const struct mtk_pin_spec_pupd_set_samereg mt8127_spec_pupd[] = {
147 MTK_PIN_PUPD_SPEC_SR(33, 0xd90, 2, 0, 1), /* KPROW0 */
148 MTK_PIN_PUPD_SPEC_SR(34, 0xd90, 6, 4, 5), /* KPROW1 */
149 MTK_PIN_PUPD_SPEC_SR(35, 0xd90, 10, 8, 9), /* KPROW2 */
150 MTK_PIN_PUPD_SPEC_SR(36, 0xda0, 2, 0, 1), /* KPCOL0 */
151 MTK_PIN_PUPD_SPEC_SR(37, 0xda0, 6, 4, 5), /* KPCOL1 */
152 MTK_PIN_PUPD_SPEC_SR(38, 0xda0, 10, 8, 9), /* KPCOL2 */
153 MTK_PIN_PUPD_SPEC_SR(46, 0xdb0, 2, 0, 1), /* EINT14 */
154 MTK_PIN_PUPD_SPEC_SR(47, 0xdb0, 6, 4, 5), /* EINT15 */
155 MTK_PIN_PUPD_SPEC_SR(48, 0xdb0, 10, 8, 9), /* EINT16 */
156 MTK_PIN_PUPD_SPEC_SR(49, 0xdb0, 14, 12, 13), /* EINT17 */
157 MTK_PIN_PUPD_SPEC_SR(85, 0xce0, 8, 10, 9), /* MSDC2_CMD */
158 MTK_PIN_PUPD_SPEC_SR(86, 0xcd0, 8, 10, 9), /* MSDC2_CLK */
159 MTK_PIN_PUPD_SPEC_SR(87, 0xd00, 0, 2, 1), /* MSDC2_DAT0 */
160 MTK_PIN_PUPD_SPEC_SR(88, 0xd00, 4, 6, 5), /* MSDC2_DAT1 */
161 MTK_PIN_PUPD_SPEC_SR(89, 0xd00, 8, 10, 9), /* MSDC2_DAT2 */
162 MTK_PIN_PUPD_SPEC_SR(90, 0xd00, 12, 14, 13), /* MSDC2_DAT3 */
163 MTK_PIN_PUPD_SPEC_SR(121, 0xc80, 8, 10, 9), /* MSDC1_CMD */
164 MTK_PIN_PUPD_SPEC_SR(122, 0xc70, 8, 10, 9), /* MSDC1_CLK */
165 MTK_PIN_PUPD_SPEC_SR(123, 0xca0, 0, 2, 1), /* MSDC1_DAT0 */
166 MTK_PIN_PUPD_SPEC_SR(124, 0xca0, 4, 6, 5), /* MSDC1_DAT1 */
167 MTK_PIN_PUPD_SPEC_SR(125, 0xca0, 8, 10, 9), /* MSDC1_DAT2 */
168 MTK_PIN_PUPD_SPEC_SR(126, 0xca0, 12, 14, 13), /* MSDC1_DAT3 */
169 MTK_PIN_PUPD_SPEC_SR(127, 0xc40, 12, 14, 13), /* MSDC0_DAT7 */
170 MTK_PIN_PUPD_SPEC_SR(128, 0xc40, 8, 10, 9), /* MSDC0_DAT6 */
171 MTK_PIN_PUPD_SPEC_SR(129, 0xc40, 4, 6, 5), /* MSDC0_DAT5 */
172 MTK_PIN_PUPD_SPEC_SR(130, 0xc40, 0, 2, 1), /* MSDC0_DAT4 */
173 MTK_PIN_PUPD_SPEC_SR(131, 0xc50, 0, 2, 1), /* MSDC0_RSTB */
174 MTK_PIN_PUPD_SPEC_SR(132, 0xc10, 8, 10, 9), /* MSDC0_CMD */
175 MTK_PIN_PUPD_SPEC_SR(133, 0xc00, 8, 10, 9), /* MSDC0_CLK */
176 MTK_PIN_PUPD_SPEC_SR(134, 0xc30, 12, 14, 13), /* MSDC0_DAT3 */
177 MTK_PIN_PUPD_SPEC_SR(135, 0xc30, 8, 10, 9), /* MSDC0_DAT2 */
178 MTK_PIN_PUPD_SPEC_SR(136, 0xc30, 4, 6, 5), /* MSDC0_DAT1 */
179 MTK_PIN_PUPD_SPEC_SR(137, 0xc30, 0, 2, 1), /* MSDC0_DAT0 */
180 MTK_PIN_PUPD_SPEC_SR(142, 0xdc0, 2, 0, 1), /* EINT21 */
181};
182
183static int mt8127_spec_pull_set(struct regmap *regmap, unsigned int pin,
184 unsigned char align, bool isup, unsigned int r1r0)
185{
186 return mtk_pctrl_spec_pull_set_samereg(regmap, mt8127_spec_pupd,
187 ARRAY_SIZE(mt8127_spec_pupd), pin, align, isup, r1r0);
188}
189
190static const struct mtk_pin_ies_smt_set mt8127_ies_set[] = {
191 MTK_PIN_IES_SMT_SPEC(0, 9, 0x900, 0),
192 MTK_PIN_IES_SMT_SPEC(10, 13, 0x900, 1),
193 MTK_PIN_IES_SMT_SPEC(14, 28, 0x900, 2),
194 MTK_PIN_IES_SMT_SPEC(29, 32, 0x900, 3),
195 MTK_PIN_IES_SMT_SPEC(33, 33, 0x910, 11),
196 MTK_PIN_IES_SMT_SPEC(34, 38, 0x900, 10),
197 MTK_PIN_IES_SMT_SPEC(39, 42, 0x900, 11),
198 MTK_PIN_IES_SMT_SPEC(43, 45, 0x900, 12),
199 MTK_PIN_IES_SMT_SPEC(46, 49, 0x900, 13),
200 MTK_PIN_IES_SMT_SPEC(50, 52, 0x910, 10),
201 MTK_PIN_IES_SMT_SPEC(53, 56, 0x900, 14),
202 MTK_PIN_IES_SMT_SPEC(57, 58, 0x910, 0),
203 MTK_PIN_IES_SMT_SPEC(59, 65, 0x910, 2),
204 MTK_PIN_IES_SMT_SPEC(66, 71, 0x910, 3),
205 MTK_PIN_IES_SMT_SPEC(72, 74, 0x910, 4),
206 MTK_PIN_IES_SMT_SPEC(75, 76, 0x900, 15),
207 MTK_PIN_IES_SMT_SPEC(77, 78, 0x910, 1),
208 MTK_PIN_IES_SMT_SPEC(79, 82, 0x910, 5),
209 MTK_PIN_IES_SMT_SPEC(83, 84, 0x910, 6),
210 MTK_PIN_IES_SMT_SPEC(117, 120, 0x910, 7),
211 MTK_PIN_IES_SMT_SPEC(121, 121, 0xc80, 4),
212 MTK_PIN_IES_SMT_SPEC(122, 122, 0xc70, 4),
213 MTK_PIN_IES_SMT_SPEC(123, 126, 0xc90, 4),
214 MTK_PIN_IES_SMT_SPEC(127, 131, 0xc20, 4),
215 MTK_PIN_IES_SMT_SPEC(132, 132, 0xc10, 4),
216 MTK_PIN_IES_SMT_SPEC(133, 133, 0xc00, 4),
217 MTK_PIN_IES_SMT_SPEC(134, 137, 0xc20, 4),
218 MTK_PIN_IES_SMT_SPEC(138, 141, 0x910, 9),
219 MTK_PIN_IES_SMT_SPEC(142, 142, 0x900, 13),
220};
221
222static const struct mtk_pin_ies_smt_set mt8127_smt_set[] = {
223 MTK_PIN_IES_SMT_SPEC(0, 9, 0x920, 0),
224 MTK_PIN_IES_SMT_SPEC(10, 13, 0x920, 1),
225 MTK_PIN_IES_SMT_SPEC(14, 28, 0x920, 2),
226 MTK_PIN_IES_SMT_SPEC(29, 32, 0x920, 3),
227 MTK_PIN_IES_SMT_SPEC(33, 33, 0x930, 11),
228 MTK_PIN_IES_SMT_SPEC(34, 38, 0x920, 10),
229 MTK_PIN_IES_SMT_SPEC(39, 42, 0x920, 11),
230 MTK_PIN_IES_SMT_SPEC(43, 45, 0x920, 12),
231 MTK_PIN_IES_SMT_SPEC(46, 49, 0x920, 13),
232 MTK_PIN_IES_SMT_SPEC(50, 52, 0x930, 10),
233 MTK_PIN_IES_SMT_SPEC(53, 56, 0x920, 14),
234 MTK_PIN_IES_SMT_SPEC(57, 58, 0x930, 0),
235 MTK_PIN_IES_SMT_SPEC(59, 65, 0x930, 2),
236 MTK_PIN_IES_SMT_SPEC(66, 71, 0x930, 3),
237 MTK_PIN_IES_SMT_SPEC(72, 74, 0x930, 4),
238 MTK_PIN_IES_SMT_SPEC(75, 76, 0x920, 15),
239 MTK_PIN_IES_SMT_SPEC(77, 78, 0x930, 1),
240 MTK_PIN_IES_SMT_SPEC(79, 82, 0x930, 5),
241 MTK_PIN_IES_SMT_SPEC(83, 84, 0x930, 6),
242 MTK_PIN_IES_SMT_SPEC(85, 85, 0xce0, 11),
243 MTK_PIN_IES_SMT_SPEC(86, 86, 0xcd0, 11),
244 MTK_PIN_IES_SMT_SPEC(87, 87, 0xd00, 3),
245 MTK_PIN_IES_SMT_SPEC(88, 88, 0xd00, 7),
246 MTK_PIN_IES_SMT_SPEC(89, 89, 0xd00, 11),
247 MTK_PIN_IES_SMT_SPEC(90, 90, 0xd00, 15),
248 MTK_PIN_IES_SMT_SPEC(117, 120, 0x930, 7),
249 MTK_PIN_IES_SMT_SPEC(121, 121, 0xc80, 11),
250 MTK_PIN_IES_SMT_SPEC(122, 122, 0xc70, 11),
251 MTK_PIN_IES_SMT_SPEC(123, 123, 0xca0, 3),
252 MTK_PIN_IES_SMT_SPEC(124, 124, 0xca0, 7),
253 MTK_PIN_IES_SMT_SPEC(125, 125, 0xca0, 11),
254 MTK_PIN_IES_SMT_SPEC(126, 126, 0xca0, 15),
255 MTK_PIN_IES_SMT_SPEC(127, 127, 0xc40, 15),
256 MTK_PIN_IES_SMT_SPEC(128, 128, 0xc40, 11),
257 MTK_PIN_IES_SMT_SPEC(129, 129, 0xc40, 7),
258 MTK_PIN_IES_SMT_SPEC(130, 130, 0xc40, 3),
259 MTK_PIN_IES_SMT_SPEC(131, 131, 0xc50, 3),
260 MTK_PIN_IES_SMT_SPEC(132, 132, 0xc10, 11),
261 MTK_PIN_IES_SMT_SPEC(133, 133, 0xc00, 11),
262 MTK_PIN_IES_SMT_SPEC(134, 134, 0xc30, 15),
263 MTK_PIN_IES_SMT_SPEC(135, 135, 0xc30, 11),
264 MTK_PIN_IES_SMT_SPEC(136, 136, 0xc30, 7),
265 MTK_PIN_IES_SMT_SPEC(137, 137, 0xc30, 3),
266 MTK_PIN_IES_SMT_SPEC(138, 141, 0x930, 9),
267 MTK_PIN_IES_SMT_SPEC(142, 142, 0x920, 13),
268};
269
270static int mt8127_ies_smt_set(struct regmap *regmap, unsigned int pin,
271 unsigned char align, int value, enum pin_config_param arg)
272{
273 if (arg == PIN_CONFIG_INPUT_ENABLE)
274 return mtk_pconf_spec_set_ies_smt_range(regmap, mt8127_ies_set,
275 ARRAY_SIZE(mt8127_ies_set), pin, align, value);
276 else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
277 return mtk_pconf_spec_set_ies_smt_range(regmap, mt8127_smt_set,
278 ARRAY_SIZE(mt8127_smt_set), pin, align, value);
279 return -EINVAL;
280}
281
282
283static const struct mtk_pinctrl_devdata mt8127_pinctrl_data = {
284 .pins = mtk_pins_mt8127,
285 .npins = ARRAY_SIZE(mtk_pins_mt8127),
286 .grp_desc = mt8127_drv_grp,
287 .n_grp_cls = ARRAY_SIZE(mt8127_drv_grp),
288 .pin_drv_grp = mt8127_pin_drv,
289 .n_pin_drv_grps = ARRAY_SIZE(mt8127_pin_drv),
290 .spec_pull_set = mt8127_spec_pull_set,
291 .spec_ies_smt_set = mt8127_ies_smt_set,
292 .dir_offset = 0x0000,
293 .pullen_offset = 0x0100,
294 .pullsel_offset = 0x0200,
295 .dout_offset = 0x0400,
296 .din_offset = 0x0500,
297 .pinmux_offset = 0x0600,
298 .type1_start = 143,
299 .type1_end = 143,
300 .port_shf = 4,
301 .port_mask = 0xf,
302 .port_align = 4,
303 .eint_offsets = {
304 .name = "mt8127_eint",
305 .stat = 0x000,
306 .ack = 0x040,
307 .mask = 0x080,
308 .mask_set = 0x0c0,
309 .mask_clr = 0x100,
310 .sens = 0x140,
311 .sens_set = 0x180,
312 .sens_clr = 0x1c0,
313 .soft = 0x200,
314 .soft_set = 0x240,
315 .soft_clr = 0x280,
316 .pol = 0x300,
317 .pol_set = 0x340,
318 .pol_clr = 0x380,
319 .dom_en = 0x400,
320 .dbnc_ctrl = 0x500,
321 .dbnc_set = 0x600,
322 .dbnc_clr = 0x700,
323 .port_mask = 7,
324 .ports = 6,
325 },
326 .ap_num = 143,
327 .db_cnt = 16,
328};
329
330static int mt8127_pinctrl_probe(struct platform_device *pdev)
331{
332 return mtk_pctrl_init(pdev, &mt8127_pinctrl_data, NULL);
333}
334
335static const struct of_device_id mt8127_pctrl_match[] = {
336 { .compatible = "mediatek,mt8127-pinctrl", },
337 { }
338};
339MODULE_DEVICE_TABLE(of, mt8127_pctrl_match);
340
341static struct platform_driver mtk_pinctrl_driver = {
342 .probe = mt8127_pinctrl_probe,
343 .driver = {
344 .name = "mediatek-mt8127-pinctrl",
Yingjoe Chen6acdee82015-05-18 20:01:32 -0700[diff] [blame]345 .of_match_table = mt8127_pctrl_match,
346 },
347};
348
349static int __init mtk_pinctrl_init(void)
350{
351 return platform_driver_register(&mtk_pinctrl_driver);
352}
353
354module_init(mtk_pinctrl_init);
355
356MODULE_LICENSE("GPL v2");
357MODULE_DESCRIPTION("MediaTek MT8127 Pinctrl Driver");
358MODULE_AUTHOR("Yingjoe Chen <yingjoe.chen@mediatek.com>");