| Jiri Olsa | c9b951c | 2014-01-07 13:47:29 +0100 | [diff] [blame] | 1 | #include <errno.h> |
| 2 | #include "perf_regs.h" | ||||
| Jiri Olsa | 0c4e774 | 2014-04-17 19:39:10 +0200 | [diff] [blame] | 3 | #include "event.h" |
| Jiri Olsa | c9b951c | 2014-01-07 13:47:29 +0100 | [diff] [blame] | 4 | |
| Stephane Eranian | af4aead | 2015-09-01 11:30:14 +0200 | [diff] [blame] | 5 | const struct sample_reg __weak sample_reg_masks[] = { |
| 6 | SMPL_REG_END | ||||
| 7 | }; | ||||
| 8 | |||||
| Sukadev Bhattiprolu | 9fb4765 | 2015-09-24 17:53:49 -0400 | [diff] [blame] | 9 | #ifdef HAVE_PERF_REGS_SUPPORT |
| Jiri Olsa | c9b951c | 2014-01-07 13:47:29 +0100 | [diff] [blame] | 10 | int perf_reg_value(u64 *valp, struct regs_dump *regs, int id) |
| 11 | { | ||||
| 12 | int i, idx = 0; | ||||
| 13 | u64 mask = regs->mask; | ||||
| 14 | |||||
| Naveen N. Rao | f478220 | 2016-04-28 15:01:10 +0530 | [diff] [blame] | 15 | if (regs->cache_mask & (1ULL << id)) |
| Jiri Olsa | 0c4e774 | 2014-04-17 19:39:10 +0200 | [diff] [blame] | 16 | goto out; |
| 17 | |||||
| Naveen N. Rao | f478220 | 2016-04-28 15:01:10 +0530 | [diff] [blame] | 18 | if (!(mask & (1ULL << id))) |
| Jiri Olsa | c9b951c | 2014-01-07 13:47:29 +0100 | [diff] [blame] | 19 | return -EINVAL; |
| 20 | |||||
| 21 | for (i = 0; i < id; i++) { | ||||
| Naveen N. Rao | f478220 | 2016-04-28 15:01:10 +0530 | [diff] [blame] | 22 | if (mask & (1ULL << i)) |
| Jiri Olsa | c9b951c | 2014-01-07 13:47:29 +0100 | [diff] [blame] | 23 | idx++; |
| 24 | } | ||||
| 25 | |||||
| Naveen N. Rao | f478220 | 2016-04-28 15:01:10 +0530 | [diff] [blame] | 26 | regs->cache_mask |= (1ULL << id); |
| Jiri Olsa | 0c4e774 | 2014-04-17 19:39:10 +0200 | [diff] [blame] | 27 | regs->cache_regs[id] = regs->regs[idx]; |
| 28 | |||||
| 29 | out: | ||||
| 30 | *valp = regs->cache_regs[id]; | ||||
| Jiri Olsa | c9b951c | 2014-01-07 13:47:29 +0100 | [diff] [blame] | 31 | return 0; |
| 32 | } | ||||
| Sukadev Bhattiprolu | 9fb4765 | 2015-09-24 17:53:49 -0400 | [diff] [blame] | 33 | #endif |