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gerrit-public.fairphone.software / kernel / msm-4.9 / 8e795840e4d89df3d594e736989212ee8a4a1fca / . / drivers / net / ethernet / broadcom / bnx2_fw.h
blob: 7db79c28b5ff53a663f519aed22807de81532794 [file] [log] [blame]
Jitendra Kalsaria28c4ec02014-06-23 15:10:33 -0400[diff] [blame]1/* bnx2_fw.h: QLogic NX2 network driver.
Michael Chanb6016b72005-05-26 13:03:09 -0700[diff] [blame]2 *
Michael Chan110d0ef2007-12-12 11:18:34 -0800[diff] [blame]3 * Copyright (c) 2004, 2005, 2006, 2007 Broadcom Corporation
Jitendra Kalsaria28c4ec02014-06-23 15:10:33 -0400[diff] [blame]4 * Copyright (c) 2014 QLogic Corporation
Michael Chanb6016b72005-05-26 13:03:09 -0700[diff] [blame]5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
Michael Chan57579f72009-04-04 16:51:14 -0700[diff] [blame]8 * the Free Software Foundation.
Michael Chanb6016b72005-05-26 13:03:09 -0700[diff] [blame]9 */
10
Benjamin Li10343cc2008-05-16 22:20:27 -0700[diff] [blame]11/* Initialized Values for the Completion Processor. */
12static const struct cpu_reg cpu_reg_com = {
13 .mode = BNX2_COM_CPU_MODE,
14 .mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT,
15 .mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA,
16 .state = BNX2_COM_CPU_STATE,
17 .state_value_clear = 0xffffff,
18 .gpr0 = BNX2_COM_CPU_REG_FILE,
19 .evmask = BNX2_COM_CPU_EVENT_MASK,
20 .pc = BNX2_COM_CPU_PROGRAM_COUNTER,
21 .inst = BNX2_COM_CPU_INSTRUCTION,
22 .bp = BNX2_COM_CPU_HW_BREAKPOINT,
23 .spad_base = BNX2_COM_SCRATCH,
24 .mips_view_base = 0x8000000,
25};
26
Benjamin Li10343cc2008-05-16 22:20:27 -0700[diff] [blame]27/* Initialized Values the Command Processor. */
28static const struct cpu_reg cpu_reg_cp = {
29 .mode = BNX2_CP_CPU_MODE,
30 .mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT,
31 .mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA,
32 .state = BNX2_CP_CPU_STATE,
33 .state_value_clear = 0xffffff,
34 .gpr0 = BNX2_CP_CPU_REG_FILE,
35 .evmask = BNX2_CP_CPU_EVENT_MASK,
36 .pc = BNX2_CP_CPU_PROGRAM_COUNTER,
37 .inst = BNX2_CP_CPU_INSTRUCTION,
38 .bp = BNX2_CP_CPU_HW_BREAKPOINT,
39 .spad_base = BNX2_CP_SCRATCH,
40 .mips_view_base = 0x8000000,
41};
42
Benjamin Li10343cc2008-05-16 22:20:27 -0700[diff] [blame]43/* Initialized Values for the RX Processor. */
44static const struct cpu_reg cpu_reg_rxp = {
45 .mode = BNX2_RXP_CPU_MODE,
46 .mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT,
47 .mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA,
48 .state = BNX2_RXP_CPU_STATE,
49 .state_value_clear = 0xffffff,
50 .gpr0 = BNX2_RXP_CPU_REG_FILE,
51 .evmask = BNX2_RXP_CPU_EVENT_MASK,
52 .pc = BNX2_RXP_CPU_PROGRAM_COUNTER,
53 .inst = BNX2_RXP_CPU_INSTRUCTION,
54 .bp = BNX2_RXP_CPU_HW_BREAKPOINT,
55 .spad_base = BNX2_RXP_SCRATCH,
56 .mips_view_base = 0x8000000,
57};
58
Benjamin Li10343cc2008-05-16 22:20:27 -0700[diff] [blame]59/* Initialized Values for the TX Patch-up Processor. */
60static const struct cpu_reg cpu_reg_tpat = {
61 .mode = BNX2_TPAT_CPU_MODE,
62 .mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT,
63 .mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA,
64 .state = BNX2_TPAT_CPU_STATE,
65 .state_value_clear = 0xffffff,
66 .gpr0 = BNX2_TPAT_CPU_REG_FILE,
67 .evmask = BNX2_TPAT_CPU_EVENT_MASK,
68 .pc = BNX2_TPAT_CPU_PROGRAM_COUNTER,
69 .inst = BNX2_TPAT_CPU_INSTRUCTION,
70 .bp = BNX2_TPAT_CPU_HW_BREAKPOINT,
71 .spad_base = BNX2_TPAT_SCRATCH,
72 .mips_view_base = 0x8000000,
73};
74
Benjamin Li10343cc2008-05-16 22:20:27 -0700[diff] [blame]75/* Initialized Values for the TX Processor. */
76static const struct cpu_reg cpu_reg_txp = {
77 .mode = BNX2_TXP_CPU_MODE,
78 .mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT,
79 .mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA,
80 .state = BNX2_TXP_CPU_STATE,
81 .state_value_clear = 0xffffff,
82 .gpr0 = BNX2_TXP_CPU_REG_FILE,
83 .evmask = BNX2_TXP_CPU_EVENT_MASK,
84 .pc = BNX2_TXP_CPU_PROGRAM_COUNTER,
85 .inst = BNX2_TXP_CPU_INSTRUCTION,
86 .bp = BNX2_TXP_CPU_HW_BREAKPOINT,
87 .spad_base = BNX2_TXP_SCRATCH,
88 .mips_view_base = 0x8000000,
89};