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gerrit-public.fairphone.software / kernel / msm-4.9 / 8e8459719cd129e6a91ebfcd46f68f8396f8f735 / . / arch / arm / boot / dts / tegra20-harmony.dts
blob: b926a07b944303fb24468d6899bc9324c7c956bb [file] [log] [blame]
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]1/dts-v1/;
2
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530[diff] [blame]3#include <dt-bindings/input/input.h>
Stephen Warren1bd0bd42012-10-17 16:38:21 -0600[diff] [blame]4#include "tegra20.dtsi"
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]5
6/ {
Bryan Wu8fef5df2012-12-20 09:41:29 +0000[diff] [blame]7 model = "NVIDIA Tegra20 Harmony evaluation board";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]8 compatible = "nvidia,harmony", "nvidia,tegra20";
9
Stephen Warren553c0a22013-12-09 14:43:59 -0700[diff] [blame]10 aliases {
11 rtc0 = "/i2c@7000d000/tps6586x@34";
12 rtc1 = "/rtc@7000e000";
Olof Johanssonc4574aa2014-11-11 12:49:30 -0800[diff] [blame]13 serial0 = &uartd;
Stephen Warren553c0a22013-12-09 14:43:59 -0700[diff] [blame]14 };
15
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]16 memory {
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]17 reg = <0x00000000 0x40000000>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]18 };
19
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]20 host1x@50000000 {
Thierry Reding1d4e0682013-12-19 16:59:25 +0100[diff] [blame]21 dc@54200000 {
22 rgb {
23 status = "okay";
24
25 nvidia,panel = <&panel>;
26 };
27 };
28
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]29 hdmi@54280000 {
Stephen Warren20ffbd72012-11-09 16:58:11 -0700[diff] [blame]30 status = "okay";
31
Thierry Redingad0acf72014-04-25 17:44:48 +0200[diff] [blame]32 hdmi-supply = <&vdd_5v0_hdmi>;
Stephen Warren20ffbd72012-11-09 16:58:11 -0700[diff] [blame]33 vdd-supply = <&hdmi_vdd_reg>;
34 pll-supply = <&hdmi_pll_reg>;
35
36 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]37 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
38 GPIO_ACTIVE_HIGH>;
Stephen Warren20ffbd72012-11-09 16:58:11 -0700[diff] [blame]39 };
40 };
41
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]42 pinmux@70000014 {
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]43 pinctrl-names = "default";
44 pinctrl-0 = <&state_default>;
45
46 state_default: pinmux {
47 ata {
48 nvidia,pins = "ata";
49 nvidia,function = "ide";
50 };
51 atb {
52 nvidia,pins = "atb", "gma", "gme";
53 nvidia,function = "sdio4";
54 };
55 atc {
56 nvidia,pins = "atc";
57 nvidia,function = "nand";
58 };
59 atd {
60 nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
61 "spia", "spib", "spic";
62 nvidia,function = "gmi";
63 };
64 cdev1 {
65 nvidia,pins = "cdev1";
66 nvidia,function = "plla_out";
67 };
68 cdev2 {
69 nvidia,pins = "cdev2";
70 nvidia,function = "pllp_out4";
71 };
72 crtp {
73 nvidia,pins = "crtp";
74 nvidia,function = "crt";
75 };
76 csus {
77 nvidia,pins = "csus";
78 nvidia,function = "vi_sensor_clk";
79 };
80 dap1 {
81 nvidia,pins = "dap1";
82 nvidia,function = "dap1";
83 };
84 dap2 {
85 nvidia,pins = "dap2";
86 nvidia,function = "dap2";
87 };
88 dap3 {
89 nvidia,pins = "dap3";
90 nvidia,function = "dap3";
91 };
92 dap4 {
93 nvidia,pins = "dap4";
94 nvidia,function = "dap4";
95 };
96 ddc {
97 nvidia,pins = "ddc";
98 nvidia,function = "i2c2";
99 };
100 dta {
101 nvidia,pins = "dta", "dtd";
102 nvidia,function = "sdio2";
103 };
104 dtb {
105 nvidia,pins = "dtb", "dtc", "dte";
106 nvidia,function = "rsvd1";
107 };
108 dtf {
109 nvidia,pins = "dtf";
110 nvidia,function = "i2c3";
111 };
112 gmc {
113 nvidia,pins = "gmc";
114 nvidia,function = "uartd";
115 };
116 gpu7 {
117 nvidia,pins = "gpu7";
118 nvidia,function = "rtck";
119 };
120 gpv {
121 nvidia,pins = "gpv", "slxa", "slxk";
122 nvidia,function = "pcie";
123 };
124 hdint {
125 nvidia,pins = "hdint", "pta";
126 nvidia,function = "hdmi";
127 };
128 i2cp {
129 nvidia,pins = "i2cp";
130 nvidia,function = "i2cp";
131 };
132 irrx {
133 nvidia,pins = "irrx", "irtx";
134 nvidia,function = "uarta";
135 };
136 kbca {
137 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
138 "kbce", "kbcf";
139 nvidia,function = "kbc";
140 };
141 lcsn {
142 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
143 "ld3", "ld4", "ld5", "ld6", "ld7",
144 "ld8", "ld9", "ld10", "ld11", "ld12",
145 "ld13", "ld14", "ld15", "ld16", "ld17",
146 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
147 "lhs", "lm0", "lm1", "lpp", "lpw0",
148 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
149 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
150 "lvs";
151 nvidia,function = "displaya";
152 };
153 owc {
154 nvidia,pins = "owc", "spdi", "spdo", "uac";
155 nvidia,function = "rsvd2";
156 };
157 pmc {
158 nvidia,pins = "pmc";
159 nvidia,function = "pwr_on";
160 };
161 rm {
162 nvidia,pins = "rm";
163 nvidia,function = "i2c1";
164 };
165 sdb {
166 nvidia,pins = "sdb", "sdc", "sdd";
167 nvidia,function = "pwm";
168 };
169 sdio1 {
170 nvidia,pins = "sdio1";
171 nvidia,function = "sdio1";
172 };
173 slxc {
174 nvidia,pins = "slxc", "slxd";
175 nvidia,function = "spdif";
176 };
177 spid {
178 nvidia,pins = "spid", "spie", "spif";
179 nvidia,function = "spi1";
180 };
181 spig {
182 nvidia,pins = "spig", "spih";
183 nvidia,function = "spi2_alt";
184 };
185 uaa {
186 nvidia,pins = "uaa", "uab", "uda";
187 nvidia,function = "ulpi";
188 };
189 uad {
190 nvidia,pins = "uad";
191 nvidia,function = "irda";
192 };
193 uca {
194 nvidia,pins = "uca", "ucb";
195 nvidia,function = "uartc";
196 };
197 conf_ata {
198 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
Stephen Warren563da212012-04-13 16:35:20 -0600[diff] [blame]199 "cdev1", "cdev2", "dap1", "dtb", "gma",
200 "gmb", "gmc", "gmd", "gme", "gpu7",
201 "gpv", "i2cp", "pta", "rm", "slxa",
202 "slxk", "spia", "spib", "uac";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]203 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
204 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]205 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]206 conf_ck32 {
207 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
208 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]209 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]210 };
Stephen Warren563da212012-04-13 16:35:20 -0600[diff] [blame]211 conf_csus {
212 nvidia,pins = "csus", "spid", "spif";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]213 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
214 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren563da212012-04-13 16:35:20 -0600[diff] [blame]215 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]216 conf_crtp {
217 nvidia,pins = "crtp", "dap2", "dap3", "dap4",
218 "dtc", "dte", "dtf", "gpu", "sdio1",
219 "slxc", "slxd", "spdi", "spdo", "spig",
Stephen Warren563da212012-04-13 16:35:20 -0600[diff] [blame]220 "uda";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]221 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
222 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]223 };
224 conf_ddc {
225 nvidia,pins = "ddc", "dta", "dtd", "kbca",
226 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
227 "sdc";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]228 nvidia,pull = <TEGRA_PIN_PULL_UP>;
229 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]230 };
231 conf_hdint {
232 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
233 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
234 "lvp0", "owc", "sdb";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]235 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]236 };
237 conf_irrx {
238 nvidia,pins = "irrx", "irtx", "sdd", "spic",
239 "spie", "spih", "uaa", "uab", "uad",
240 "uca", "ucb";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]241 nvidia,pull = <TEGRA_PIN_PULL_UP>;
242 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]243 };
244 conf_lc {
245 nvidia,pins = "lc", "ls";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]246 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]247 };
248 conf_ld0 {
249 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
250 "ld5", "ld6", "ld7", "ld8", "ld9",
251 "ld10", "ld11", "ld12", "ld13", "ld14",
252 "ld15", "ld16", "ld17", "ldi", "lhp0",
253 "lhp1", "lhp2", "lhs", "lm0", "lpp",
254 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
255 "lvs", "pmc";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]256 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]257 };
258 conf_ld17_0 {
259 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
260 "ld23_22";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]261 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]262 };
263 };
264 };
265
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]266 i2s@70002800 {
267 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]268 };
269
270 serial@70006300 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]271 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]272 };
273
Thierry Reding1d4e0682013-12-19 16:59:25 +0100[diff] [blame]274 pwm: pwm@7000a000 {
275 status = "okay";
276 };
277
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]278 i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]279 status = "okay";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]280 clock-frequency = <400000>;
281
Stephen Warren797acf72012-01-11 16:09:57 -0700[diff] [blame]282 wm8903: wm8903@1a {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]283 compatible = "wlf,wm8903";
284 reg = <0x1a>;
Stephen Warren797acf72012-01-11 16:09:57 -0700[diff] [blame]285 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700[diff] [blame]286 interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]287
288 gpio-controller;
289 #gpio-cells = <2>;
290
Stephen Warren797acf72012-01-11 16:09:57 -0700[diff] [blame]291 micdet-cfg = <0>;
292 micdet-delay = <100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]293 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]294 };
295 };
296
Stephen Warren20ffbd72012-11-09 16:58:11 -0700[diff] [blame]297 hdmi_ddc: i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]298 status = "okay";
Stephen Warren20ffbd72012-11-09 16:58:11 -0700[diff] [blame]299 clock-frequency = <100000>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]300 };
301
302 i2c@7000c500 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]303 status = "okay";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]304 clock-frequency = <400000>;
305 };
306
307 i2c@7000d000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]308 status = "okay";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]309 clock-frequency = <400000>;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]310
311 pmic: tps6586x@34 {
312 compatible = "ti,tps6586x";
313 reg = <0x34>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700[diff] [blame]314 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]315
Stephen Warrenbe972c32012-09-11 11:40:04 -0600[diff] [blame]316 ti,system-power-controller;
317
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]318 #gpio-cells = <2>;
319 gpio-controller;
320
321 sys-supply = <&vdd_5v0_reg>;
322 vin-sm0-supply = <&sys_reg>;
323 vin-sm1-supply = <&sys_reg>;
324 vin-sm2-supply = <&sys_reg>;
325 vinldo01-supply = <&sm2_reg>;
326 vinldo23-supply = <&sm2_reg>;
327 vinldo4-supply = <&sm2_reg>;
328 vinldo678-supply = <&sm2_reg>;
329 vinldo9-supply = <&sm2_reg>;
330
331 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]332 sys_reg: sys {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]333 regulator-name = "vdd_sys";
334 regulator-always-on;
335 };
336
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]337 sm0 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]338 regulator-name = "vdd_sm0,vdd_core";
339 regulator-min-microvolt = <1200000>;
340 regulator-max-microvolt = <1200000>;
341 regulator-always-on;
342 };
343
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]344 sm1 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]345 regulator-name = "vdd_sm1,vdd_cpu";
346 regulator-min-microvolt = <1000000>;
347 regulator-max-microvolt = <1000000>;
348 regulator-always-on;
349 };
350
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]351 sm2_reg: sm2 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]352 regulator-name = "vdd_sm2,vin_ldo*";
353 regulator-min-microvolt = <3700000>;
354 regulator-max-microvolt = <3700000>;
355 regulator-always-on;
356 };
357
Thierry Reding722afc12013-08-09 16:49:22 +0200[diff] [blame]358 pci_clk_reg: ldo0 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]359 regulator-name = "vdd_ldo0,vddio_pex_clk";
360 regulator-min-microvolt = <3300000>;
361 regulator-max-microvolt = <3300000>;
362 };
363
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]364 ldo1 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]365 regulator-name = "vdd_ldo1,avdd_pll*";
366 regulator-min-microvolt = <1100000>;
367 regulator-max-microvolt = <1100000>;
368 regulator-always-on;
369 };
370
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]371 ldo2 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]372 regulator-name = "vdd_ldo2,vdd_rtc";
373 regulator-min-microvolt = <1200000>;
374 regulator-max-microvolt = <1200000>;
375 };
376
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]377 ldo3 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]378 regulator-name = "vdd_ldo3,avdd_usb*";
379 regulator-min-microvolt = <3300000>;
380 regulator-max-microvolt = <3300000>;
381 regulator-always-on;
382 };
383
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]384 ldo4 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]385 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
386 regulator-min-microvolt = <1800000>;
387 regulator-max-microvolt = <1800000>;
388 regulator-always-on;
389 };
390
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]391 ldo5 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]392 regulator-name = "vdd_ldo5,vcore_mmc";
393 regulator-min-microvolt = <2850000>;
394 regulator-max-microvolt = <2850000>;
395 regulator-always-on;
396 };
397
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]398 ldo6 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]399 regulator-name = "vdd_ldo6,avdd_vdac";
400 regulator-min-microvolt = <1800000>;
401 regulator-max-microvolt = <1800000>;
402 };
403
Stephen Warren20ffbd72012-11-09 16:58:11 -0700[diff] [blame]404 hdmi_vdd_reg: ldo7 {
Stephen Warren740418e2012-09-20 15:20:39 -0600[diff] [blame]405 regulator-name = "vdd_ldo7,avdd_hdmi";
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]406 regulator-min-microvolt = <3300000>;
407 regulator-max-microvolt = <3300000>;
408 };
409
Stephen Warren20ffbd72012-11-09 16:58:11 -0700[diff] [blame]410 hdmi_pll_reg: ldo8 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]411 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
412 regulator-min-microvolt = <1800000>;
413 regulator-max-microvolt = <1800000>;
414 };
415
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]416 ldo9 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]417 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
418 regulator-min-microvolt = <2850000>;
419 regulator-max-microvolt = <2850000>;
420 regulator-always-on;
421 };
422
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]423 ldo_rtc {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]424 regulator-name = "vdd_rtc_out,vdd_cell";
425 regulator-min-microvolt = <3300000>;
426 regulator-max-microvolt = <3300000>;
427 regulator-always-on;
428 };
429 };
430 };
Thierry Reding42d25342012-11-09 22:58:43 +0100[diff] [blame]431
432 temperature-sensor@4c {
433 compatible = "adi,adt7461";
434 reg = <0x4c>;
435 };
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]436 };
437
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]438 kbc@7000e200 {
Laxman Dewanganc0967ce2013-01-21 23:14:05 +0530[diff] [blame]439 status = "okay";
440 nvidia,debounce-delay-ms = <2>;
441 nvidia,repeat-delay-ms = <160>;
442 nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
443 nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530[diff] [blame]444 linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W)
445 MATRIX_KEY(0x00, 0x03, KEY_S)
446 MATRIX_KEY(0x00, 0x04, KEY_A)
447 MATRIX_KEY(0x00, 0x05, KEY_Z)
448 MATRIX_KEY(0x00, 0x07, KEY_FN)
449 MATRIX_KEY(0x01, 0x07, KEY_MENU)
450 MATRIX_KEY(0x02, 0x06, KEY_LEFTALT)
451 MATRIX_KEY(0x02, 0x07, KEY_RIGHTALT)
452 MATRIX_KEY(0x03, 0x00, KEY_5)
453 MATRIX_KEY(0x03, 0x01, KEY_4)
454 MATRIX_KEY(0x03, 0x02, KEY_R)
455 MATRIX_KEY(0x03, 0x03, KEY_E)
456 MATRIX_KEY(0x03, 0x04, KEY_F)
457 MATRIX_KEY(0x03, 0x05, KEY_D)
458 MATRIX_KEY(0x03, 0x06, KEY_X)
459 MATRIX_KEY(0x04, 0x00, KEY_7)
460 MATRIX_KEY(0x04, 0x01, KEY_6)
461 MATRIX_KEY(0x04, 0x02, KEY_T)
462 MATRIX_KEY(0x04, 0x03, KEY_H)
463 MATRIX_KEY(0x04, 0x04, KEY_G)
464 MATRIX_KEY(0x04, 0x05, KEY_V)
465 MATRIX_KEY(0x04, 0x06, KEY_C)
466 MATRIX_KEY(0x04, 0x07, KEY_SPACE)
467 MATRIX_KEY(0x05, 0x00, KEY_9)
468 MATRIX_KEY(0x05, 0x01, KEY_8)
469 MATRIX_KEY(0x05, 0x02, KEY_U)
470 MATRIX_KEY(0x05, 0x03, KEY_Y)
471 MATRIX_KEY(0x05, 0x04, KEY_J)
472 MATRIX_KEY(0x05, 0x05, KEY_N)
473 MATRIX_KEY(0x05, 0x06, KEY_B)
474 MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH)
475 MATRIX_KEY(0x06, 0x00, KEY_MINUS)
476 MATRIX_KEY(0x06, 0x01, KEY_0)
477 MATRIX_KEY(0x06, 0x02, KEY_O)
478 MATRIX_KEY(0x06, 0x03, KEY_I)
479 MATRIX_KEY(0x06, 0x04, KEY_L)
480 MATRIX_KEY(0x06, 0x05, KEY_K)
481 MATRIX_KEY(0x06, 0x06, KEY_COMMA)
482 MATRIX_KEY(0x06, 0x07, KEY_M)
483 MATRIX_KEY(0x07, 0x01, KEY_EQUAL)
484 MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE)
485 MATRIX_KEY(0x07, 0x03, KEY_ENTER)
486 MATRIX_KEY(0x07, 0x07, KEY_MENU)
487 MATRIX_KEY(0x08, 0x04, KEY_LEFTSHIFT)
488 MATRIX_KEY(0x08, 0x05, KEY_RIGHTSHIFT)
489 MATRIX_KEY(0x09, 0x05, KEY_LEFTCTRL)
490 MATRIX_KEY(0x09, 0x07, KEY_RIGHTCTRL)
491 MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE)
492 MATRIX_KEY(0x0B, 0x01, KEY_P)
493 MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE)
494 MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON)
495 MATRIX_KEY(0x0B, 0x04, KEY_SLASH)
496 MATRIX_KEY(0x0B, 0x05, KEY_DOT)
497 MATRIX_KEY(0x0C, 0x00, KEY_F10)
498 MATRIX_KEY(0x0C, 0x01, KEY_F9)
499 MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE)
500 MATRIX_KEY(0x0C, 0x03, KEY_3)
501 MATRIX_KEY(0x0C, 0x04, KEY_2)
502 MATRIX_KEY(0x0C, 0x05, KEY_UP)
503 MATRIX_KEY(0x0C, 0x06, KEY_PRINT)
504 MATRIX_KEY(0x0C, 0x07, KEY_PAUSE)
505 MATRIX_KEY(0x0D, 0x00, KEY_INSERT)
506 MATRIX_KEY(0x0D, 0x01, KEY_DELETE)
507 MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP )
508 MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN)
509 MATRIX_KEY(0x0D, 0x05, KEY_RIGHT)
510 MATRIX_KEY(0x0D, 0x06, KEY_DOWN)
511 MATRIX_KEY(0x0D, 0x07, KEY_LEFT)
512 MATRIX_KEY(0x0E, 0x00, KEY_F11)
513 MATRIX_KEY(0x0E, 0x01, KEY_F12)
514 MATRIX_KEY(0x0E, 0x02, KEY_F8)
515 MATRIX_KEY(0x0E, 0x03, KEY_Q)
516 MATRIX_KEY(0x0E, 0x04, KEY_F4)
517 MATRIX_KEY(0x0E, 0x05, KEY_F3)
518 MATRIX_KEY(0x0E, 0x06, KEY_1)
519 MATRIX_KEY(0x0E, 0x07, KEY_F7)
520 MATRIX_KEY(0x0F, 0x00, KEY_ESC)
521 MATRIX_KEY(0x0F, 0x01, KEY_GRAVE)
522 MATRIX_KEY(0x0F, 0x02, KEY_F5)
523 MATRIX_KEY(0x0F, 0x03, KEY_TAB)
524 MATRIX_KEY(0x0F, 0x04, KEY_F1)
525 MATRIX_KEY(0x0F, 0x05, KEY_F2)
526 MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK)
527 MATRIX_KEY(0x0F, 0x07, KEY_F6)
528 MATRIX_KEY(0x14, 0x00, KEY_KP7)
529 MATRIX_KEY(0x15, 0x00, KEY_KP9)
530 MATRIX_KEY(0x15, 0x01, KEY_KP8)
531 MATRIX_KEY(0x15, 0x02, KEY_KP4)
532 MATRIX_KEY(0x15, 0x04, KEY_KP1)
533 MATRIX_KEY(0x16, 0x01, KEY_KPSLASH)
534 MATRIX_KEY(0x16, 0x02, KEY_KP6)
535 MATRIX_KEY(0x16, 0x03, KEY_KP5)
536 MATRIX_KEY(0x16, 0x04, KEY_KP3)
537 MATRIX_KEY(0x16, 0x05, KEY_KP2)
538 MATRIX_KEY(0x16, 0x07, KEY_KP0)
539 MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK)
540 MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS)
541 MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS)
542 MATRIX_KEY(0x1B, 0x05, KEY_KPDOT)
543 MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP)
544 MATRIX_KEY(0x1D, 0x03, KEY_HOME)
545 MATRIX_KEY(0x1D, 0x04, KEY_END)
546 MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSUP)
547 MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN)
548 MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSDOWN)
549 MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK)
550 MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK)
551 MATRIX_KEY(0x1E, 0x02, KEY_MUTE)
552 MATRIX_KEY(0x1F, 0x04, KEY_QUESTION)>;
Laxman Dewanganc0967ce2013-01-21 23:14:05 +0530[diff] [blame]553 };
554
Stephen Warren57899052013-11-26 14:43:45 -0700[diff] [blame]555 pmc@7000e400 {
556 nvidia,invert-interrupt;
557 nvidia,suspend-mode = <1>;
558 nvidia,cpu-pwr-good-time = <5000>;
559 nvidia,cpu-pwr-off-time = <5000>;
560 nvidia,core-pwr-good-time = <3845 3845>;
561 nvidia,core-pwr-off-time = <3875>;
562 nvidia,sys-clock-req-active-high;
563 };
564
565 pcie-controller@80003000 {
Thierry Redingcca86142014-05-28 16:49:12 +0200[diff] [blame]566 status = "okay";
567
568 avdd-pex-supply = <&pci_vdd_reg>;
569 vdd-pex-supply = <&pci_vdd_reg>;
570 avdd-pex-pll-supply = <&pci_vdd_reg>;
571 avdd-plle-supply = <&pci_vdd_reg>;
572 vddio-pex-clk-supply = <&pci_clk_reg>;
573
Stephen Warren57899052013-11-26 14:43:45 -0700[diff] [blame]574 pci@1,0 {
575 status = "okay";
576 };
577
578 pci@2,0 {
579 status = "okay";
580 };
581 };
582
583 usb@c5000000 {
584 status = "okay";
585 };
586
587 usb-phy@c5000000 {
588 status = "okay";
589 };
590
591 usb@c5004000 {
592 status = "okay";
593 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
594 GPIO_ACTIVE_LOW>;
595 };
596
597 usb-phy@c5004000 {
598 status = "okay";
599 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
600 GPIO_ACTIVE_LOW>;
601 };
602
603 usb@c5008000 {
604 status = "okay";
605 };
606
607 usb-phy@c5008000 {
608 status = "okay";
609 };
610
611 sdhci@c8000200 {
612 status = "okay";
613 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
614 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
615 power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
616 bus-width = <4>;
617 };
618
619 sdhci@c8000600 {
620 status = "okay";
621 cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
622 wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
623 power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
624 bus-width = <8>;
625 };
626
Thierry Reding1d4e0682013-12-19 16:59:25 +0100[diff] [blame]627 backlight: backlight {
628 compatible = "pwm-backlight";
629
630 enable-gpios = <&gpio TEGRA_GPIO(B, 5) GPIO_ACTIVE_HIGH>;
631 power-supply = <&vdd_bl_reg>;
632 pwms = <&pwm 0 5000000>;
633
634 brightness-levels = <0 4 8 16 32 64 128 255>;
635 default-brightness-level = <6>;
636 };
637
Stephen Warren57899052013-11-26 14:43:45 -0700[diff] [blame]638 clocks {
639 compatible = "simple-bus";
640 #address-cells = <1>;
641 #size-cells = <0>;
642
643 clk32k_in: clock@0 {
644 compatible = "fixed-clock";
645 reg=<0>;
646 #clock-cells = <0>;
647 clock-frequency = <32768>;
648 };
649 };
650
651 gpio-keys {
652 compatible = "gpio-keys";
653
654 power {
655 label = "Power";
656 gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530[diff] [blame]657 linux,code = <KEY_POWER>;
Stephen Warren57899052013-11-26 14:43:45 -0700[diff] [blame]658 gpio-key,wakeup;
659 };
660 };
661
Thierry Reding1d4e0682013-12-19 16:59:25 +0100[diff] [blame]662 panel: panel {
663 compatible = "auo,b101aw03", "simple-panel";
664
665 power-supply = <&vdd_pnl_reg>;
666 enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
667
668 backlight = <&backlight>;
669 };
670
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]671 regulators {
672 compatible = "simple-bus";
673 #address-cells = <1>;
674 #size-cells = <0>;
675
676 vdd_5v0_reg: regulator@0 {
677 compatible = "regulator-fixed";
678 reg = <0>;
679 regulator-name = "vdd_5v0";
680 regulator-min-microvolt = <5000000>;
681 regulator-max-microvolt = <5000000>;
682 regulator-always-on;
683 };
684
685 regulator@1 {
686 compatible = "regulator-fixed";
687 reg = <1>;
688 regulator-name = "vdd_1v5";
689 regulator-min-microvolt = <1500000>;
690 regulator-max-microvolt = <1500000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]691 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]692 };
693
694 regulator@2 {
695 compatible = "regulator-fixed";
696 reg = <2>;
697 regulator-name = "vdd_1v2";
698 regulator-min-microvolt = <1200000>;
699 regulator-max-microvolt = <1200000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]700 gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]701 enable-active-high;
702 };
703
Thierry Reding722afc12013-08-09 16:49:22 +0200[diff] [blame]704 pci_vdd_reg: regulator@3 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]705 compatible = "regulator-fixed";
706 reg = <3>;
707 regulator-name = "vdd_1v05";
708 regulator-min-microvolt = <1050000>;
709 regulator-max-microvolt = <1050000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]710 gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]711 enable-active-high;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]712 };
713
Thierry Reding1d4e0682013-12-19 16:59:25 +0100[diff] [blame]714 vdd_pnl_reg: regulator@4 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]715 compatible = "regulator-fixed";
716 reg = <4>;
717 regulator-name = "vdd_pnl";
718 regulator-min-microvolt = <2800000>;
719 regulator-max-microvolt = <2800000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]720 gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]721 enable-active-high;
722 };
723
Thierry Reding1d4e0682013-12-19 16:59:25 +0100[diff] [blame]724 vdd_bl_reg: regulator@5 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]725 compatible = "regulator-fixed";
726 reg = <5>;
727 regulator-name = "vdd_bl";
728 regulator-min-microvolt = <2800000>;
729 regulator-max-microvolt = <2800000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]730 gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]731 enable-active-high;
732 };
Thierry Redingad0acf72014-04-25 17:44:48 +0200[diff] [blame]733
734 vdd_5v0_hdmi: regulator@6 {
735 compatible = "regulator-fixed";
736 reg = <6>;
737 regulator-name = "VDDIO_HDMI";
738 regulator-min-microvolt = <5000000>;
739 regulator-max-microvolt = <5000000>;
740 gpio = <&gpio TEGRA_GPIO(T, 2) GPIO_ACTIVE_HIGH>;
741 enable-active-high;
742 vin-supply = <&vdd_5v0_reg>;
743 };
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]744 };
745
Stephen Warren797acf72012-01-11 16:09:57 -0700[diff] [blame]746 sound {
747 compatible = "nvidia,tegra-audio-wm8903-harmony",
748 "nvidia,tegra-audio-wm8903";
749 nvidia,model = "NVIDIA Tegra Harmony";
750
751 nvidia,audio-routing =
752 "Headphone Jack", "HPOUTR",
753 "Headphone Jack", "HPOUTL",
754 "Int Spk", "ROP",
755 "Int Spk", "RON",
756 "Int Spk", "LOP",
757 "Int Spk", "LON",
758 "Mic Jack", "MICBIAS",
759 "IN1L", "Mic Jack";
760
761 nvidia,i2s-controller = <&tegra_i2s1>;
762 nvidia,audio-codec = <&wm8903>;
763
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]764 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
765 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
766 GPIO_ACTIVE_HIGH>;
767 nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
768 GPIO_ACTIVE_HIGH>;
769 nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
770 GPIO_ACTIVE_HIGH>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600[diff] [blame]771
Hiroshi Doyu885a8cf2013-05-22 19:45:32 +0300[diff] [blame]772 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
773 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
774 <&tegra_car TEGRA20_CLK_CDEV1>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600[diff] [blame]775 clock-names = "pll_a", "pll_a_out0", "mclk";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]776 };
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]777};