Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1 | /******************************************************************************* |
| 2 | |
| 3 | Intel 10 Gigabit PCI Express Linux driver |
Don Skidmore | 9497182 | 2012-01-06 03:24:16 +0000 | [diff] [blame] | 4 | Copyright(c) 1999 - 2012 Intel Corporation. |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 5 | |
| 6 | This program is free software; you can redistribute it and/or modify it |
| 7 | under the terms and conditions of the GNU General Public License, |
| 8 | version 2, as published by the Free Software Foundation. |
| 9 | |
| 10 | This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | more details. |
| 14 | |
| 15 | You should have received a copy of the GNU General Public License along with |
| 16 | this program; if not, write to the Free Software Foundation, Inc., |
| 17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 18 | |
| 19 | The full GNU General Public License is included in this distribution in |
| 20 | the file called "COPYING". |
| 21 | |
| 22 | Contact Information: |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
| 24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 25 | |
| 26 | *******************************************************************************/ |
| 27 | |
| 28 | #ifndef _IXGBE_TYPE_H_ |
| 29 | #define _IXGBE_TYPE_H_ |
| 30 | |
| 31 | #include <linux/types.h> |
Ben Hutchings | 6b73e10 | 2009-04-29 08:08:58 +0000 | [diff] [blame] | 32 | #include <linux/mdio.h> |
Jiri Pirko | 32e7bfc | 2010-01-25 13:36:10 -0800 | [diff] [blame] | 33 | #include <linux/netdevice.h> |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 34 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 35 | /* Device IDs */ |
Don Skidmore | 1e336d0 | 2009-01-26 20:57:51 -0800 | [diff] [blame] | 36 | #define IXGBE_DEV_ID_82598 0x10B6 |
Don Skidmore | 2f21bdd | 2009-02-01 01:18:23 -0800 | [diff] [blame] | 37 | #define IXGBE_DEV_ID_82598_BX 0x1508 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 38 | #define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6 |
| 39 | #define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7 |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 40 | #define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB |
Jesse Brandeburg | 0befdb3 | 2008-10-31 00:46:40 -0700 | [diff] [blame] | 41 | #define IXGBE_DEV_ID_82598AT 0x10C8 |
Peter P Waskiewicz Jr | 3845bec | 2009-07-16 15:50:52 +0000 | [diff] [blame] | 42 | #define IXGBE_DEV_ID_82598AT2 0x150B |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 43 | #define IXGBE_DEV_ID_82598EB_CX4 0x10DD |
Jesse Brandeburg | 8d792cd | 2008-08-08 16:24:19 -0700 | [diff] [blame] | 44 | #define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 45 | #define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1 |
| 46 | #define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1 |
Jesse Brandeburg | b95f5fc | 2008-09-11 19:58:59 -0700 | [diff] [blame] | 47 | #define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4 |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 48 | #define IXGBE_DEV_ID_82599_KX4 0x10F7 |
Don Skidmore | dbfec66 | 2009-10-02 08:58:25 +0000 | [diff] [blame] | 49 | #define IXGBE_DEV_ID_82599_KX4_MEZZ 0x1514 |
Don Skidmore | 74757d4 | 2009-12-08 07:22:23 +0000 | [diff] [blame] | 50 | #define IXGBE_DEV_ID_82599_KR 0x1517 |
Mallikarjuna R Chilakala | 119fc60 | 2010-05-20 23:07:06 -0700 | [diff] [blame] | 51 | #define IXGBE_DEV_ID_82599_T3_LOM 0x151C |
Peter P Waskiewicz Jr | 8911184 | 2009-09-14 07:47:49 +0000 | [diff] [blame] | 52 | #define IXGBE_DEV_ID_82599_CX4 0x10F9 |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 53 | #define IXGBE_DEV_ID_82599_SFP 0x10FB |
Don Skidmore | dbffcb2 | 2010-12-03 03:32:34 +0000 | [diff] [blame] | 54 | #define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152a |
| 55 | #define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529 |
Don Skidmore | 0b077fe | 2010-12-03 03:32:13 +0000 | [diff] [blame] | 56 | #define IXGBE_SUBDEV_ID_82599_SFP 0x11A9 |
Don Skidmore | b6dfd93 | 2012-07-11 07:17:42 +0000 | [diff] [blame] | 57 | #define IXGBE_SUBDEV_ID_82599_RNDC 0x1F72 |
Don Skidmore | 0e22d04 | 2011-12-10 06:49:43 +0000 | [diff] [blame] | 58 | #define IXGBE_SUBDEV_ID_82599_560FLR 0x17D0 |
Emil Tantilov | f8a06c2 | 2012-08-16 08:13:07 +0000 | [diff] [blame] | 59 | #define IXGBE_SUBDEV_ID_82599_ECNA_DP 0x0470 |
Don Skidmore | 38ad1c8 | 2009-10-08 15:35:58 +0000 | [diff] [blame] | 60 | #define IXGBE_DEV_ID_82599_SFP_EM 0x1507 |
Emil Tantilov | 4c40ef0 | 2011-03-24 07:06:02 +0000 | [diff] [blame] | 61 | #define IXGBE_DEV_ID_82599_SFP_SF2 0x154D |
Emil Tantilov | 7d14528 | 2011-09-08 08:30:14 +0000 | [diff] [blame] | 62 | #define IXGBE_DEV_ID_82599EN_SFP 0x1557 |
Peter P Waskiewicz Jr | 1fcf03e | 2009-05-17 20:58:04 +0000 | [diff] [blame] | 63 | #define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC |
Don Skidmore | 312eb93 | 2009-10-02 08:58:04 +0000 | [diff] [blame] | 64 | #define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8 |
Alexander Duyck | 50d6c68 | 2010-11-16 19:27:05 -0800 | [diff] [blame] | 65 | #define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C |
Don Skidmore | 4f6290c | 2011-05-14 06:36:35 +0000 | [diff] [blame] | 66 | #define IXGBE_DEV_ID_82599_LS 0x154F |
Don Skidmore | b93a222 | 2010-11-16 19:27:17 -0800 | [diff] [blame] | 67 | #define IXGBE_DEV_ID_X540T 0x1528 |
Emil Tantilov | 9e791e4 | 2011-11-04 06:43:29 +0000 | [diff] [blame] | 68 | #define IXGBE_DEV_ID_82599_SFP_SF_QP 0x154A |
joshua.a.hay@intel.com | df376f0 | 2012-09-21 00:08:21 +0000 | [diff] [blame] | 69 | #define IXGBE_DEV_ID_X540T1 0x1560 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 70 | |
Greg Rose | c6bda30 | 2011-08-24 02:37:55 +0000 | [diff] [blame] | 71 | /* VF Device IDs */ |
| 72 | #define IXGBE_DEV_ID_82599_VF 0x10ED |
| 73 | #define IXGBE_DEV_ID_X540_VF 0x1515 |
| 74 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 75 | /* General Registers */ |
| 76 | #define IXGBE_CTRL 0x00000 |
| 77 | #define IXGBE_STATUS 0x00008 |
| 78 | #define IXGBE_CTRL_EXT 0x00018 |
| 79 | #define IXGBE_ESDP 0x00020 |
| 80 | #define IXGBE_EODSDP 0x00028 |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 81 | #define IXGBE_I2CCTL 0x00028 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 82 | #define IXGBE_LEDCTL 0x00200 |
| 83 | #define IXGBE_FRTIMER 0x00048 |
| 84 | #define IXGBE_TCPTIMER 0x0004C |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 85 | #define IXGBE_CORESPARE 0x00600 |
| 86 | #define IXGBE_EXVET 0x05078 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 87 | |
| 88 | /* NVM Registers */ |
| 89 | #define IXGBE_EEC 0x10010 |
| 90 | #define IXGBE_EERD 0x10014 |
Mallikarjuna R Chilakala | 21ce849 | 2010-05-13 17:33:41 +0000 | [diff] [blame] | 91 | #define IXGBE_EEWR 0x10018 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 92 | #define IXGBE_FLA 0x1001C |
| 93 | #define IXGBE_EEMNGCTL 0x10110 |
| 94 | #define IXGBE_EEMNGDATA 0x10114 |
| 95 | #define IXGBE_FLMNGCTL 0x10118 |
| 96 | #define IXGBE_FLMNGDATA 0x1011C |
| 97 | #define IXGBE_FLMNGCNT 0x10120 |
| 98 | #define IXGBE_FLOP 0x1013C |
| 99 | #define IXGBE_GRC 0x10200 |
| 100 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 101 | /* General Receive Control */ |
| 102 | #define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */ |
Emil Tantilov | 888be1a | 2011-02-08 09:48:32 +0000 | [diff] [blame] | 103 | #define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 104 | |
| 105 | #define IXGBE_VPDDIAG0 0x10204 |
| 106 | #define IXGBE_VPDDIAG1 0x10208 |
| 107 | |
| 108 | /* I2CCTL Bit Masks */ |
| 109 | #define IXGBE_I2C_CLK_IN 0x00000001 |
| 110 | #define IXGBE_I2C_CLK_OUT 0x00000002 |
| 111 | #define IXGBE_I2C_DATA_IN 0x00000004 |
| 112 | #define IXGBE_I2C_DATA_OUT 0x00000008 |
Don Skidmore | 8f56e4b | 2012-03-15 07:36:37 +0000 | [diff] [blame] | 113 | #define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT 500 |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 114 | |
Don Skidmore | e1ea915 | 2012-02-17 02:38:58 +0000 | [diff] [blame] | 115 | #define IXGBE_I2C_THERMAL_SENSOR_ADDR 0xF8 |
| 116 | #define IXGBE_EMC_INTERNAL_DATA 0x00 |
| 117 | #define IXGBE_EMC_INTERNAL_THERM_LIMIT 0x20 |
| 118 | #define IXGBE_EMC_DIODE1_DATA 0x01 |
| 119 | #define IXGBE_EMC_DIODE1_THERM_LIMIT 0x19 |
| 120 | #define IXGBE_EMC_DIODE2_DATA 0x23 |
| 121 | #define IXGBE_EMC_DIODE2_THERM_LIMIT 0x1A |
| 122 | |
| 123 | #define IXGBE_MAX_SENSORS 3 |
| 124 | |
| 125 | struct ixgbe_thermal_diode_data { |
| 126 | u8 location; |
| 127 | u8 temp; |
| 128 | u8 caution_thresh; |
| 129 | u8 max_op_thresh; |
| 130 | }; |
| 131 | |
| 132 | struct ixgbe_thermal_sensor_data { |
| 133 | struct ixgbe_thermal_diode_data sensor[IXGBE_MAX_SENSORS]; |
| 134 | }; |
| 135 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 136 | /* Interrupt Registers */ |
| 137 | #define IXGBE_EICR 0x00800 |
| 138 | #define IXGBE_EICS 0x00808 |
| 139 | #define IXGBE_EIMS 0x00880 |
| 140 | #define IXGBE_EIMC 0x00888 |
| 141 | #define IXGBE_EIAC 0x00810 |
| 142 | #define IXGBE_EIAM 0x00890 |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 143 | #define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4) |
| 144 | #define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4) |
| 145 | #define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4) |
| 146 | #define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4) |
Jesse Brandeburg | 509ee93 | 2009-03-13 22:13:28 +0000 | [diff] [blame] | 147 | /* |
| 148 | * 82598 EITR is 16 bits but set the limits based on the max |
| 149 | * supported by all ixgbe hardware. 82599 EITR is only 12 bits, |
| 150 | * with the lower 3 always zero. |
| 151 | */ |
| 152 | #define IXGBE_MAX_INT_RATE 488281 |
| 153 | #define IXGBE_MIN_INT_RATE 956 |
| 154 | #define IXGBE_MAX_EITR 0x00000FF8 |
| 155 | #define IXGBE_MIN_EITR 8 |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 156 | #define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \ |
| 157 | (0x012300 + (((_i) - 24) * 4))) |
Jesse Brandeburg | 509ee93 | 2009-03-13 22:13:28 +0000 | [diff] [blame] | 158 | #define IXGBE_EITR_ITR_INT_MASK 0x00000FF8 |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 159 | #define IXGBE_EITR_LLI_MOD 0x00008000 |
| 160 | #define IXGBE_EITR_CNT_WDIS 0x80000000 |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 161 | #define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 162 | #define IXGBE_IVAR_MISC 0x00A00 /* misc MSI-X interrupt causes */ |
| 163 | #define IXGBE_EITRSEL 0x00894 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 164 | #define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */ |
| 165 | #define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 166 | #define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4))) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 167 | #define IXGBE_GPIE 0x00898 |
| 168 | |
| 169 | /* Flow Control Registers */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 170 | #define IXGBE_FCADBUL 0x03210 |
| 171 | #define IXGBE_FCADBUH 0x03214 |
| 172 | #define IXGBE_FCAMACL 0x04328 |
| 173 | #define IXGBE_FCAMACH 0x0432C |
| 174 | #define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */ |
| 175 | #define IXGBE_FCRTL_82599(_i) (0x03220 + ((_i) * 4)) /* 8 of these (0-7) */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 176 | #define IXGBE_PFCTOP 0x03008 |
| 177 | #define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */ |
| 178 | #define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */ |
| 179 | #define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */ |
| 180 | #define IXGBE_FCRTV 0x032A0 |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 181 | #define IXGBE_FCCFG 0x03D00 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 182 | #define IXGBE_TFCS 0x0CE00 |
| 183 | |
| 184 | /* Receive DMA Registers */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 185 | #define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \ |
Alexander Duyck | 795be95 | 2012-01-18 22:13:30 +0000 | [diff] [blame] | 186 | (0x0D000 + (((_i) - 64) * 0x40))) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 187 | #define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \ |
Alexander Duyck | 795be95 | 2012-01-18 22:13:30 +0000 | [diff] [blame] | 188 | (0x0D004 + (((_i) - 64) * 0x40))) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 189 | #define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \ |
Alexander Duyck | 795be95 | 2012-01-18 22:13:30 +0000 | [diff] [blame] | 190 | (0x0D008 + (((_i) - 64) * 0x40))) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 191 | #define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \ |
Alexander Duyck | 795be95 | 2012-01-18 22:13:30 +0000 | [diff] [blame] | 192 | (0x0D010 + (((_i) - 64) * 0x40))) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 193 | #define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \ |
Alexander Duyck | 795be95 | 2012-01-18 22:13:30 +0000 | [diff] [blame] | 194 | (0x0D018 + (((_i) - 64) * 0x40))) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 195 | #define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \ |
Alexander Duyck | 795be95 | 2012-01-18 22:13:30 +0000 | [diff] [blame] | 196 | (0x0D028 + (((_i) - 64) * 0x40))) |
Emil Tantilov | 83dfde4 | 2011-03-31 09:36:24 +0000 | [diff] [blame] | 197 | #define IXGBE_RSCCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \ |
Alexander Duyck | 795be95 | 2012-01-18 22:13:30 +0000 | [diff] [blame] | 198 | (0x0D02C + (((_i) - 64) * 0x40))) |
Emil Tantilov | 83dfde4 | 2011-03-31 09:36:24 +0000 | [diff] [blame] | 199 | #define IXGBE_RSCDBU 0x03028 |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 200 | #define IXGBE_RDDCC 0x02F20 |
| 201 | #define IXGBE_RXMEMWRAP 0x03190 |
| 202 | #define IXGBE_STARCTRL 0x03024 |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 203 | /* |
| 204 | * Split and Replication Receive Control Registers |
| 205 | * 00-15 : 0x02100 + n*4 |
| 206 | * 16-64 : 0x01014 + n*0x40 |
| 207 | * 64-127: 0x0D014 + (n-64)*0x40 |
| 208 | */ |
| 209 | #define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \ |
| 210 | (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \ |
Alexander Duyck | 795be95 | 2012-01-18 22:13:30 +0000 | [diff] [blame] | 211 | (0x0D014 + (((_i) - 64) * 0x40)))) |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 212 | /* |
| 213 | * Rx DCA Control Register: |
| 214 | * 00-15 : 0x02200 + n*4 |
| 215 | * 16-64 : 0x0100C + n*0x40 |
| 216 | * 64-127: 0x0D00C + (n-64)*0x40 |
| 217 | */ |
| 218 | #define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \ |
| 219 | (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \ |
Alexander Duyck | 795be95 | 2012-01-18 22:13:30 +0000 | [diff] [blame] | 220 | (0x0D00C + (((_i) - 64) * 0x40)))) |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 221 | #define IXGBE_RDRXCTL 0x02F00 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 222 | #define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4)) |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 223 | /* 8 of these 0x03C00 - 0x03C1C */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 224 | #define IXGBE_RXCTRL 0x03000 |
| 225 | #define IXGBE_DROPEN 0x03D04 |
| 226 | #define IXGBE_RXPBSIZE_SHIFT 10 |
| 227 | |
| 228 | /* Receive Registers */ |
| 229 | #define IXGBE_RXCSUM 0x05000 |
| 230 | #define IXGBE_RFCTL 0x05008 |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 231 | #define IXGBE_DRECCCTL 0x02F08 |
| 232 | #define IXGBE_DRECCCTL_DISABLE 0 |
| 233 | /* Multicast Table Array - 128 entries */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 234 | #define IXGBE_MTA(_i) (0x05200 + ((_i) * 4)) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 235 | #define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ |
| 236 | (0x0A200 + ((_i) * 8))) |
| 237 | #define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ |
| 238 | (0x0A204 + ((_i) * 8))) |
| 239 | #define IXGBE_MPSAR_LO(_i) (0x0A600 + ((_i) * 8)) |
| 240 | #define IXGBE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8)) |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 241 | /* Packet split receive type */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 242 | #define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \ |
| 243 | (0x0EA00 + ((_i) * 4))) |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 244 | /* array of 4096 1-bit vlan filters */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 245 | #define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4)) |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 246 | /*array of 4096 4-bit vlan vmdq indices */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 247 | #define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4)) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 248 | #define IXGBE_FCTRL 0x05080 |
| 249 | #define IXGBE_VLNCTRL 0x05088 |
| 250 | #define IXGBE_MCSTCTRL 0x05090 |
| 251 | #define IXGBE_MRQC 0x05818 |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 252 | #define IXGBE_SAQF(_i) (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */ |
| 253 | #define IXGBE_DAQF(_i) (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */ |
| 254 | #define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */ |
| 255 | #define IXGBE_FTQF(_i) (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */ |
| 256 | #define IXGBE_ETQF(_i) (0x05128 + ((_i) * 4)) /* EType Queue Filter */ |
| 257 | #define IXGBE_ETQS(_i) (0x0EC00 + ((_i) * 4)) /* EType Queue Select */ |
| 258 | #define IXGBE_SYNQF 0x0EC30 /* SYN Packet Queue Filter */ |
| 259 | #define IXGBE_RQTC 0x0EC70 |
| 260 | #define IXGBE_MTQC 0x08120 |
| 261 | #define IXGBE_VLVF(_i) (0x0F100 + ((_i) * 4)) /* 64 of these (0-63) */ |
| 262 | #define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4)) /* 128 of these (0-127) */ |
Greg Rose | 7f01648 | 2010-05-04 22:12:06 +0000 | [diff] [blame] | 263 | #define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4)) /* 64 of these (0-63) */ |
Emil Tantilov | 83dfde4 | 2011-03-31 09:36:24 +0000 | [diff] [blame] | 264 | #define IXGBE_VT_CTL 0x051B0 |
| 265 | #define IXGBE_PFMAILBOX(_i) (0x04B00 + (4 * (_i))) /* 64 total */ |
| 266 | #define IXGBE_PFMBMEM(_i) (0x13000 + (64 * (_i))) /* 64 Mailboxes, 16 DW each */ |
| 267 | #define IXGBE_PFMBICR(_i) (0x00710 + (4 * (_i))) /* 4 total */ |
| 268 | #define IXGBE_PFMBIMR(_i) (0x00720 + (4 * (_i))) /* 4 total */ |
| 269 | #define IXGBE_VFRE(_i) (0x051E0 + ((_i) * 4)) |
| 270 | #define IXGBE_VFTE(_i) (0x08110 + ((_i) * 4)) |
| 271 | #define IXGBE_VMECM(_i) (0x08790 + ((_i) * 4)) |
| 272 | #define IXGBE_QDE 0x2F04 |
| 273 | #define IXGBE_VMTXSW(_i) (0x05180 + ((_i) * 4)) /* 2 total */ |
| 274 | #define IXGBE_VMOLR(_i) (0x0F000 + ((_i) * 4)) /* 64 total */ |
| 275 | #define IXGBE_UTA(_i) (0x0F400 + ((_i) * 4)) |
| 276 | #define IXGBE_MRCTL(_i) (0x0F600 + ((_i) * 4)) |
| 277 | #define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4)) |
| 278 | #define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4)) |
| 279 | #define IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/ |
| 280 | #define IXGBE_RXFECCERR0 0x051B8 |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 281 | #define IXGBE_LLITHRESH 0x0EC90 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 282 | #define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */ |
| 283 | #define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */ |
| 284 | #define IXGBE_IMIRVP 0x05AC0 |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 285 | #define IXGBE_VMD_CTL 0x0581C |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 286 | #define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */ |
| 287 | #define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */ |
| 288 | |
Peter P Waskiewicz Jr | bfde493 | 2009-06-04 16:01:06 +0000 | [diff] [blame] | 289 | /* Flow Director registers */ |
| 290 | #define IXGBE_FDIRCTRL 0x0EE00 |
| 291 | #define IXGBE_FDIRHKEY 0x0EE68 |
| 292 | #define IXGBE_FDIRSKEY 0x0EE6C |
| 293 | #define IXGBE_FDIRDIP4M 0x0EE3C |
| 294 | #define IXGBE_FDIRSIP4M 0x0EE40 |
| 295 | #define IXGBE_FDIRTCPM 0x0EE44 |
| 296 | #define IXGBE_FDIRUDPM 0x0EE48 |
| 297 | #define IXGBE_FDIRIP6M 0x0EE74 |
| 298 | #define IXGBE_FDIRM 0x0EE70 |
| 299 | |
| 300 | /* Flow Director Stats registers */ |
| 301 | #define IXGBE_FDIRFREE 0x0EE38 |
| 302 | #define IXGBE_FDIRLEN 0x0EE4C |
| 303 | #define IXGBE_FDIRUSTAT 0x0EE50 |
| 304 | #define IXGBE_FDIRFSTAT 0x0EE54 |
| 305 | #define IXGBE_FDIRMATCH 0x0EE58 |
| 306 | #define IXGBE_FDIRMISS 0x0EE5C |
| 307 | |
| 308 | /* Flow Director Programming registers */ |
| 309 | #define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4)) /* 3 of these (0-2) */ |
| 310 | #define IXGBE_FDIRIPSA 0x0EE18 |
| 311 | #define IXGBE_FDIRIPDA 0x0EE1C |
| 312 | #define IXGBE_FDIRPORT 0x0EE20 |
| 313 | #define IXGBE_FDIRVLAN 0x0EE24 |
| 314 | #define IXGBE_FDIRHASH 0x0EE28 |
| 315 | #define IXGBE_FDIRCMD 0x0EE2C |
| 316 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 317 | /* Transmit DMA registers */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 318 | #define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of these (0-31)*/ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 319 | #define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40)) |
| 320 | #define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40)) |
| 321 | #define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40)) |
| 322 | #define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40)) |
| 323 | #define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40)) |
| 324 | #define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40)) |
| 325 | #define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40)) |
| 326 | #define IXGBE_DTXCTL 0x07E00 |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 327 | |
Greg Rose | a985b6c3 | 2010-11-18 03:02:52 +0000 | [diff] [blame] | 328 | #define IXGBE_DMATXCTL 0x04A80 |
| 329 | #define IXGBE_PFVFSPOOF(_i) (0x08200 + ((_i) * 4)) /* 8 of these 0 - 7 */ |
Greg Rose | 7f87047 | 2010-01-09 02:25:29 +0000 | [diff] [blame] | 330 | #define IXGBE_PFDTXGSWC 0x08220 |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 331 | #define IXGBE_DTXMXSZRQ 0x08100 |
| 332 | #define IXGBE_DTXTCPFLGL 0x04A88 |
| 333 | #define IXGBE_DTXTCPFLGH 0x04A8C |
| 334 | #define IXGBE_LBDRPEN 0x0CA00 |
| 335 | #define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */ |
| 336 | |
| 337 | #define IXGBE_DMATXCTL_TE 0x1 /* Transmit Enable */ |
| 338 | #define IXGBE_DMATXCTL_NS 0x2 /* No Snoop LSO hdr buffer */ |
| 339 | #define IXGBE_DMATXCTL_GDV 0x8 /* Global Double VLAN */ |
| 340 | #define IXGBE_DMATXCTL_VT_SHIFT 16 /* VLAN EtherType */ |
Greg Rose | 7f87047 | 2010-01-09 02:25:29 +0000 | [diff] [blame] | 341 | |
| 342 | #define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */ |
Greg Rose | a985b6c3 | 2010-11-18 03:02:52 +0000 | [diff] [blame] | 343 | |
| 344 | /* Anti-spoofing defines */ |
| 345 | #define IXGBE_SPOOF_MACAS_MASK 0xFF |
| 346 | #define IXGBE_SPOOF_VLANAS_MASK 0xFF00 |
| 347 | #define IXGBE_SPOOF_VLANAS_SHIFT 8 |
| 348 | #define IXGBE_PFVFSPOOF_REG_COUNT 8 |
| 349 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 350 | #define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 351 | /* Tx DCA Control register : 128 of these (0-127) */ |
| 352 | #define IXGBE_DCA_TXCTRL_82599(_i) (0x0600C + ((_i) * 0x40)) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 353 | #define IXGBE_TIPG 0x0CB00 |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 354 | #define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) /* 8 of these */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 355 | #define IXGBE_MNGTXMAP 0x0CD10 |
| 356 | #define IXGBE_TIPG_FIBER_DEFAULT 3 |
| 357 | #define IXGBE_TXPBSIZE_SHIFT 10 |
| 358 | |
| 359 | /* Wake up registers */ |
| 360 | #define IXGBE_WUC 0x05800 |
| 361 | #define IXGBE_WUFC 0x05808 |
| 362 | #define IXGBE_WUS 0x05810 |
| 363 | #define IXGBE_IPAV 0x05838 |
| 364 | #define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */ |
| 365 | #define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 366 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 367 | #define IXGBE_WUPL 0x05900 |
| 368 | #define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */ |
Alexander Duyck | 795be95 | 2012-01-18 22:13:30 +0000 | [diff] [blame] | 369 | #define IXGBE_FHFT(_n) (0x09000 + ((_n) * 0x100)) /* Flex host filter table */ |
| 370 | #define IXGBE_FHFT_EXT(_n) (0x09800 + ((_n) * 0x100)) /* Ext Flexible Host |
| 371 | * Filter Table */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 372 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 373 | #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4 |
| 374 | #define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2 |
| 375 | |
| 376 | /* Each Flexible Filter is at most 128 (0x80) bytes in length */ |
| 377 | #define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128 |
| 378 | #define IXGBE_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */ |
| 379 | #define IXGBE_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */ |
| 380 | |
| 381 | /* Definitions for power management and wakeup registers */ |
| 382 | /* Wake Up Control */ |
| 383 | #define IXGBE_WUC_PME_EN 0x00000002 /* PME Enable */ |
| 384 | #define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */ |
Emil Tantilov | 888be1a | 2011-02-08 09:48:32 +0000 | [diff] [blame] | 385 | #define IXGBE_WUC_WKEN 0x00000010 /* Enable PE_WAKE_N pin assertion */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 386 | |
| 387 | /* Wake Up Filter Control */ |
| 388 | #define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ |
| 389 | #define IXGBE_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ |
| 390 | #define IXGBE_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ |
| 391 | #define IXGBE_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ |
| 392 | #define IXGBE_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ |
| 393 | #define IXGBE_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ |
| 394 | #define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ |
| 395 | #define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ |
| 396 | #define IXGBE_WUFC_MNG 0x00000100 /* Directed Mgmt Packet Wakeup Enable */ |
| 397 | |
| 398 | #define IXGBE_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */ |
| 399 | #define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ |
| 400 | #define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ |
| 401 | #define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ |
| 402 | #define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ |
| 403 | #define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */ |
| 404 | #define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */ |
| 405 | #define IXGBE_WUFC_FLX_FILTERS 0x000F0000 /* Mask for 4 flex filters */ |
| 406 | #define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000 /* Mask for Ext. flex filters */ |
Emil Tantilov | 83dfde4 | 2011-03-31 09:36:24 +0000 | [diff] [blame] | 407 | #define IXGBE_WUFC_ALL_FILTERS 0x003F00FF /* Mask for all wakeup filters */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 408 | #define IXGBE_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */ |
| 409 | |
| 410 | /* Wake Up Status */ |
| 411 | #define IXGBE_WUS_LNKC IXGBE_WUFC_LNKC |
| 412 | #define IXGBE_WUS_MAG IXGBE_WUFC_MAG |
| 413 | #define IXGBE_WUS_EX IXGBE_WUFC_EX |
| 414 | #define IXGBE_WUS_MC IXGBE_WUFC_MC |
| 415 | #define IXGBE_WUS_BC IXGBE_WUFC_BC |
| 416 | #define IXGBE_WUS_ARP IXGBE_WUFC_ARP |
| 417 | #define IXGBE_WUS_IPV4 IXGBE_WUFC_IPV4 |
| 418 | #define IXGBE_WUS_IPV6 IXGBE_WUFC_IPV6 |
| 419 | #define IXGBE_WUS_MNG IXGBE_WUFC_MNG |
| 420 | #define IXGBE_WUS_FLX0 IXGBE_WUFC_FLX0 |
| 421 | #define IXGBE_WUS_FLX1 IXGBE_WUFC_FLX1 |
| 422 | #define IXGBE_WUS_FLX2 IXGBE_WUFC_FLX2 |
| 423 | #define IXGBE_WUS_FLX3 IXGBE_WUFC_FLX3 |
| 424 | #define IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4 |
| 425 | #define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5 |
| 426 | #define IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS |
| 427 | |
| 428 | /* Wake Up Packet Length */ |
| 429 | #define IXGBE_WUPL_LENGTH_MASK 0xFFFF |
| 430 | |
| 431 | /* DCB registers */ |
John Fastabend | 9da712d | 2011-08-23 03:14:22 +0000 | [diff] [blame] | 432 | #define MAX_TRAFFIC_CLASS 8 |
John Fastabend | 4de2a02 | 2011-09-27 03:52:01 +0000 | [diff] [blame] | 433 | #define X540_TRAFFIC_CLASS 4 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 434 | #define IXGBE_RMCS 0x03D00 |
| 435 | #define IXGBE_DPMCS 0x07F40 |
| 436 | #define IXGBE_PDPMCS 0x0CD00 |
| 437 | #define IXGBE_RUPPBMR 0x050A0 |
| 438 | #define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */ |
| 439 | #define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */ |
| 440 | #define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */ |
| 441 | #define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */ |
| 442 | #define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */ |
| 443 | #define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */ |
| 444 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 445 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 446 | /* Security Control Registers */ |
| 447 | #define IXGBE_SECTXCTRL 0x08800 |
| 448 | #define IXGBE_SECTXSTAT 0x08804 |
| 449 | #define IXGBE_SECTXBUFFAF 0x08808 |
| 450 | #define IXGBE_SECTXMINIFG 0x08810 |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 451 | #define IXGBE_SECRXCTRL 0x08D00 |
| 452 | #define IXGBE_SECRXSTAT 0x08D04 |
| 453 | |
| 454 | /* Security Bit Fields and Masks */ |
| 455 | #define IXGBE_SECTXCTRL_SECTX_DIS 0x00000001 |
| 456 | #define IXGBE_SECTXCTRL_TX_DIS 0x00000002 |
| 457 | #define IXGBE_SECTXCTRL_STORE_FORWARD 0x00000004 |
| 458 | |
| 459 | #define IXGBE_SECTXSTAT_SECTX_RDY 0x00000001 |
| 460 | #define IXGBE_SECTXSTAT_ECC_TXERR 0x00000002 |
| 461 | |
| 462 | #define IXGBE_SECRXCTRL_SECRX_DIS 0x00000001 |
| 463 | #define IXGBE_SECRXCTRL_RX_DIS 0x00000002 |
| 464 | |
| 465 | #define IXGBE_SECRXSTAT_SECRX_RDY 0x00000001 |
| 466 | #define IXGBE_SECRXSTAT_ECC_RXERR 0x00000002 |
| 467 | |
| 468 | /* LinkSec (MacSec) Registers */ |
| 469 | #define IXGBE_LSECTXCAP 0x08A00 |
| 470 | #define IXGBE_LSECRXCAP 0x08F00 |
| 471 | #define IXGBE_LSECTXCTRL 0x08A04 |
| 472 | #define IXGBE_LSECTXSCL 0x08A08 /* SCI Low */ |
| 473 | #define IXGBE_LSECTXSCH 0x08A0C /* SCI High */ |
| 474 | #define IXGBE_LSECTXSA 0x08A10 |
| 475 | #define IXGBE_LSECTXPN0 0x08A14 |
| 476 | #define IXGBE_LSECTXPN1 0x08A18 |
| 477 | #define IXGBE_LSECTXKEY0(_n) (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */ |
| 478 | #define IXGBE_LSECTXKEY1(_n) (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */ |
| 479 | #define IXGBE_LSECRXCTRL 0x08F04 |
| 480 | #define IXGBE_LSECRXSCL 0x08F08 |
| 481 | #define IXGBE_LSECRXSCH 0x08F0C |
| 482 | #define IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */ |
| 483 | #define IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */ |
| 484 | #define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m)))) |
| 485 | #define IXGBE_LSECTXUT 0x08A3C /* OutPktsUntagged */ |
| 486 | #define IXGBE_LSECTXPKTE 0x08A40 /* OutPktsEncrypted */ |
| 487 | #define IXGBE_LSECTXPKTP 0x08A44 /* OutPktsProtected */ |
| 488 | #define IXGBE_LSECTXOCTE 0x08A48 /* OutOctetsEncrypted */ |
| 489 | #define IXGBE_LSECTXOCTP 0x08A4C /* OutOctetsProtected */ |
| 490 | #define IXGBE_LSECRXUT 0x08F40 /* InPktsUntagged/InPktsNoTag */ |
| 491 | #define IXGBE_LSECRXOCTD 0x08F44 /* InOctetsDecrypted */ |
| 492 | #define IXGBE_LSECRXOCTV 0x08F48 /* InOctetsValidated */ |
| 493 | #define IXGBE_LSECRXBAD 0x08F4C /* InPktsBadTag */ |
| 494 | #define IXGBE_LSECRXNOSCI 0x08F50 /* InPktsNoSci */ |
| 495 | #define IXGBE_LSECRXUNSCI 0x08F54 /* InPktsUnknownSci */ |
| 496 | #define IXGBE_LSECRXUNCH 0x08F58 /* InPktsUnchecked */ |
| 497 | #define IXGBE_LSECRXDELAY 0x08F5C /* InPktsDelayed */ |
| 498 | #define IXGBE_LSECRXLATE 0x08F60 /* InPktsLate */ |
| 499 | #define IXGBE_LSECRXOK(_n) (0x08F64 + (0x04 * (_n))) /* InPktsOk */ |
| 500 | #define IXGBE_LSECRXINV(_n) (0x08F6C + (0x04 * (_n))) /* InPktsInvalid */ |
| 501 | #define IXGBE_LSECRXNV(_n) (0x08F74 + (0x04 * (_n))) /* InPktsNotValid */ |
| 502 | #define IXGBE_LSECRXUNSA 0x08F7C /* InPktsUnusedSa */ |
| 503 | #define IXGBE_LSECRXNUSA 0x08F80 /* InPktsNotUsingSa */ |
| 504 | |
| 505 | /* LinkSec (MacSec) Bit Fields and Masks */ |
| 506 | #define IXGBE_LSECTXCAP_SUM_MASK 0x00FF0000 |
| 507 | #define IXGBE_LSECTXCAP_SUM_SHIFT 16 |
| 508 | #define IXGBE_LSECRXCAP_SUM_MASK 0x00FF0000 |
| 509 | #define IXGBE_LSECRXCAP_SUM_SHIFT 16 |
| 510 | |
| 511 | #define IXGBE_LSECTXCTRL_EN_MASK 0x00000003 |
| 512 | #define IXGBE_LSECTXCTRL_DISABLE 0x0 |
| 513 | #define IXGBE_LSECTXCTRL_AUTH 0x1 |
| 514 | #define IXGBE_LSECTXCTRL_AUTH_ENCRYPT 0x2 |
| 515 | #define IXGBE_LSECTXCTRL_AISCI 0x00000020 |
| 516 | #define IXGBE_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00 |
| 517 | #define IXGBE_LSECTXCTRL_RSV_MASK 0x000000D8 |
| 518 | |
| 519 | #define IXGBE_LSECRXCTRL_EN_MASK 0x0000000C |
| 520 | #define IXGBE_LSECRXCTRL_EN_SHIFT 2 |
| 521 | #define IXGBE_LSECRXCTRL_DISABLE 0x0 |
| 522 | #define IXGBE_LSECRXCTRL_CHECK 0x1 |
| 523 | #define IXGBE_LSECRXCTRL_STRICT 0x2 |
| 524 | #define IXGBE_LSECRXCTRL_DROP 0x3 |
| 525 | #define IXGBE_LSECRXCTRL_PLSH 0x00000040 |
| 526 | #define IXGBE_LSECRXCTRL_RP 0x00000080 |
| 527 | #define IXGBE_LSECRXCTRL_RSV_MASK 0xFFFFFF33 |
| 528 | |
| 529 | /* IpSec Registers */ |
| 530 | #define IXGBE_IPSTXIDX 0x08900 |
| 531 | #define IXGBE_IPSTXSALT 0x08904 |
| 532 | #define IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i))) /* 4 of these (0-3) */ |
| 533 | #define IXGBE_IPSRXIDX 0x08E00 |
| 534 | #define IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */ |
| 535 | #define IXGBE_IPSRXSPI 0x08E14 |
| 536 | #define IXGBE_IPSRXIPIDX 0x08E18 |
| 537 | #define IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */ |
| 538 | #define IXGBE_IPSRXSALT 0x08E2C |
| 539 | #define IXGBE_IPSRXMOD 0x08E30 |
| 540 | |
| 541 | #define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE 0x4 |
| 542 | |
| 543 | /* DCB registers */ |
| 544 | #define IXGBE_RTRPCS 0x02430 |
| 545 | #define IXGBE_RTTDCS 0x04900 |
Greg Rose | 7f87047 | 2010-01-09 02:25:29 +0000 | [diff] [blame] | 546 | #define IXGBE_RTTDCS_ARBDIS 0x00000040 /* DCB arbiter disable */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 547 | #define IXGBE_RTTPCS 0x0CD00 |
| 548 | #define IXGBE_RTRUP2TC 0x03020 |
| 549 | #define IXGBE_RTTUP2TC 0x0C800 |
| 550 | #define IXGBE_RTRPT4C(_i) (0x02140 + ((_i) * 4)) /* 8 of these (0-7) */ |
Emil Tantilov | 83dfde4 | 2011-03-31 09:36:24 +0000 | [diff] [blame] | 551 | #define IXGBE_TXLLQ(_i) (0x082E0 + ((_i) * 4)) /* 4 of these (0-3) */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 552 | #define IXGBE_RTRPT4S(_i) (0x02160 + ((_i) * 4)) /* 8 of these (0-7) */ |
| 553 | #define IXGBE_RTTDT2C(_i) (0x04910 + ((_i) * 4)) /* 8 of these (0-7) */ |
| 554 | #define IXGBE_RTTDT2S(_i) (0x04930 + ((_i) * 4)) /* 8 of these (0-7) */ |
| 555 | #define IXGBE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */ |
| 556 | #define IXGBE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */ |
| 557 | #define IXGBE_RTTDQSEL 0x04904 |
| 558 | #define IXGBE_RTTDT1C 0x04908 |
| 559 | #define IXGBE_RTTDT1S 0x0490C |
| 560 | #define IXGBE_RTTDTECC 0x04990 |
| 561 | #define IXGBE_RTTDTECC_NO_BCN 0x00000100 |
| 562 | #define IXGBE_RTTBCNRC 0x04984 |
Lior Levy | ff4ab20 | 2011-03-11 02:03:07 +0000 | [diff] [blame] | 563 | #define IXGBE_RTTBCNRC_RS_ENA 0x80000000 |
| 564 | #define IXGBE_RTTBCNRC_RF_DEC_MASK 0x00003FFF |
| 565 | #define IXGBE_RTTBCNRC_RF_INT_SHIFT 14 |
| 566 | #define IXGBE_RTTBCNRC_RF_INT_MASK \ |
| 567 | (IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT) |
Lior Levy | 7555e83 | 2011-06-25 00:09:08 -0700 | [diff] [blame] | 568 | #define IXGBE_RTTBCNRM 0x04980 |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 569 | |
Emil Tantilov | 83dfde4 | 2011-03-31 09:36:24 +0000 | [diff] [blame] | 570 | /* FCoE DMA Context Registers */ |
Yi Zou | bff6617 | 2009-05-13 13:09:39 +0000 | [diff] [blame] | 571 | #define IXGBE_FCPTRL 0x02410 /* FC User Desc. PTR Low */ |
| 572 | #define IXGBE_FCPTRH 0x02414 /* FC USer Desc. PTR High */ |
| 573 | #define IXGBE_FCBUFF 0x02418 /* FC Buffer Control */ |
| 574 | #define IXGBE_FCDMARW 0x02420 /* FC Receive DMA RW */ |
| 575 | #define IXGBE_FCINVST0 0x03FC0 /* FC Invalid DMA Context Status Reg 0 */ |
| 576 | #define IXGBE_FCINVST(_i) (IXGBE_FCINVST0 + ((_i) * 4)) |
| 577 | #define IXGBE_FCBUFF_VALID (1 << 0) /* DMA Context Valid */ |
| 578 | #define IXGBE_FCBUFF_BUFFSIZE (3 << 3) /* User Buffer Size */ |
| 579 | #define IXGBE_FCBUFF_WRCONTX (1 << 7) /* 0: Initiator, 1: Target */ |
| 580 | #define IXGBE_FCBUFF_BUFFCNT 0x0000ff00 /* Number of User Buffers */ |
| 581 | #define IXGBE_FCBUFF_OFFSET 0xffff0000 /* User Buffer Offset */ |
| 582 | #define IXGBE_FCBUFF_BUFFSIZE_SHIFT 3 |
| 583 | #define IXGBE_FCBUFF_BUFFCNT_SHIFT 8 |
| 584 | #define IXGBE_FCBUFF_OFFSET_SHIFT 16 |
| 585 | #define IXGBE_FCDMARW_WE (1 << 14) /* Write enable */ |
| 586 | #define IXGBE_FCDMARW_RE (1 << 15) /* Read enable */ |
| 587 | #define IXGBE_FCDMARW_FCOESEL 0x000001ff /* FC X_ID: 11 bits */ |
| 588 | #define IXGBE_FCDMARW_LASTSIZE 0xffff0000 /* Last User Buffer Size */ |
| 589 | #define IXGBE_FCDMARW_LASTSIZE_SHIFT 16 |
| 590 | |
| 591 | /* FCoE SOF/EOF */ |
| 592 | #define IXGBE_TEOFF 0x04A94 /* Tx FC EOF */ |
| 593 | #define IXGBE_TSOFF 0x04A98 /* Tx FC SOF */ |
| 594 | #define IXGBE_REOFF 0x05158 /* Rx FC EOF */ |
| 595 | #define IXGBE_RSOFF 0x051F8 /* Rx FC SOF */ |
| 596 | /* FCoE Filter Context Registers */ |
| 597 | #define IXGBE_FCFLT 0x05108 /* FC FLT Context */ |
| 598 | #define IXGBE_FCFLTRW 0x05110 /* FC Filter RW Control */ |
| 599 | #define IXGBE_FCPARAM 0x051d8 /* FC Offset Parameter */ |
| 600 | #define IXGBE_FCFLT_VALID (1 << 0) /* Filter Context Valid */ |
| 601 | #define IXGBE_FCFLT_FIRST (1 << 1) /* Filter First */ |
| 602 | #define IXGBE_FCFLT_SEQID 0x00ff0000 /* Sequence ID */ |
| 603 | #define IXGBE_FCFLT_SEQCNT 0xff000000 /* Sequence Count */ |
| 604 | #define IXGBE_FCFLTRW_RVALDT (1 << 13) /* Fast Re-Validation */ |
| 605 | #define IXGBE_FCFLTRW_WE (1 << 14) /* Write Enable */ |
| 606 | #define IXGBE_FCFLTRW_RE (1 << 15) /* Read Enable */ |
| 607 | /* FCoE Receive Control */ |
| 608 | #define IXGBE_FCRXCTRL 0x05100 /* FC Receive Control */ |
| 609 | #define IXGBE_FCRXCTRL_FCOELLI (1 << 0) /* Low latency interrupt */ |
| 610 | #define IXGBE_FCRXCTRL_SAVBAD (1 << 1) /* Save Bad Frames */ |
| 611 | #define IXGBE_FCRXCTRL_FRSTRDH (1 << 2) /* EN 1st Read Header */ |
| 612 | #define IXGBE_FCRXCTRL_LASTSEQH (1 << 3) /* EN Last Header in Seq */ |
| 613 | #define IXGBE_FCRXCTRL_ALLH (1 << 4) /* EN All Headers */ |
| 614 | #define IXGBE_FCRXCTRL_FRSTSEQH (1 << 5) /* EN 1st Seq. Header */ |
| 615 | #define IXGBE_FCRXCTRL_ICRC (1 << 6) /* Ignore Bad FC CRC */ |
| 616 | #define IXGBE_FCRXCTRL_FCCRCBO (1 << 7) /* FC CRC Byte Ordering */ |
| 617 | #define IXGBE_FCRXCTRL_FCOEVER 0x00000f00 /* FCoE Version: 4 bits */ |
| 618 | #define IXGBE_FCRXCTRL_FCOEVER_SHIFT 8 |
| 619 | /* FCoE Redirection */ |
| 620 | #define IXGBE_FCRECTL 0x0ED00 /* FC Redirection Control */ |
| 621 | #define IXGBE_FCRETA0 0x0ED10 /* FC Redirection Table 0 */ |
| 622 | #define IXGBE_FCRETA(_i) (IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */ |
| 623 | #define IXGBE_FCRECTL_ENA 0x1 /* FCoE Redir Table Enable */ |
| 624 | #define IXGBE_FCRETA_SIZE 8 /* Max entries in FCRETA */ |
| 625 | #define IXGBE_FCRETA_ENTRY_MASK 0x0000007f /* 7 bits for the queue index */ |
| 626 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 627 | /* Stats registers */ |
| 628 | #define IXGBE_CRCERRS 0x04000 |
| 629 | #define IXGBE_ILLERRC 0x04004 |
| 630 | #define IXGBE_ERRBC 0x04008 |
| 631 | #define IXGBE_MSPDC 0x04010 |
| 632 | #define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/ |
| 633 | #define IXGBE_MLFC 0x04034 |
| 634 | #define IXGBE_MRFC 0x04038 |
| 635 | #define IXGBE_RLEC 0x04040 |
| 636 | #define IXGBE_LXONTXC 0x03F60 |
| 637 | #define IXGBE_LXONRXC 0x0CF60 |
| 638 | #define IXGBE_LXOFFTXC 0x03F68 |
| 639 | #define IXGBE_LXOFFRXC 0x0CF68 |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 640 | #define IXGBE_LXONRXCNT 0x041A4 |
| 641 | #define IXGBE_LXOFFRXCNT 0x041A8 |
| 642 | #define IXGBE_PXONRXCNT(_i) (0x04140 + ((_i) * 4)) /* 8 of these */ |
| 643 | #define IXGBE_PXOFFRXCNT(_i) (0x04160 + ((_i) * 4)) /* 8 of these */ |
| 644 | #define IXGBE_PXON2OFFCNT(_i) (0x03240 + ((_i) * 4)) /* 8 of these */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 645 | #define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/ |
| 646 | #define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/ |
| 647 | #define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/ |
| 648 | #define IXGBE_PXOFFRXC(_i) (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/ |
| 649 | #define IXGBE_PRC64 0x0405C |
| 650 | #define IXGBE_PRC127 0x04060 |
| 651 | #define IXGBE_PRC255 0x04064 |
| 652 | #define IXGBE_PRC511 0x04068 |
| 653 | #define IXGBE_PRC1023 0x0406C |
| 654 | #define IXGBE_PRC1522 0x04070 |
| 655 | #define IXGBE_GPRC 0x04074 |
| 656 | #define IXGBE_BPRC 0x04078 |
| 657 | #define IXGBE_MPRC 0x0407C |
| 658 | #define IXGBE_GPTC 0x04080 |
| 659 | #define IXGBE_GORCL 0x04088 |
| 660 | #define IXGBE_GORCH 0x0408C |
| 661 | #define IXGBE_GOTCL 0x04090 |
| 662 | #define IXGBE_GOTCH 0x04094 |
| 663 | #define IXGBE_RNBC(_i) (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/ |
| 664 | #define IXGBE_RUC 0x040A4 |
| 665 | #define IXGBE_RFC 0x040A8 |
| 666 | #define IXGBE_ROC 0x040AC |
| 667 | #define IXGBE_RJC 0x040B0 |
| 668 | #define IXGBE_MNGPRC 0x040B4 |
| 669 | #define IXGBE_MNGPDC 0x040B8 |
| 670 | #define IXGBE_MNGPTC 0x0CF90 |
| 671 | #define IXGBE_TORL 0x040C0 |
| 672 | #define IXGBE_TORH 0x040C4 |
| 673 | #define IXGBE_TPR 0x040D0 |
| 674 | #define IXGBE_TPT 0x040D4 |
| 675 | #define IXGBE_PTC64 0x040D8 |
| 676 | #define IXGBE_PTC127 0x040DC |
| 677 | #define IXGBE_PTC255 0x040E0 |
| 678 | #define IXGBE_PTC511 0x040E4 |
| 679 | #define IXGBE_PTC1023 0x040E8 |
| 680 | #define IXGBE_PTC1522 0x040EC |
| 681 | #define IXGBE_MPTC 0x040F0 |
| 682 | #define IXGBE_BPTC 0x040F4 |
| 683 | #define IXGBE_XEC 0x04120 |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 684 | #define IXGBE_SSVPC 0x08780 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 685 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 686 | #define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4)) |
| 687 | #define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \ |
| 688 | (0x08600 + ((_i) * 4))) |
| 689 | #define IXGBE_TQSM(_i) (0x08600 + ((_i) * 4)) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 690 | |
| 691 | #define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */ |
| 692 | #define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */ |
| 693 | #define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */ |
| 694 | #define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */ |
Emil Tantilov | 667c756 | 2011-02-26 06:40:05 +0000 | [diff] [blame] | 695 | #define IXGBE_QBRC_L(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */ |
| 696 | #define IXGBE_QBRC_H(_i) (0x01038 + ((_i) * 0x40)) /* 16 of these */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 697 | #define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40)) /* 16 of these */ |
| 698 | #define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8)) /* 16 of these */ |
| 699 | #define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8)) /* 16 of these */ |
Yi Zou | bff6617 | 2009-05-13 13:09:39 +0000 | [diff] [blame] | 700 | #define IXGBE_FCCRC 0x05118 /* Count of Good Eth CRC w/ Bad FC CRC */ |
| 701 | #define IXGBE_FCOERPDC 0x0241C /* FCoE Rx Packets Dropped Count */ |
| 702 | #define IXGBE_FCLAST 0x02424 /* FCoE Last Error Count */ |
| 703 | #define IXGBE_FCOEPRC 0x02428 /* Number of FCoE Packets Received */ |
| 704 | #define IXGBE_FCOEDWRC 0x0242C /* Number of FCoE DWords Received */ |
| 705 | #define IXGBE_FCOEPTC 0x08784 /* Number of FCoE Packets Transmitted */ |
| 706 | #define IXGBE_FCOEDWTC 0x08788 /* Number of FCoE DWords Transmitted */ |
Emil Tantilov | 58f6bcf | 2011-04-21 08:43:43 +0000 | [diff] [blame] | 707 | #define IXGBE_O2BGPTC 0x041C4 |
| 708 | #define IXGBE_O2BSPC 0x087B0 |
| 709 | #define IXGBE_B2OSPC 0x041C0 |
| 710 | #define IXGBE_B2OGPRC 0x02F90 |
Emil Tantilov | a3aeea0 | 2011-02-26 06:40:11 +0000 | [diff] [blame] | 711 | #define IXGBE_PCRC8ECL 0x0E810 |
| 712 | #define IXGBE_PCRC8ECH 0x0E811 |
| 713 | #define IXGBE_PCRC8ECH_MASK 0x1F |
| 714 | #define IXGBE_LDPCECL 0x0E820 |
| 715 | #define IXGBE_LDPCECH 0x0E821 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 716 | |
| 717 | /* Management */ |
| 718 | #define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */ |
| 719 | #define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */ |
| 720 | #define IXGBE_MANC 0x05820 |
| 721 | #define IXGBE_MFVAL 0x05824 |
| 722 | #define IXGBE_MANC2H 0x05860 |
| 723 | #define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */ |
| 724 | #define IXGBE_MIPAF 0x058B0 |
| 725 | #define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */ |
| 726 | #define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */ |
| 727 | #define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 728 | #define IXGBE_METF(_i) (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */ |
| 729 | #define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */ |
| 730 | #define IXGBE_LSWFW 0x15014 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 731 | |
| 732 | /* ARC Subsystem registers */ |
| 733 | #define IXGBE_HICR 0x15F00 |
| 734 | #define IXGBE_FWSTS 0x15F0C |
| 735 | #define IXGBE_HSMC0R 0x15F04 |
| 736 | #define IXGBE_HSMC1R 0x15F08 |
| 737 | #define IXGBE_SWSR 0x15F10 |
| 738 | #define IXGBE_HFDR 0x15FE8 |
| 739 | #define IXGBE_FLEX_MNG 0x15800 /* 0x15800 - 0x15EFC */ |
| 740 | |
Emil Tantilov | 9612de9 | 2011-05-07 07:40:20 +0000 | [diff] [blame] | 741 | #define IXGBE_HICR_EN 0x01 /* Enable bit - RO */ |
| 742 | /* Driver sets this bit when done to put command in RAM */ |
| 743 | #define IXGBE_HICR_C 0x02 |
| 744 | #define IXGBE_HICR_SV 0x04 /* Status Validity */ |
| 745 | #define IXGBE_HICR_FW_RESET_ENABLE 0x40 |
| 746 | #define IXGBE_HICR_FW_RESET 0x80 |
| 747 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 748 | /* PCI-E registers */ |
| 749 | #define IXGBE_GCR 0x11000 |
| 750 | #define IXGBE_GTV 0x11004 |
| 751 | #define IXGBE_FUNCTAG 0x11008 |
| 752 | #define IXGBE_GLT 0x1100C |
| 753 | #define IXGBE_GSCL_1 0x11010 |
| 754 | #define IXGBE_GSCL_2 0x11014 |
| 755 | #define IXGBE_GSCL_3 0x11018 |
| 756 | #define IXGBE_GSCL_4 0x1101C |
| 757 | #define IXGBE_GSCN_0 0x11020 |
| 758 | #define IXGBE_GSCN_1 0x11024 |
| 759 | #define IXGBE_GSCN_2 0x11028 |
| 760 | #define IXGBE_GSCN_3 0x1102C |
| 761 | #define IXGBE_FACTPS 0x10150 |
| 762 | #define IXGBE_PCIEANACTL 0x11040 |
| 763 | #define IXGBE_SWSM 0x10140 |
| 764 | #define IXGBE_FWSM 0x10148 |
| 765 | #define IXGBE_GSSR 0x10160 |
| 766 | #define IXGBE_MREVID 0x11064 |
| 767 | #define IXGBE_DCA_ID 0x11070 |
| 768 | #define IXGBE_DCA_CTRL 0x11074 |
Mallikarjuna R Chilakala | 21ce849 | 2010-05-13 17:33:41 +0000 | [diff] [blame] | 769 | #define IXGBE_SWFW_SYNC IXGBE_GSSR |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 770 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 771 | /* PCIe registers 82599-specific */ |
| 772 | #define IXGBE_GCR_EXT 0x11050 |
| 773 | #define IXGBE_GSCL_5_82599 0x11030 |
| 774 | #define IXGBE_GSCL_6_82599 0x11034 |
| 775 | #define IXGBE_GSCL_7_82599 0x11038 |
| 776 | #define IXGBE_GSCL_8_82599 0x1103C |
| 777 | #define IXGBE_PHYADR_82599 0x11040 |
| 778 | #define IXGBE_PHYDAT_82599 0x11044 |
| 779 | #define IXGBE_PHYCTL_82599 0x11048 |
| 780 | #define IXGBE_PBACLR_82599 0x11068 |
| 781 | #define IXGBE_CIAA_82599 0x11088 |
| 782 | #define IXGBE_CIAD_82599 0x1108C |
Emil Tantilov | 83dfde4 | 2011-03-31 09:36:24 +0000 | [diff] [blame] | 783 | #define IXGBE_PICAUSE 0x110B0 |
| 784 | #define IXGBE_PIENA 0x110B8 |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 785 | #define IXGBE_CDQ_MBR_82599 0x110B4 |
Emil Tantilov | 83dfde4 | 2011-03-31 09:36:24 +0000 | [diff] [blame] | 786 | #define IXGBE_PCIESPARE 0x110BC |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 787 | #define IXGBE_MISC_REG_82599 0x110F0 |
| 788 | #define IXGBE_ECC_CTRL_0_82599 0x11100 |
| 789 | #define IXGBE_ECC_CTRL_1_82599 0x11104 |
| 790 | #define IXGBE_ECC_STATUS_82599 0x110E0 |
| 791 | #define IXGBE_BAR_CTRL_82599 0x110F4 |
| 792 | |
Mallikarjuna R Chilakala | 202ff1e | 2009-08-03 07:20:38 +0000 | [diff] [blame] | 793 | /* PCI Express Control */ |
| 794 | #define IXGBE_GCR_CMPL_TMOUT_MASK 0x0000F000 |
| 795 | #define IXGBE_GCR_CMPL_TMOUT_10ms 0x00001000 |
| 796 | #define IXGBE_GCR_CMPL_TMOUT_RESEND 0x00010000 |
| 797 | #define IXGBE_GCR_CAP_VER2 0x00040000 |
| 798 | |
Greg Rose | 7f87047 | 2010-01-09 02:25:29 +0000 | [diff] [blame] | 799 | #define IXGBE_GCR_EXT_MSIX_EN 0x80000000 |
Emil Tantilov | ff9d1a5 | 2011-08-16 04:35:11 +0000 | [diff] [blame] | 800 | #define IXGBE_GCR_EXT_BUFFERS_CLEAR 0x40000000 |
Greg Rose | 7f87047 | 2010-01-09 02:25:29 +0000 | [diff] [blame] | 801 | #define IXGBE_GCR_EXT_VT_MODE_16 0x00000001 |
| 802 | #define IXGBE_GCR_EXT_VT_MODE_32 0x00000002 |
| 803 | #define IXGBE_GCR_EXT_VT_MODE_64 0x00000003 |
| 804 | #define IXGBE_GCR_EXT_SRIOV (IXGBE_GCR_EXT_MSIX_EN | \ |
| 805 | IXGBE_GCR_EXT_VT_MODE_64) |
| 806 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 807 | /* Time Sync Registers */ |
| 808 | #define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */ |
| 809 | #define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */ |
| 810 | #define IXGBE_RXSTMPL 0x051E8 /* Rx timestamp Low - RO */ |
| 811 | #define IXGBE_RXSTMPH 0x051A4 /* Rx timestamp High - RO */ |
| 812 | #define IXGBE_RXSATRL 0x051A0 /* Rx timestamp attribute low - RO */ |
| 813 | #define IXGBE_RXSATRH 0x051A8 /* Rx timestamp attribute high - RO */ |
| 814 | #define IXGBE_RXMTRL 0x05120 /* RX message type register low - RW */ |
| 815 | #define IXGBE_TXSTMPL 0x08C04 /* Tx timestamp value Low - RO */ |
| 816 | #define IXGBE_TXSTMPH 0x08C08 /* Tx timestamp value High - RO */ |
| 817 | #define IXGBE_SYSTIML 0x08C0C /* System time register Low - RO */ |
| 818 | #define IXGBE_SYSTIMH 0x08C10 /* System time register High - RO */ |
| 819 | #define IXGBE_TIMINCA 0x08C14 /* Increment attributes register - RW */ |
Emil Tantilov | 83dfde4 | 2011-03-31 09:36:24 +0000 | [diff] [blame] | 820 | #define IXGBE_TIMADJL 0x08C18 /* Time Adjustment Offset register Low - RW */ |
| 821 | #define IXGBE_TIMADJH 0x08C1C /* Time Adjustment Offset register High - RW */ |
| 822 | #define IXGBE_TSAUXC 0x08C20 /* TimeSync Auxiliary Control register - RW */ |
| 823 | #define IXGBE_TRGTTIML0 0x08C24 /* Target Time Register 0 Low - RW */ |
| 824 | #define IXGBE_TRGTTIMH0 0x08C28 /* Target Time Register 0 High - RW */ |
| 825 | #define IXGBE_TRGTTIML1 0x08C2C /* Target Time Register 1 Low - RW */ |
| 826 | #define IXGBE_TRGTTIMH1 0x08C30 /* Target Time Register 1 High - RW */ |
Jacob E Keller | 681ae1a | 2012-05-01 05:24:41 +0000 | [diff] [blame] | 827 | #define IXGBE_CLKTIML 0x08C34 /* Clock Out Time Register Low - RW */ |
| 828 | #define IXGBE_CLKTIMH 0x08C38 /* Clock Out Time Register High - RW */ |
Emil Tantilov | 83dfde4 | 2011-03-31 09:36:24 +0000 | [diff] [blame] | 829 | #define IXGBE_FREQOUT0 0x08C34 /* Frequency Out 0 Control register - RW */ |
| 830 | #define IXGBE_FREQOUT1 0x08C38 /* Frequency Out 1 Control register - RW */ |
| 831 | #define IXGBE_AUXSTMPL0 0x08C3C /* Auxiliary Time Stamp 0 register Low - RO */ |
| 832 | #define IXGBE_AUXSTMPH0 0x08C40 /* Auxiliary Time Stamp 0 register High - RO */ |
| 833 | #define IXGBE_AUXSTMPL1 0x08C44 /* Auxiliary Time Stamp 1 register Low - RO */ |
| 834 | #define IXGBE_AUXSTMPH1 0x08C48 /* Auxiliary Time Stamp 1 register High - RO */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 835 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 836 | /* Diagnostic Registers */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 837 | #define IXGBE_RDSTATCTL 0x02C20 |
| 838 | #define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */ |
| 839 | #define IXGBE_RDHMPN 0x02F08 |
Jesse Brandeburg | 98c00a1 | 2008-09-11 19:56:41 -0700 | [diff] [blame] | 840 | #define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4)) |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 841 | #define IXGBE_RDPROBE 0x02F20 |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 842 | #define IXGBE_RDMAM 0x02F30 |
| 843 | #define IXGBE_RDMAD 0x02F34 |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 844 | #define IXGBE_TDSTATCTL 0x07C20 |
| 845 | #define IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */ |
| 846 | #define IXGBE_TDHMPN 0x07F08 |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 847 | #define IXGBE_TDHMPN2 0x082FC |
| 848 | #define IXGBE_TXDESCIC 0x082CC |
Jesse Brandeburg | 98c00a1 | 2008-09-11 19:56:41 -0700 | [diff] [blame] | 849 | #define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4)) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 850 | #define IXGBE_TIC_DW2(_i) (0x082B0 + ((_i) * 4)) |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 851 | #define IXGBE_TDPROBE 0x07F20 |
| 852 | #define IXGBE_TXBUFCTRL 0x0C600 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 853 | #define IXGBE_TXBUFDATA0 0x0C610 |
| 854 | #define IXGBE_TXBUFDATA1 0x0C614 |
| 855 | #define IXGBE_TXBUFDATA2 0x0C618 |
| 856 | #define IXGBE_TXBUFDATA3 0x0C61C |
| 857 | #define IXGBE_RXBUFCTRL 0x03600 |
| 858 | #define IXGBE_RXBUFDATA0 0x03610 |
| 859 | #define IXGBE_RXBUFDATA1 0x03614 |
| 860 | #define IXGBE_RXBUFDATA2 0x03618 |
| 861 | #define IXGBE_RXBUFDATA3 0x0361C |
| 862 | #define IXGBE_PCIE_DIAG(_i) (0x11090 + ((_i) * 4)) /* 8 of these */ |
| 863 | #define IXGBE_RFVAL 0x050A4 |
| 864 | #define IXGBE_MDFTC1 0x042B8 |
| 865 | #define IXGBE_MDFTC2 0x042C0 |
| 866 | #define IXGBE_MDFTFIFO1 0x042C4 |
| 867 | #define IXGBE_MDFTFIFO2 0x042C8 |
| 868 | #define IXGBE_MDFTS 0x042CC |
| 869 | #define IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/ |
| 870 | #define IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/ |
| 871 | #define IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/ |
| 872 | #define IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/ |
| 873 | #define IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/ |
| 874 | #define IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/ |
| 875 | #define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/ |
| 876 | #define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/ |
| 877 | #define IXGBE_PCIEECCCTL 0x1106C |
Emil Tantilov | 83dfde4 | 2011-03-31 09:36:24 +0000 | [diff] [blame] | 878 | #define IXGBE_RXWRPTR(_i) (0x03100 + ((_i) * 4)) /* 8 of these 3100-310C*/ |
| 879 | #define IXGBE_RXUSED(_i) (0x03120 + ((_i) * 4)) /* 8 of these 3120-312C*/ |
| 880 | #define IXGBE_RXRDPTR(_i) (0x03140 + ((_i) * 4)) /* 8 of these 3140-314C*/ |
| 881 | #define IXGBE_RXRDWRPTR(_i) (0x03160 + ((_i) * 4)) /* 8 of these 3160-310C*/ |
| 882 | #define IXGBE_TXWRPTR(_i) (0x0C100 + ((_i) * 4)) /* 8 of these C100-C10C*/ |
| 883 | #define IXGBE_TXUSED(_i) (0x0C120 + ((_i) * 4)) /* 8 of these C120-C12C*/ |
| 884 | #define IXGBE_TXRDPTR(_i) (0x0C140 + ((_i) * 4)) /* 8 of these C140-C14C*/ |
| 885 | #define IXGBE_TXRDWRPTR(_i) (0x0C160 + ((_i) * 4)) /* 8 of these C160-C10C*/ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 886 | #define IXGBE_PCIEECCCTL0 0x11100 |
| 887 | #define IXGBE_PCIEECCCTL1 0x11104 |
Emil Tantilov | 83dfde4 | 2011-03-31 09:36:24 +0000 | [diff] [blame] | 888 | #define IXGBE_RXDBUECC 0x03F70 |
| 889 | #define IXGBE_TXDBUECC 0x0CF70 |
| 890 | #define IXGBE_RXDBUEST 0x03F74 |
| 891 | #define IXGBE_TXDBUEST 0x0CF74 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 892 | #define IXGBE_PBTXECC 0x0C300 |
| 893 | #define IXGBE_PBRXECC 0x03300 |
| 894 | #define IXGBE_GHECCR 0x110B0 |
| 895 | |
| 896 | /* MAC Registers */ |
| 897 | #define IXGBE_PCS1GCFIG 0x04200 |
| 898 | #define IXGBE_PCS1GLCTL 0x04208 |
| 899 | #define IXGBE_PCS1GLSTA 0x0420C |
| 900 | #define IXGBE_PCS1GDBG0 0x04210 |
| 901 | #define IXGBE_PCS1GDBG1 0x04214 |
| 902 | #define IXGBE_PCS1GANA 0x04218 |
| 903 | #define IXGBE_PCS1GANLP 0x0421C |
| 904 | #define IXGBE_PCS1GANNP 0x04220 |
| 905 | #define IXGBE_PCS1GANLPNP 0x04224 |
| 906 | #define IXGBE_HLREG0 0x04240 |
| 907 | #define IXGBE_HLREG1 0x04244 |
| 908 | #define IXGBE_PAP 0x04248 |
| 909 | #define IXGBE_MACA 0x0424C |
| 910 | #define IXGBE_APAE 0x04250 |
| 911 | #define IXGBE_ARD 0x04254 |
| 912 | #define IXGBE_AIS 0x04258 |
| 913 | #define IXGBE_MSCA 0x0425C |
| 914 | #define IXGBE_MSRWD 0x04260 |
| 915 | #define IXGBE_MLADD 0x04264 |
| 916 | #define IXGBE_MHADD 0x04268 |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 917 | #define IXGBE_MAXFRS 0x04268 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 918 | #define IXGBE_TREG 0x0426C |
| 919 | #define IXGBE_PCSS1 0x04288 |
| 920 | #define IXGBE_PCSS2 0x0428C |
| 921 | #define IXGBE_XPCSS 0x04290 |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 922 | #define IXGBE_MFLCN 0x04294 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 923 | #define IXGBE_SERDESC 0x04298 |
| 924 | #define IXGBE_MACS 0x0429C |
| 925 | #define IXGBE_AUTOC 0x042A0 |
| 926 | #define IXGBE_LINKS 0x042A4 |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 927 | #define IXGBE_LINKS2 0x04324 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 928 | #define IXGBE_AUTOC2 0x042A8 |
| 929 | #define IXGBE_AUTOC3 0x042AC |
| 930 | #define IXGBE_ANLP1 0x042B0 |
| 931 | #define IXGBE_ANLP2 0x042B4 |
Emil Tantilov | 83dfde4 | 2011-03-31 09:36:24 +0000 | [diff] [blame] | 932 | #define IXGBE_MACC 0x04330 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 933 | #define IXGBE_ATLASCTL 0x04800 |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 934 | #define IXGBE_MMNGC 0x042D0 |
| 935 | #define IXGBE_ANLPNP1 0x042D4 |
| 936 | #define IXGBE_ANLPNP2 0x042D8 |
| 937 | #define IXGBE_KRPCSFC 0x042E0 |
| 938 | #define IXGBE_KRPCSS 0x042E4 |
| 939 | #define IXGBE_FECS1 0x042E8 |
| 940 | #define IXGBE_FECS2 0x042EC |
| 941 | #define IXGBE_SMADARCTL 0x14F10 |
| 942 | #define IXGBE_MPVC 0x04318 |
| 943 | #define IXGBE_SGMIIC 0x04314 |
| 944 | |
Emil Tantilov | 83dfde4 | 2011-03-31 09:36:24 +0000 | [diff] [blame] | 945 | /* Statistics Registers */ |
| 946 | #define IXGBE_RXNFGPC 0x041B0 |
| 947 | #define IXGBE_RXNFGBCL 0x041B4 |
| 948 | #define IXGBE_RXNFGBCH 0x041B8 |
| 949 | #define IXGBE_RXDGPC 0x02F50 |
| 950 | #define IXGBE_RXDGBCL 0x02F54 |
| 951 | #define IXGBE_RXDGBCH 0x02F58 |
| 952 | #define IXGBE_RXDDGPC 0x02F5C |
| 953 | #define IXGBE_RXDDGBCL 0x02F60 |
| 954 | #define IXGBE_RXDDGBCH 0x02F64 |
| 955 | #define IXGBE_RXLPBKGPC 0x02F68 |
| 956 | #define IXGBE_RXLPBKGBCL 0x02F6C |
| 957 | #define IXGBE_RXLPBKGBCH 0x02F70 |
| 958 | #define IXGBE_RXDLPBKGPC 0x02F74 |
| 959 | #define IXGBE_RXDLPBKGBCL 0x02F78 |
| 960 | #define IXGBE_RXDLPBKGBCH 0x02F7C |
| 961 | #define IXGBE_TXDGPC 0x087A0 |
| 962 | #define IXGBE_TXDGBCL 0x087A4 |
| 963 | #define IXGBE_TXDGBCH 0x087A8 |
| 964 | |
| 965 | #define IXGBE_RXDSTATCTRL 0x02F40 |
| 966 | |
| 967 | /* Copper Pond 2 link timeout */ |
Mallikarjuna R Chilakala | 734e979 | 2009-12-15 11:57:20 +0000 | [diff] [blame] | 968 | #define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50 |
| 969 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 970 | /* Omer CORECTL */ |
| 971 | #define IXGBE_CORECTL 0x014F00 |
| 972 | /* BARCTRL */ |
Emil Tantilov | 83dfde4 | 2011-03-31 09:36:24 +0000 | [diff] [blame] | 973 | #define IXGBE_BARCTRL 0x110F4 |
| 974 | #define IXGBE_BARCTRL_FLSIZE 0x0700 |
| 975 | #define IXGBE_BARCTRL_FLSIZE_SHIFT 8 |
| 976 | #define IXGBE_BARCTRL_CSRSIZE 0x2000 |
| 977 | |
| 978 | /* RSCCTL Bit Masks */ |
| 979 | #define IXGBE_RSCCTL_RSCEN 0x01 |
| 980 | #define IXGBE_RSCCTL_MAXDESC_1 0x00 |
| 981 | #define IXGBE_RSCCTL_MAXDESC_4 0x04 |
| 982 | #define IXGBE_RSCCTL_MAXDESC_8 0x08 |
| 983 | #define IXGBE_RSCCTL_MAXDESC_16 0x0C |
| 984 | |
| 985 | /* RSCDBU Bit Masks */ |
| 986 | #define IXGBE_RSCDBU_RSCSMALDIS_MASK 0x0000007F |
| 987 | #define IXGBE_RSCDBU_RSCACKDIS 0x00000080 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 988 | |
Jesse Brandeburg | cc41ac7 | 2008-08-26 04:27:27 -0700 | [diff] [blame] | 989 | /* RDRXCTL Bit Masks */ |
| 990 | #define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min Threshold Size */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 991 | #define IXGBE_RDRXCTL_CRCSTRIP 0x00000002 /* CRC Strip */ |
Jesse Brandeburg | cc41ac7 | 2008-08-26 04:27:27 -0700 | [diff] [blame] | 992 | #define IXGBE_RDRXCTL_MVMEN 0x00000020 |
| 993 | #define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 994 | #define IXGBE_RDRXCTL_AGGDIS 0x00010000 /* Aggregation disable */ |
Emil Tantilov | 83dfde4 | 2011-03-31 09:36:24 +0000 | [diff] [blame] | 995 | #define IXGBE_RDRXCTL_RSCFRSTSIZE 0x003E0000 /* RSC First packet size */ |
| 996 | #define IXGBE_RDRXCTL_RSCLLIDIS 0x00800000 /* Disable RSC compl on LLI */ |
Alexander Duyck | 7367096 | 2010-08-19 13:38:34 +0000 | [diff] [blame] | 997 | #define IXGBE_RDRXCTL_RSCACKC 0x02000000 /* must set 1 when RSC enabled */ |
| 998 | #define IXGBE_RDRXCTL_FCOE_WRFIX 0x04000000 /* must set 1 when RSC enabled */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 999 | |
| 1000 | /* RQTC Bit Masks and Shifts */ |
| 1001 | #define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4) |
| 1002 | #define IXGBE_RQTC_TC0_MASK (0x7 << 0) |
| 1003 | #define IXGBE_RQTC_TC1_MASK (0x7 << 4) |
| 1004 | #define IXGBE_RQTC_TC2_MASK (0x7 << 8) |
| 1005 | #define IXGBE_RQTC_TC3_MASK (0x7 << 12) |
| 1006 | #define IXGBE_RQTC_TC4_MASK (0x7 << 16) |
| 1007 | #define IXGBE_RQTC_TC5_MASK (0x7 << 20) |
| 1008 | #define IXGBE_RQTC_TC6_MASK (0x7 << 24) |
| 1009 | #define IXGBE_RQTC_TC7_MASK (0x7 << 28) |
| 1010 | |
| 1011 | /* PSRTYPE.RQPL Bit masks and shift */ |
| 1012 | #define IXGBE_PSRTYPE_RQPL_MASK 0x7 |
| 1013 | #define IXGBE_PSRTYPE_RQPL_SHIFT 29 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1014 | |
| 1015 | /* CTRL Bit Masks */ |
| 1016 | #define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Master Disable bit */ |
| 1017 | #define IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */ |
| 1018 | #define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */ |
Alexander Duyck | 8132b54 | 2011-07-15 07:29:44 +0000 | [diff] [blame] | 1019 | #define IXGBE_CTRL_RST_MASK (IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1020 | |
| 1021 | /* FACTPS */ |
| 1022 | #define IXGBE_FACTPS_LFS 0x40000000 /* LAN Function Select */ |
| 1023 | |
| 1024 | /* MHADD Bit Masks */ |
| 1025 | #define IXGBE_MHADD_MFS_MASK 0xFFFF0000 |
| 1026 | #define IXGBE_MHADD_MFS_SHIFT 16 |
| 1027 | |
| 1028 | /* Extended Device Control */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1029 | #define IXGBE_CTRL_EXT_PFRSTD 0x00004000 /* Physical Function Reset Done */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1030 | #define IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */ |
| 1031 | #define IXGBE_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ |
| 1032 | #define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ |
| 1033 | |
| 1034 | /* Direct Cache Access (DCA) definitions */ |
| 1035 | #define IXGBE_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */ |
| 1036 | #define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */ |
| 1037 | |
| 1038 | #define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */ |
| 1039 | #define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */ |
| 1040 | |
| 1041 | #define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1042 | #define IXGBE_DCA_RXCTRL_CPUID_MASK_82599 0xFF000000 /* Rx CPUID Mask */ |
| 1043 | #define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1044 | #define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */ |
| 1045 | #define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */ |
| 1046 | #define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */ |
Don Skidmore | 15005a3 | 2009-01-19 16:54:13 -0800 | [diff] [blame] | 1047 | #define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx rd Desc Relax Order */ |
Alexander Duyck | bdda1a6 | 2012-02-08 07:50:14 +0000 | [diff] [blame] | 1048 | #define IXGBE_DCA_RXCTRL_DATA_WRO_EN (1 << 13) /* Rx wr data Relax Order */ |
| 1049 | #define IXGBE_DCA_RXCTRL_HEAD_WRO_EN (1 << 15) /* Rx wr header RO */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1050 | |
| 1051 | #define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1052 | #define IXGBE_DCA_TXCTRL_CPUID_MASK_82599 0xFF000000 /* Tx CPUID Mask */ |
| 1053 | #define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1054 | #define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */ |
Alexander Duyck | bdda1a6 | 2012-02-08 07:50:14 +0000 | [diff] [blame] | 1055 | #define IXGBE_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */ |
| 1056 | #define IXGBE_DCA_TXCTRL_DESC_WRO_EN (1 << 11) /* Tx Desc writeback RO bit */ |
| 1057 | #define IXGBE_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1058 | #define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */ |
| 1059 | |
| 1060 | /* MSCA Bit Masks */ |
| 1061 | #define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Address (new protocol) */ |
| 1062 | #define IXGBE_MSCA_NP_ADDR_SHIFT 0 |
| 1063 | #define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000 /* Device Type (new protocol) */ |
| 1064 | #define IXGBE_MSCA_DEV_TYPE_SHIFT 16 /* Register Address (old protocol */ |
| 1065 | #define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000 /* PHY Address mask */ |
| 1066 | #define IXGBE_MSCA_PHY_ADDR_SHIFT 21 /* PHY Address shift*/ |
| 1067 | #define IXGBE_MSCA_OP_CODE_MASK 0x0C000000 /* OP CODE mask */ |
| 1068 | #define IXGBE_MSCA_OP_CODE_SHIFT 26 /* OP CODE shift */ |
| 1069 | #define IXGBE_MSCA_ADDR_CYCLE 0x00000000 /* OP CODE 00 (addr cycle) */ |
| 1070 | #define IXGBE_MSCA_WRITE 0x04000000 /* OP CODE 01 (write) */ |
Emil Tantilov | 83dfde4 | 2011-03-31 09:36:24 +0000 | [diff] [blame] | 1071 | #define IXGBE_MSCA_READ 0x0C000000 /* OP CODE 11 (read) */ |
| 1072 | #define IXGBE_MSCA_READ_AUTOINC 0x08000000 /* OP CODE 10 (read, auto inc)*/ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1073 | #define IXGBE_MSCA_ST_CODE_MASK 0x30000000 /* ST Code mask */ |
| 1074 | #define IXGBE_MSCA_ST_CODE_SHIFT 28 /* ST Code shift */ |
| 1075 | #define IXGBE_MSCA_NEW_PROTOCOL 0x00000000 /* ST CODE 00 (new protocol) */ |
| 1076 | #define IXGBE_MSCA_OLD_PROTOCOL 0x10000000 /* ST CODE 01 (old protocol) */ |
| 1077 | #define IXGBE_MSCA_MDI_COMMAND 0x40000000 /* Initiate MDI command */ |
| 1078 | #define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000 /* MDI in progress enable */ |
| 1079 | |
| 1080 | /* MSRWD bit masks */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1081 | #define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF |
| 1082 | #define IXGBE_MSRWD_WRITE_DATA_SHIFT 0 |
| 1083 | #define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000 |
| 1084 | #define IXGBE_MSRWD_READ_DATA_SHIFT 16 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1085 | |
| 1086 | /* Atlas registers */ |
| 1087 | #define IXGBE_ATLAS_PDN_LPBK 0x24 |
| 1088 | #define IXGBE_ATLAS_PDN_10G 0xB |
| 1089 | #define IXGBE_ATLAS_PDN_1G 0xC |
| 1090 | #define IXGBE_ATLAS_PDN_AN 0xD |
| 1091 | |
| 1092 | /* Atlas bit masks */ |
| 1093 | #define IXGBE_ATLASCTL_WRITE_CMD 0x00010000 |
| 1094 | #define IXGBE_ATLAS_PDN_TX_REG_EN 0x10 |
| 1095 | #define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0 |
| 1096 | #define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0 |
| 1097 | #define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0 |
| 1098 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1099 | /* Omer bit masks */ |
| 1100 | #define IXGBE_CORECTL_WRITE_CMD 0x00010000 |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1101 | |
Ben Hutchings | 6b73e10 | 2009-04-29 08:08:58 +0000 | [diff] [blame] | 1102 | /* MDIO definitions */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1103 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1104 | #define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */ |
| 1105 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1106 | #define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Control Reg */ |
| 1107 | #define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */ |
| 1108 | #define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */ |
| 1109 | #define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */ |
| 1110 | #define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018 |
| 1111 | #define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010 |
| 1112 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1113 | #define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1114 | #define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */ |
| 1115 | #define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */ |
| 1116 | |
Emil Tantilov | 9dda173 | 2011-03-05 01:28:07 +0000 | [diff] [blame] | 1117 | /* MII clause 22/28 definitions */ |
| 1118 | #define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */ |
| 1119 | #define IXGBE_MII_AUTONEG_XNP_TX_REG 0x17 /* 1G XNP Transmit */ |
| 1120 | #define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX 0x4000 /* full duplex, bit:14*/ |
| 1121 | #define IXGBE_MII_1GBASE_T_ADVERTISE 0x8000 /* full duplex, bit:15*/ |
| 1122 | #define IXGBE_MII_AUTONEG_REG 0x0 |
| 1123 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1124 | #define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0 |
| 1125 | #define IXGBE_MAX_PHY_ADDR 32 |
| 1126 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1127 | /* PHY IDs*/ |
Jesse Brandeburg | 0befdb3 | 2008-10-31 00:46:40 -0700 | [diff] [blame] | 1128 | #define TN1010_PHY_ID 0x00A19410 |
| 1129 | #define TNX_FW_REV 0xB |
Don Skidmore | 2b26490 | 2010-12-09 06:55:14 +0000 | [diff] [blame] | 1130 | #define X540_PHY_ID 0x01540200 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1131 | #define QT2022_PHY_ID 0x0043A400 |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 1132 | #define ATH_PHY_ID 0x03429050 |
Don Skidmore | fe15e8e | 2010-11-16 19:27:16 -0800 | [diff] [blame] | 1133 | #define AQ_FW_REV 0x20 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1134 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1135 | /* PHY Types */ |
| 1136 | #define IXGBE_M88E1145_E_PHY_ID 0x01410CD0 |
| 1137 | |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 1138 | /* Special PHY Init Routine */ |
| 1139 | #define IXGBE_PHY_INIT_OFFSET_NL 0x002B |
| 1140 | #define IXGBE_PHY_INIT_END_NL 0xFFFF |
| 1141 | #define IXGBE_CONTROL_MASK_NL 0xF000 |
| 1142 | #define IXGBE_DATA_MASK_NL 0x0FFF |
| 1143 | #define IXGBE_CONTROL_SHIFT_NL 12 |
| 1144 | #define IXGBE_DELAY_NL 0 |
| 1145 | #define IXGBE_DATA_NL 1 |
| 1146 | #define IXGBE_CONTROL_NL 0x000F |
| 1147 | #define IXGBE_CONTROL_EOL_NL 0x0FFF |
| 1148 | #define IXGBE_CONTROL_SOL_NL 0x0000 |
| 1149 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1150 | /* General purpose Interrupt Enable */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1151 | #define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */ |
| 1152 | #define IXGBE_SDP1_GPIEN 0x00000002 /* SDP1 */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1153 | #define IXGBE_SDP2_GPIEN 0x00000004 /* SDP2 */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1154 | #define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */ |
| 1155 | #define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */ |
| 1156 | #define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */ |
| 1157 | #define IXGBE_GPIE_EIAME 0x40000000 |
| 1158 | #define IXGBE_GPIE_PBA_SUPPORT 0x80000000 |
Emil Tantilov | 83dfde4 | 2011-03-31 09:36:24 +0000 | [diff] [blame] | 1159 | #define IXGBE_GPIE_RSC_DELAY_SHIFT 11 |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1160 | #define IXGBE_GPIE_VTMODE_MASK 0x0000C000 /* VT Mode Mask */ |
| 1161 | #define IXGBE_GPIE_VTMODE_16 0x00004000 /* 16 VFs 8 queues per VF */ |
| 1162 | #define IXGBE_GPIE_VTMODE_32 0x00008000 /* 32 VFs 4 queues per VF */ |
| 1163 | #define IXGBE_GPIE_VTMODE_64 0x0000C000 /* 64 VFs 2 queues per VF */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1164 | |
John Fastabend | 80605c65 | 2011-05-02 12:34:10 +0000 | [diff] [blame] | 1165 | /* Packet Buffer Initialization */ |
| 1166 | #define IXGBE_TXPBSIZE_20KB 0x00005000 /* 20KB Packet Buffer */ |
| 1167 | #define IXGBE_TXPBSIZE_40KB 0x0000A000 /* 40KB Packet Buffer */ |
| 1168 | #define IXGBE_RXPBSIZE_48KB 0x0000C000 /* 48KB Packet Buffer */ |
| 1169 | #define IXGBE_RXPBSIZE_64KB 0x00010000 /* 64KB Packet Buffer */ |
| 1170 | #define IXGBE_RXPBSIZE_80KB 0x00014000 /* 80KB Packet Buffer */ |
| 1171 | #define IXGBE_RXPBSIZE_128KB 0x00020000 /* 128KB Packet Buffer */ |
| 1172 | #define IXGBE_RXPBSIZE_MAX 0x00080000 /* 512KB Packet Buffer*/ |
| 1173 | #define IXGBE_TXPBSIZE_MAX 0x00028000 /* 160KB Packet Buffer*/ |
| 1174 | |
| 1175 | #define IXGBE_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */ |
| 1176 | #define IXGBE_MAX_PB 8 |
| 1177 | |
| 1178 | /* Packet buffer allocation strategies */ |
| 1179 | enum { |
| 1180 | PBA_STRATEGY_EQUAL = 0, /* Distribute PB space equally */ |
| 1181 | #define PBA_STRATEGY_EQUAL PBA_STRATEGY_EQUAL |
| 1182 | PBA_STRATEGY_WEIGHTED = 1, /* Weight front half of TCs */ |
| 1183 | #define PBA_STRATEGY_WEIGHTED PBA_STRATEGY_WEIGHTED |
| 1184 | }; |
| 1185 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1186 | /* Transmit Flow Control status */ |
| 1187 | #define IXGBE_TFCS_TXOFF 0x00000001 |
| 1188 | #define IXGBE_TFCS_TXOFF0 0x00000100 |
| 1189 | #define IXGBE_TFCS_TXOFF1 0x00000200 |
| 1190 | #define IXGBE_TFCS_TXOFF2 0x00000400 |
| 1191 | #define IXGBE_TFCS_TXOFF3 0x00000800 |
| 1192 | #define IXGBE_TFCS_TXOFF4 0x00001000 |
| 1193 | #define IXGBE_TFCS_TXOFF5 0x00002000 |
| 1194 | #define IXGBE_TFCS_TXOFF6 0x00004000 |
| 1195 | #define IXGBE_TFCS_TXOFF7 0x00008000 |
| 1196 | |
| 1197 | /* TCP Timer */ |
| 1198 | #define IXGBE_TCPTIMER_KS 0x00000100 |
| 1199 | #define IXGBE_TCPTIMER_COUNT_ENABLE 0x00000200 |
| 1200 | #define IXGBE_TCPTIMER_COUNT_FINISH 0x00000400 |
| 1201 | #define IXGBE_TCPTIMER_LOOP 0x00000800 |
| 1202 | #define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF |
| 1203 | |
| 1204 | /* HLREG0 Bit Masks */ |
| 1205 | #define IXGBE_HLREG0_TXCRCEN 0x00000001 /* bit 0 */ |
| 1206 | #define IXGBE_HLREG0_RXCRCSTRP 0x00000002 /* bit 1 */ |
| 1207 | #define IXGBE_HLREG0_JUMBOEN 0x00000004 /* bit 2 */ |
| 1208 | #define IXGBE_HLREG0_TXPADEN 0x00000400 /* bit 10 */ |
| 1209 | #define IXGBE_HLREG0_TXPAUSEEN 0x00001000 /* bit 12 */ |
| 1210 | #define IXGBE_HLREG0_RXPAUSEEN 0x00004000 /* bit 14 */ |
| 1211 | #define IXGBE_HLREG0_LPBK 0x00008000 /* bit 15 */ |
| 1212 | #define IXGBE_HLREG0_MDCSPD 0x00010000 /* bit 16 */ |
| 1213 | #define IXGBE_HLREG0_CONTMDC 0x00020000 /* bit 17 */ |
| 1214 | #define IXGBE_HLREG0_CTRLFLTR 0x00040000 /* bit 18 */ |
| 1215 | #define IXGBE_HLREG0_PREPEND 0x00F00000 /* bits 20-23 */ |
| 1216 | #define IXGBE_HLREG0_PRIPAUSEEN 0x01000000 /* bit 24 */ |
| 1217 | #define IXGBE_HLREG0_RXPAUSERECDA 0x06000000 /* bits 25-26 */ |
| 1218 | #define IXGBE_HLREG0_RXLNGTHERREN 0x08000000 /* bit 27 */ |
| 1219 | #define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000 /* bit 28 */ |
| 1220 | |
| 1221 | /* VMD_CTL bitmasks */ |
| 1222 | #define IXGBE_VMD_CTL_VMDQ_EN 0x00000001 |
| 1223 | #define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002 |
| 1224 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1225 | /* VT_CTL bitmasks */ |
| 1226 | #define IXGBE_VT_CTL_DIS_DEFPL 0x20000000 /* disable default pool */ |
| 1227 | #define IXGBE_VT_CTL_REPLEN 0x40000000 /* replication enabled */ |
| 1228 | #define IXGBE_VT_CTL_VT_ENABLE 0x00000001 /* Enable VT Mode */ |
Don Skidmore | 6e4e87d | 2009-04-09 22:27:00 +0000 | [diff] [blame] | 1229 | #define IXGBE_VT_CTL_POOL_SHIFT 7 |
| 1230 | #define IXGBE_VT_CTL_POOL_MASK (0x3F << IXGBE_VT_CTL_POOL_SHIFT) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1231 | |
| 1232 | /* VMOLR bitmasks */ |
| 1233 | #define IXGBE_VMOLR_AUPE 0x01000000 /* accept untagged packets */ |
| 1234 | #define IXGBE_VMOLR_ROMPE 0x02000000 /* accept packets in MTA tbl */ |
| 1235 | #define IXGBE_VMOLR_ROPE 0x04000000 /* accept packets in UC tbl */ |
| 1236 | #define IXGBE_VMOLR_BAM 0x08000000 /* accept broadcast packets */ |
| 1237 | #define IXGBE_VMOLR_MPE 0x10000000 /* multicast promiscuous */ |
| 1238 | |
| 1239 | /* VFRE bitmask */ |
| 1240 | #define IXGBE_VFRE_ENABLE_ALL 0xFFFFFFFF |
| 1241 | |
Greg Rose | 7f87047 | 2010-01-09 02:25:29 +0000 | [diff] [blame] | 1242 | #define IXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ |
| 1243 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1244 | /* RDHMPN and TDHMPN bitmasks */ |
| 1245 | #define IXGBE_RDHMPN_RDICADDR 0x007FF800 |
| 1246 | #define IXGBE_RDHMPN_RDICRDREQ 0x00800000 |
| 1247 | #define IXGBE_RDHMPN_RDICADDR_SHIFT 11 |
| 1248 | #define IXGBE_TDHMPN_TDICADDR 0x003FF800 |
| 1249 | #define IXGBE_TDHMPN_TDICRDREQ 0x00800000 |
| 1250 | #define IXGBE_TDHMPN_TDICADDR_SHIFT 11 |
| 1251 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1252 | #define IXGBE_RDMAM_MEM_SEL_SHIFT 13 |
| 1253 | #define IXGBE_RDMAM_DWORD_SHIFT 9 |
| 1254 | #define IXGBE_RDMAM_DESC_COMP_FIFO 1 |
| 1255 | #define IXGBE_RDMAM_DFC_CMD_FIFO 2 |
| 1256 | #define IXGBE_RDMAM_TCN_STATUS_RAM 4 |
| 1257 | #define IXGBE_RDMAM_WB_COLL_FIFO 5 |
| 1258 | #define IXGBE_RDMAM_QSC_CNT_RAM 6 |
| 1259 | #define IXGBE_RDMAM_QSC_QUEUE_CNT 8 |
| 1260 | #define IXGBE_RDMAM_QSC_QUEUE_RAM 0xA |
| 1261 | #define IXGBE_RDMAM_DESC_COM_FIFO_RANGE 135 |
| 1262 | #define IXGBE_RDMAM_DESC_COM_FIFO_COUNT 4 |
| 1263 | #define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE 48 |
| 1264 | #define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT 7 |
| 1265 | #define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE 256 |
| 1266 | #define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT 9 |
| 1267 | #define IXGBE_RDMAM_WB_COLL_FIFO_RANGE 8 |
| 1268 | #define IXGBE_RDMAM_WB_COLL_FIFO_COUNT 4 |
| 1269 | #define IXGBE_RDMAM_QSC_CNT_RAM_RANGE 64 |
| 1270 | #define IXGBE_RDMAM_QSC_CNT_RAM_COUNT 4 |
| 1271 | #define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE 32 |
| 1272 | #define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT 4 |
| 1273 | #define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE 128 |
| 1274 | #define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT 8 |
| 1275 | |
| 1276 | #define IXGBE_TXDESCIC_READY 0x80000000 |
| 1277 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1278 | /* Receive Checksum Control */ |
| 1279 | #define IXGBE_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ |
| 1280 | #define IXGBE_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ |
| 1281 | |
| 1282 | /* FCRTL Bit Masks */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1283 | #define IXGBE_FCRTL_XONE 0x80000000 /* XON enable */ |
| 1284 | #define IXGBE_FCRTH_FCEN 0x80000000 /* Packet buffer fc enable */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1285 | |
| 1286 | /* PAP bit masks*/ |
| 1287 | #define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */ |
| 1288 | |
| 1289 | /* RMCS Bit Masks */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1290 | #define IXGBE_RMCS_RRM 0x00000002 /* Receive Recycle Mode enable */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1291 | /* Receive Arbitration Control: 0 Round Robin, 1 DFP */ |
| 1292 | #define IXGBE_RMCS_RAC 0x00000004 |
| 1293 | #define IXGBE_RMCS_DFP IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1294 | #define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority FC ena */ |
| 1295 | #define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority FC ena */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1296 | #define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */ |
| 1297 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1298 | /* FCCFG Bit Masks */ |
| 1299 | #define IXGBE_FCCFG_TFCE_802_3X 0x00000008 /* Tx link FC enable */ |
| 1300 | #define IXGBE_FCCFG_TFCE_PRIORITY 0x00000010 /* Tx priority FC enable */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1301 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1302 | /* Interrupt register bitmasks */ |
| 1303 | |
| 1304 | /* Extended Interrupt Cause Read */ |
| 1305 | #define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1306 | #define IXGBE_EICR_FLOW_DIR 0x00010000 /* FDir Exception */ |
| 1307 | #define IXGBE_EICR_RX_MISS 0x00020000 /* Packet Buffer Overrun */ |
| 1308 | #define IXGBE_EICR_PCI 0x00040000 /* PCI Exception */ |
| 1309 | #define IXGBE_EICR_MAILBOX 0x00080000 /* VF to PF Mailbox Interrupt */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1310 | #define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1311 | #define IXGBE_EICR_LINKSEC 0x00200000 /* PN Threshold */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1312 | #define IXGBE_EICR_MNG 0x00400000 /* Manageability Event Interrupt */ |
Jacob Keller | 4f51bf7 | 2011-08-20 04:49:45 +0000 | [diff] [blame] | 1313 | #define IXGBE_EICR_TS 0x00800000 /* Thermal Sensor Event */ |
Jacob E Keller | 681ae1a | 2012-05-01 05:24:41 +0000 | [diff] [blame] | 1314 | #define IXGBE_EICR_TIMESYNC 0x01000000 /* Timesync Event */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1315 | #define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */ |
| 1316 | #define IXGBE_EICR_GPI_SDP1 0x02000000 /* Gen Purpose Interrupt on SDP1 */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1317 | #define IXGBE_EICR_GPI_SDP2 0x04000000 /* Gen Purpose Interrupt on SDP2 */ |
| 1318 | #define IXGBE_EICR_ECC 0x10000000 /* ECC Error */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1319 | #define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */ |
| 1320 | #define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */ |
| 1321 | #define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */ |
| 1322 | #define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ |
| 1323 | |
| 1324 | /* Extended Interrupt Cause Set */ |
| 1325 | #define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1326 | #define IXGBE_EICS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */ |
| 1327 | #define IXGBE_EICS_RX_MISS IXGBE_EICR_RX_MISS /* Pkt Buffer Overrun */ |
| 1328 | #define IXGBE_EICS_PCI IXGBE_EICR_PCI /* PCI Exception */ |
| 1329 | #define IXGBE_EICS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1330 | #define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */ |
| 1331 | #define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ |
Jacob E Keller | 681ae1a | 2012-05-01 05:24:41 +0000 | [diff] [blame] | 1332 | #define IXGBE_EICS_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1333 | #define IXGBE_EICS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ |
| 1334 | #define IXGBE_EICS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1335 | #define IXGBE_EICS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */ |
| 1336 | #define IXGBE_EICS_ECC IXGBE_EICR_ECC /* ECC Error */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1337 | #define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ |
| 1338 | #define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1339 | #define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ |
| 1340 | #define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ |
| 1341 | |
| 1342 | /* Extended Interrupt Mask Set */ |
| 1343 | #define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1344 | #define IXGBE_EIMS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */ |
| 1345 | #define IXGBE_EIMS_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */ |
| 1346 | #define IXGBE_EIMS_PCI IXGBE_EICR_PCI /* PCI Exception */ |
| 1347 | #define IXGBE_EIMS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1348 | #define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */ |
| 1349 | #define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ |
Jacob Keller | 4f51bf7 | 2011-08-20 04:49:45 +0000 | [diff] [blame] | 1350 | #define IXGBE_EIMS_TS IXGBE_EICR_TS /* Thermel Sensor Event */ |
Jacob E Keller | 681ae1a | 2012-05-01 05:24:41 +0000 | [diff] [blame] | 1351 | #define IXGBE_EIMS_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1352 | #define IXGBE_EIMS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ |
| 1353 | #define IXGBE_EIMS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1354 | #define IXGBE_EIMS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */ |
| 1355 | #define IXGBE_EIMS_ECC IXGBE_EICR_ECC /* ECC Error */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1356 | #define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1357 | #define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */ |
| 1358 | #define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ |
| 1359 | #define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ |
| 1360 | |
| 1361 | /* Extended Interrupt Mask Clear */ |
| 1362 | #define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1363 | #define IXGBE_EIMC_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */ |
| 1364 | #define IXGBE_EIMC_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */ |
| 1365 | #define IXGBE_EIMC_PCI IXGBE_EICR_PCI /* PCI Exception */ |
| 1366 | #define IXGBE_EIMC_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1367 | #define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */ |
| 1368 | #define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ |
Jacob E Keller | 681ae1a | 2012-05-01 05:24:41 +0000 | [diff] [blame] | 1369 | #define IXGBE_EIMC_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1370 | #define IXGBE_EIMC_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ |
| 1371 | #define IXGBE_EIMC_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1372 | #define IXGBE_EIMC_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */ |
| 1373 | #define IXGBE_EIMC_ECC IXGBE_EICR_ECC /* ECC Error */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1374 | #define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ |
| 1375 | #define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Err */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1376 | #define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ |
| 1377 | #define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ |
| 1378 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1379 | #define IXGBE_EIMS_ENABLE_MASK ( \ |
| 1380 | IXGBE_EIMS_RTX_QUEUE | \ |
| 1381 | IXGBE_EIMS_LSC | \ |
| 1382 | IXGBE_EIMS_TCP_TIMER | \ |
| 1383 | IXGBE_EIMS_OTHER) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1384 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1385 | /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1386 | #define IXGBE_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */ |
| 1387 | #define IXGBE_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */ |
| 1388 | #define IXGBE_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */ |
| 1389 | #define IXGBE_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */ |
| 1390 | #define IXGBE_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */ |
| 1391 | #define IXGBE_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */ |
| 1392 | #define IXGBE_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */ |
| 1393 | #define IXGBE_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */ |
| 1394 | #define IXGBE_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */ |
| 1395 | #define IXGBE_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of control bits */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1396 | #define IXGBE_IMIR_SIZE_BP_82599 0x00001000 /* Packet size bypass */ |
| 1397 | #define IXGBE_IMIR_CTRL_URG_82599 0x00002000 /* Check URG bit in header */ |
| 1398 | #define IXGBE_IMIR_CTRL_ACK_82599 0x00004000 /* Check ACK bit in header */ |
| 1399 | #define IXGBE_IMIR_CTRL_PSH_82599 0x00008000 /* Check PSH bit in header */ |
| 1400 | #define IXGBE_IMIR_CTRL_RST_82599 0x00010000 /* Check RST bit in header */ |
| 1401 | #define IXGBE_IMIR_CTRL_SYN_82599 0x00020000 /* Check SYN bit in header */ |
| 1402 | #define IXGBE_IMIR_CTRL_FIN_82599 0x00040000 /* Check FIN bit in header */ |
| 1403 | #define IXGBE_IMIR_CTRL_BP_82599 0x00080000 /* Bypass check of control bits */ |
| 1404 | #define IXGBE_IMIR_LLI_EN_82599 0x00100000 /* Enables low latency Int */ |
| 1405 | #define IXGBE_IMIR_RX_QUEUE_MASK_82599 0x0000007F /* Rx Queue Mask */ |
| 1406 | #define IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21 /* Rx Queue Shift */ |
| 1407 | #define IXGBE_IMIRVP_PRIORITY_MASK 0x00000007 /* VLAN priority mask */ |
| 1408 | #define IXGBE_IMIRVP_PRIORITY_EN 0x00000008 /* VLAN priority enable */ |
| 1409 | |
| 1410 | #define IXGBE_MAX_FTQF_FILTERS 128 |
| 1411 | #define IXGBE_FTQF_PROTOCOL_MASK 0x00000003 |
| 1412 | #define IXGBE_FTQF_PROTOCOL_TCP 0x00000000 |
| 1413 | #define IXGBE_FTQF_PROTOCOL_UDP 0x00000001 |
| 1414 | #define IXGBE_FTQF_PROTOCOL_SCTP 2 |
| 1415 | #define IXGBE_FTQF_PRIORITY_MASK 0x00000007 |
| 1416 | #define IXGBE_FTQF_PRIORITY_SHIFT 2 |
| 1417 | #define IXGBE_FTQF_POOL_MASK 0x0000003F |
| 1418 | #define IXGBE_FTQF_POOL_SHIFT 8 |
| 1419 | #define IXGBE_FTQF_5TUPLE_MASK_MASK 0x0000001F |
| 1420 | #define IXGBE_FTQF_5TUPLE_MASK_SHIFT 25 |
Emil Tantilov | 83dfde4 | 2011-03-31 09:36:24 +0000 | [diff] [blame] | 1421 | #define IXGBE_FTQF_SOURCE_ADDR_MASK 0x1E |
| 1422 | #define IXGBE_FTQF_DEST_ADDR_MASK 0x1D |
| 1423 | #define IXGBE_FTQF_SOURCE_PORT_MASK 0x1B |
| 1424 | #define IXGBE_FTQF_DEST_PORT_MASK 0x17 |
| 1425 | #define IXGBE_FTQF_PROTOCOL_COMP_MASK 0x0F |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1426 | #define IXGBE_FTQF_POOL_MASK_EN 0x40000000 |
| 1427 | #define IXGBE_FTQF_QUEUE_ENABLE 0x80000000 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1428 | |
| 1429 | /* Interrupt clear mask */ |
| 1430 | #define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF |
| 1431 | |
| 1432 | /* Interrupt Vector Allocation Registers */ |
| 1433 | #define IXGBE_IVAR_REG_NUM 25 |
Don Skidmore | e80e887 | 2009-04-09 22:27:19 +0000 | [diff] [blame] | 1434 | #define IXGBE_IVAR_REG_NUM_82599 64 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1435 | #define IXGBE_IVAR_TXRX_ENTRY 96 |
| 1436 | #define IXGBE_IVAR_RX_ENTRY 64 |
| 1437 | #define IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i)) |
| 1438 | #define IXGBE_IVAR_TX_QUEUE(_i) (64 + (_i)) |
| 1439 | #define IXGBE_IVAR_TX_ENTRY 32 |
| 1440 | |
| 1441 | #define IXGBE_IVAR_TCP_TIMER_INDEX 96 /* 0 based index */ |
| 1442 | #define IXGBE_IVAR_OTHER_CAUSES_INDEX 97 /* 0 based index */ |
| 1443 | |
| 1444 | #define IXGBE_MSIX_VECTOR(_i) (0 + (_i)) |
| 1445 | |
| 1446 | #define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */ |
| 1447 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1448 | /* ETYPE Queue Filter/Select Bit Masks */ |
| 1449 | #define IXGBE_MAX_ETQF_FILTERS 8 |
Yi Zou | bff6617 | 2009-05-13 13:09:39 +0000 | [diff] [blame] | 1450 | #define IXGBE_ETQF_FCOE 0x08000000 /* bit 27 */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1451 | #define IXGBE_ETQF_BCN 0x10000000 /* bit 28 */ |
| 1452 | #define IXGBE_ETQF_1588 0x40000000 /* bit 30 */ |
| 1453 | #define IXGBE_ETQF_FILTER_EN 0x80000000 /* bit 31 */ |
| 1454 | #define IXGBE_ETQF_POOL_ENABLE (1 << 26) /* bit 26 */ |
Alexander Duyck | 81fadde | 2012-05-05 05:32:37 +0000 | [diff] [blame] | 1455 | #define IXGBE_ETQF_POOL_SHIFT 20 |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1456 | |
| 1457 | #define IXGBE_ETQS_RX_QUEUE 0x007F0000 /* bits 22:16 */ |
| 1458 | #define IXGBE_ETQS_RX_QUEUE_SHIFT 16 |
| 1459 | #define IXGBE_ETQS_LLI 0x20000000 /* bit 29 */ |
| 1460 | #define IXGBE_ETQS_QUEUE_EN 0x80000000 /* bit 31 */ |
| 1461 | |
| 1462 | /* |
| 1463 | * ETQF filter list: one static filter per filter consumer. This is |
| 1464 | * to avoid filter collisions later. Add new filters |
| 1465 | * here!! |
| 1466 | * |
| 1467 | * Current filters: |
| 1468 | * EAPOL 802.1x (0x888e): Filter 0 |
Emil Tantilov | 83dfde4 | 2011-03-31 09:36:24 +0000 | [diff] [blame] | 1469 | * FCoE (0x8906): Filter 2 |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1470 | * 1588 (0x88f7): Filter 3 |
Emil Tantilov | 83dfde4 | 2011-03-31 09:36:24 +0000 | [diff] [blame] | 1471 | * FIP (0x8914): Filter 4 |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1472 | */ |
| 1473 | #define IXGBE_ETQF_FILTER_EAPOL 0 |
Yi Zou | bff6617 | 2009-05-13 13:09:39 +0000 | [diff] [blame] | 1474 | #define IXGBE_ETQF_FILTER_FCOE 2 |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1475 | #define IXGBE_ETQF_FILTER_1588 3 |
Chris Leech | af06393 | 2010-03-24 12:45:21 +0000 | [diff] [blame] | 1476 | #define IXGBE_ETQF_FILTER_FIP 4 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1477 | /* VLAN Control Bit Masks */ |
| 1478 | #define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */ |
| 1479 | #define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */ |
| 1480 | #define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */ |
| 1481 | #define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */ |
| 1482 | #define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */ |
| 1483 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1484 | /* VLAN pool filtering masks */ |
| 1485 | #define IXGBE_VLVF_VIEN 0x80000000 /* filter is valid */ |
| 1486 | #define IXGBE_VLVF_ENTRIES 64 |
Greg Rose | 7f87047 | 2010-01-09 02:25:29 +0000 | [diff] [blame] | 1487 | #define IXGBE_VLVF_VLANID_MASK 0x00000FFF |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1488 | |
Greg Rose | 7f01648 | 2010-05-04 22:12:06 +0000 | [diff] [blame] | 1489 | /* Per VF Port VLAN insertion rules */ |
| 1490 | #define IXGBE_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */ |
| 1491 | #define IXGBE_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */ |
| 1492 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1493 | #define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */ |
| 1494 | |
| 1495 | /* STATUS Bit Masks */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1496 | #define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */ |
| 1497 | #define IXGBE_STATUS_LAN_ID_SHIFT 2 /* LAN ID Shift*/ |
| 1498 | #define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1499 | |
| 1500 | #define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */ |
| 1501 | #define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */ |
| 1502 | |
| 1503 | /* ESDP Bit Masks */ |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 1504 | #define IXGBE_ESDP_SDP0 0x00000001 /* SDP0 Data Value */ |
| 1505 | #define IXGBE_ESDP_SDP1 0x00000002 /* SDP1 Data Value */ |
| 1506 | #define IXGBE_ESDP_SDP2 0x00000004 /* SDP2 Data Value */ |
| 1507 | #define IXGBE_ESDP_SDP3 0x00000008 /* SDP3 Data Value */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1508 | #define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */ |
| 1509 | #define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */ |
| 1510 | #define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */ |
Jacob E Keller | 681ae1a | 2012-05-01 05:24:41 +0000 | [diff] [blame] | 1511 | #define IXGBE_ESDP_SDP0_DIR 0x00000100 /* SDP0 IO direction */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1512 | #define IXGBE_ESDP_SDP4_DIR 0x00000004 /* SDP4 IO direction */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1513 | #define IXGBE_ESDP_SDP5_DIR 0x00002000 /* SDP5 IO direction */ |
Jacob E Keller | 681ae1a | 2012-05-01 05:24:41 +0000 | [diff] [blame] | 1514 | #define IXGBE_ESDP_SDP0_NATIVE 0x00010000 /* SDP0 Native Function */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1515 | |
| 1516 | /* LEDCTL Bit Masks */ |
| 1517 | #define IXGBE_LED_IVRT_BASE 0x00000040 |
| 1518 | #define IXGBE_LED_BLINK_BASE 0x00000080 |
| 1519 | #define IXGBE_LED_MODE_MASK_BASE 0x0000000F |
| 1520 | #define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i))) |
Alexander Duyck | 795be95 | 2012-01-18 22:13:30 +0000 | [diff] [blame] | 1521 | #define IXGBE_LED_MODE_SHIFT(_i) (8 * (_i)) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1522 | #define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i) |
| 1523 | #define IXGBE_LED_BLINK(_i) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i) |
| 1524 | #define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i) |
| 1525 | |
| 1526 | /* LED modes */ |
| 1527 | #define IXGBE_LED_LINK_UP 0x0 |
| 1528 | #define IXGBE_LED_LINK_10G 0x1 |
| 1529 | #define IXGBE_LED_MAC 0x2 |
| 1530 | #define IXGBE_LED_FILTER 0x3 |
| 1531 | #define IXGBE_LED_LINK_ACTIVE 0x4 |
| 1532 | #define IXGBE_LED_LINK_1G 0x5 |
| 1533 | #define IXGBE_LED_ON 0xE |
| 1534 | #define IXGBE_LED_OFF 0xF |
| 1535 | |
| 1536 | /* AUTOC Bit Masks */ |
Peter P Waskiewicz Jr | 3201d31 | 2009-02-05 23:54:21 -0800 | [diff] [blame] | 1537 | #define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1538 | #define IXGBE_AUTOC_KX4_SUPP 0x80000000 |
| 1539 | #define IXGBE_AUTOC_KX_SUPP 0x40000000 |
| 1540 | #define IXGBE_AUTOC_PAUSE 0x30000000 |
Peter P Waskiewicz Jr | 539e5f0 | 2009-09-30 12:07:38 +0000 | [diff] [blame] | 1541 | #define IXGBE_AUTOC_ASM_PAUSE 0x20000000 |
| 1542 | #define IXGBE_AUTOC_SYM_PAUSE 0x10000000 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1543 | #define IXGBE_AUTOC_RF 0x08000000 |
| 1544 | #define IXGBE_AUTOC_PD_TMR 0x06000000 |
| 1545 | #define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000 |
| 1546 | #define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000 |
| 1547 | #define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000 |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1548 | #define IXGBE_AUTOC_FECA 0x00040000 |
| 1549 | #define IXGBE_AUTOC_FECR 0x00020000 |
| 1550 | #define IXGBE_AUTOC_KR_SUPP 0x00010000 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1551 | #define IXGBE_AUTOC_AN_RESTART 0x00001000 |
| 1552 | #define IXGBE_AUTOC_FLU 0x00000001 |
| 1553 | #define IXGBE_AUTOC_LMS_SHIFT 13 |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1554 | #define IXGBE_AUTOC_LMS_10G_SERIAL (0x3 << IXGBE_AUTOC_LMS_SHIFT) |
| 1555 | #define IXGBE_AUTOC_LMS_KX4_KX_KR (0x4 << IXGBE_AUTOC_LMS_SHIFT) |
| 1556 | #define IXGBE_AUTOC_LMS_SGMII_1G_100M (0x5 << IXGBE_AUTOC_LMS_SHIFT) |
| 1557 | #define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT) |
| 1558 | #define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT) |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1559 | #define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT) |
| 1560 | #define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT) |
| 1561 | #define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT) |
| 1562 | #define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT) |
| 1563 | #define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT) |
| 1564 | #define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT) |
| 1565 | #define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1566 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1567 | #define IXGBE_AUTOC_1G_PMA_PMD_MASK 0x00000200 |
| 1568 | #define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9 |
| 1569 | #define IXGBE_AUTOC_10G_PMA_PMD_MASK 0x00000180 |
| 1570 | #define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1571 | #define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) |
| 1572 | #define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) |
| 1573 | #define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) |
| 1574 | #define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) |
| 1575 | #define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1576 | #define IXGBE_AUTOC_1G_SFI (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) |
| 1577 | #define IXGBE_AUTOC_1G_KX_BX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) |
| 1578 | |
| 1579 | #define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000 |
| 1580 | #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK 0x00030000 |
| 1581 | #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16 |
| 1582 | #define IXGBE_AUTOC2_10G_KR (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) |
| 1583 | #define IXGBE_AUTOC2_10G_XFI (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) |
| 1584 | #define IXGBE_AUTOC2_10G_SFI (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1585 | |
Emil Tantilov | 83dfde4 | 2011-03-31 09:36:24 +0000 | [diff] [blame] | 1586 | #define IXGBE_MACC_FLU 0x00000001 |
| 1587 | #define IXGBE_MACC_FSV_10G 0x00030000 |
| 1588 | #define IXGBE_MACC_FS 0x00040000 |
| 1589 | #define IXGBE_MAC_RX2TX_LPBK 0x00000002 |
| 1590 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1591 | /* LINKS Bit Masks */ |
| 1592 | #define IXGBE_LINKS_KX_AN_COMP 0x80000000 |
| 1593 | #define IXGBE_LINKS_UP 0x40000000 |
| 1594 | #define IXGBE_LINKS_SPEED 0x20000000 |
| 1595 | #define IXGBE_LINKS_MODE 0x18000000 |
| 1596 | #define IXGBE_LINKS_RX_MODE 0x06000000 |
| 1597 | #define IXGBE_LINKS_TX_MODE 0x01800000 |
| 1598 | #define IXGBE_LINKS_XGXS_EN 0x00400000 |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1599 | #define IXGBE_LINKS_SGMII_EN 0x02000000 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1600 | #define IXGBE_LINKS_PCS_1G_EN 0x00200000 |
| 1601 | #define IXGBE_LINKS_1G_AN_EN 0x00100000 |
| 1602 | #define IXGBE_LINKS_KX_AN_IDLE 0x00080000 |
| 1603 | #define IXGBE_LINKS_1G_SYNC 0x00040000 |
| 1604 | #define IXGBE_LINKS_10G_ALIGN 0x00020000 |
| 1605 | #define IXGBE_LINKS_10G_LANE_SYNC 0x00017000 |
| 1606 | #define IXGBE_LINKS_TL_FAULT 0x00001000 |
| 1607 | #define IXGBE_LINKS_SIGNAL 0x00000F00 |
| 1608 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1609 | #define IXGBE_LINKS_SPEED_82599 0x30000000 |
| 1610 | #define IXGBE_LINKS_SPEED_10G_82599 0x30000000 |
| 1611 | #define IXGBE_LINKS_SPEED_1G_82599 0x20000000 |
| 1612 | #define IXGBE_LINKS_SPEED_100_82599 0x10000000 |
Jesse Brandeburg | cf8280e | 2008-09-11 19:55:32 -0700 | [diff] [blame] | 1613 | #define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1614 | #define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */ |
| 1615 | |
Peter P Waskiewicz Jr | 539e5f0 | 2009-09-30 12:07:38 +0000 | [diff] [blame] | 1616 | #define IXGBE_LINKS2_AN_SUPPORTED 0x00000040 |
| 1617 | |
Peter P Waskiewicz Jr | 0ecc061 | 2009-02-06 21:46:54 -0800 | [diff] [blame] | 1618 | /* PCS1GLSTA Bit Masks */ |
| 1619 | #define IXGBE_PCS1GLSTA_LINK_OK 1 |
| 1620 | #define IXGBE_PCS1GLSTA_SYNK_OK 0x10 |
| 1621 | #define IXGBE_PCS1GLSTA_AN_COMPLETE 0x10000 |
| 1622 | #define IXGBE_PCS1GLSTA_AN_PAGE_RX 0x20000 |
| 1623 | #define IXGBE_PCS1GLSTA_AN_TIMED_OUT 0x40000 |
| 1624 | #define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000 |
| 1625 | #define IXGBE_PCS1GLSTA_AN_ERROR_RWS 0x100000 |
| 1626 | |
| 1627 | #define IXGBE_PCS1GANA_SYM_PAUSE 0x80 |
| 1628 | #define IXGBE_PCS1GANA_ASM_PAUSE 0x100 |
| 1629 | |
| 1630 | /* PCS1GLCTL Bit Masks */ |
| 1631 | #define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN 0x00040000 /* PCS 1G autoneg to en */ |
| 1632 | #define IXGBE_PCS1GLCTL_FLV_LINK_UP 1 |
| 1633 | #define IXGBE_PCS1GLCTL_FORCE_LINK 0x20 |
| 1634 | #define IXGBE_PCS1GLCTL_LOW_LINK_LATCH 0x40 |
| 1635 | #define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000 |
| 1636 | #define IXGBE_PCS1GLCTL_AN_RESTART 0x20000 |
| 1637 | |
Peter P Waskiewicz Jr | 539e5f0 | 2009-09-30 12:07:38 +0000 | [diff] [blame] | 1638 | /* ANLP1 Bit Masks */ |
| 1639 | #define IXGBE_ANLP1_PAUSE 0x0C00 |
| 1640 | #define IXGBE_ANLP1_SYM_PAUSE 0x0400 |
| 1641 | #define IXGBE_ANLP1_ASM_PAUSE 0x0800 |
Don Skidmore | a7f5a5f | 2010-12-03 13:23:30 +0000 | [diff] [blame] | 1642 | #define IXGBE_ANLP1_AN_STATE_MASK 0x000f0000 |
| 1643 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1644 | /* SW Semaphore Register bitmasks */ |
| 1645 | #define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ |
| 1646 | #define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ |
| 1647 | #define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ |
Mallikarjuna R Chilakala | 21ce849 | 2010-05-13 17:33:41 +0000 | [diff] [blame] | 1648 | #define IXGBE_SWFW_REGSMP 0x80000000 /* Register Semaphore bit 31 */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1649 | |
Mallikarjuna R Chilakala | 21ce849 | 2010-05-13 17:33:41 +0000 | [diff] [blame] | 1650 | /* SW_FW_SYNC/GSSR definitions */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1651 | #define IXGBE_GSSR_EEP_SM 0x0001 |
| 1652 | #define IXGBE_GSSR_PHY0_SM 0x0002 |
| 1653 | #define IXGBE_GSSR_PHY1_SM 0x0004 |
| 1654 | #define IXGBE_GSSR_MAC_CSR_SM 0x0008 |
| 1655 | #define IXGBE_GSSR_FLASH_SM 0x0010 |
Emil Tantilov | 83dfde4 | 2011-03-31 09:36:24 +0000 | [diff] [blame] | 1656 | #define IXGBE_GSSR_SW_MNG_SM 0x0400 |
| 1657 | |
| 1658 | /* FW Status register bitmask */ |
| 1659 | #define IXGBE_FWSTS_FWRI 0x00000200 /* Firmware Reset Indication */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1660 | |
| 1661 | /* EEC Register */ |
| 1662 | #define IXGBE_EEC_SK 0x00000001 /* EEPROM Clock */ |
| 1663 | #define IXGBE_EEC_CS 0x00000002 /* EEPROM Chip Select */ |
| 1664 | #define IXGBE_EEC_DI 0x00000004 /* EEPROM Data In */ |
| 1665 | #define IXGBE_EEC_DO 0x00000008 /* EEPROM Data Out */ |
| 1666 | #define IXGBE_EEC_FWE_MASK 0x00000030 /* FLASH Write Enable */ |
| 1667 | #define IXGBE_EEC_FWE_DIS 0x00000010 /* Disable FLASH writes */ |
| 1668 | #define IXGBE_EEC_FWE_EN 0x00000020 /* Enable FLASH writes */ |
| 1669 | #define IXGBE_EEC_FWE_SHIFT 4 |
| 1670 | #define IXGBE_EEC_REQ 0x00000040 /* EEPROM Access Request */ |
| 1671 | #define IXGBE_EEC_GNT 0x00000080 /* EEPROM Access Grant */ |
| 1672 | #define IXGBE_EEC_PRES 0x00000100 /* EEPROM Present */ |
| 1673 | #define IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */ |
Mallikarjuna R Chilakala | 21ce849 | 2010-05-13 17:33:41 +0000 | [diff] [blame] | 1674 | #define IXGBE_EEC_FLUP 0x00800000 /* Flash update command */ |
Don Skidmore | fe15e8e | 2010-11-16 19:27:16 -0800 | [diff] [blame] | 1675 | #define IXGBE_EEC_SEC1VAL 0x02000000 /* Sector 1 Valid */ |
Mallikarjuna R Chilakala | 21ce849 | 2010-05-13 17:33:41 +0000 | [diff] [blame] | 1676 | #define IXGBE_EEC_FLUDONE 0x04000000 /* Flash update done */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1677 | /* EEPROM Addressing bits based on type (0-small, 1-large) */ |
| 1678 | #define IXGBE_EEC_ADDR_SIZE 0x00000400 |
| 1679 | #define IXGBE_EEC_SIZE 0x00007800 /* EEPROM Size */ |
Emil Tantilov | 83dfde4 | 2011-03-31 09:36:24 +0000 | [diff] [blame] | 1680 | #define IXGBE_EERD_MAX_ADDR 0x00003FFF /* EERD alows 14 bits for addr. */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1681 | |
| 1682 | #define IXGBE_EEC_SIZE_SHIFT 11 |
| 1683 | #define IXGBE_EEPROM_WORD_SIZE_SHIFT 6 |
| 1684 | #define IXGBE_EEPROM_OPCODE_BITS 8 |
| 1685 | |
Don Skidmore | 289700db | 2010-12-03 03:32:58 +0000 | [diff] [blame] | 1686 | /* Part Number String Length */ |
| 1687 | #define IXGBE_PBANUM_LENGTH 11 |
| 1688 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1689 | /* Checksum and EEPROM pointers */ |
Don Skidmore | 289700db | 2010-12-03 03:32:58 +0000 | [diff] [blame] | 1690 | #define IXGBE_PBANUM_PTR_GUARD 0xFAFA |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1691 | #define IXGBE_EEPROM_CHECKSUM 0x3F |
| 1692 | #define IXGBE_EEPROM_SUM 0xBABA |
| 1693 | #define IXGBE_PCIE_ANALOG_PTR 0x03 |
| 1694 | #define IXGBE_ATLAS0_CONFIG_PTR 0x04 |
Don Skidmore | fe15e8e | 2010-11-16 19:27:16 -0800 | [diff] [blame] | 1695 | #define IXGBE_PHY_PTR 0x04 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1696 | #define IXGBE_ATLAS1_CONFIG_PTR 0x05 |
Don Skidmore | fe15e8e | 2010-11-16 19:27:16 -0800 | [diff] [blame] | 1697 | #define IXGBE_OPTION_ROM_PTR 0x05 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1698 | #define IXGBE_PCIE_GENERAL_PTR 0x06 |
| 1699 | #define IXGBE_PCIE_CONFIG0_PTR 0x07 |
| 1700 | #define IXGBE_PCIE_CONFIG1_PTR 0x08 |
| 1701 | #define IXGBE_CORE0_PTR 0x09 |
| 1702 | #define IXGBE_CORE1_PTR 0x0A |
| 1703 | #define IXGBE_MAC0_PTR 0x0B |
| 1704 | #define IXGBE_MAC1_PTR 0x0C |
| 1705 | #define IXGBE_CSR0_CONFIG_PTR 0x0D |
| 1706 | #define IXGBE_CSR1_CONFIG_PTR 0x0E |
| 1707 | #define IXGBE_FW_PTR 0x0F |
| 1708 | #define IXGBE_PBANUM0_PTR 0x15 |
| 1709 | #define IXGBE_PBANUM1_PTR 0x16 |
Emil Tantilov | 83dfde4 | 2011-03-31 09:36:24 +0000 | [diff] [blame] | 1710 | #define IXGBE_FREE_SPACE_PTR 0X3E |
Don Skidmore | e1ea915 | 2012-02-17 02:38:58 +0000 | [diff] [blame] | 1711 | |
| 1712 | /* External Thermal Sensor Config */ |
| 1713 | #define IXGBE_ETS_CFG 0x26 |
| 1714 | #define IXGBE_ETS_LTHRES_DELTA_MASK 0x07C0 |
| 1715 | #define IXGBE_ETS_LTHRES_DELTA_SHIFT 6 |
| 1716 | #define IXGBE_ETS_TYPE_MASK 0x0038 |
| 1717 | #define IXGBE_ETS_TYPE_SHIFT 3 |
| 1718 | #define IXGBE_ETS_TYPE_EMC 0x000 |
| 1719 | #define IXGBE_ETS_TYPE_EMC_SHIFTED 0x000 |
| 1720 | #define IXGBE_ETS_NUM_SENSORS_MASK 0x0007 |
| 1721 | #define IXGBE_ETS_DATA_LOC_MASK 0x3C00 |
| 1722 | #define IXGBE_ETS_DATA_LOC_SHIFT 10 |
| 1723 | #define IXGBE_ETS_DATA_INDEX_MASK 0x0300 |
| 1724 | #define IXGBE_ETS_DATA_INDEX_SHIFT 8 |
| 1725 | #define IXGBE_ETS_DATA_HTHRESH_MASK 0x00FF |
| 1726 | |
PJ Waskiewicz | 0365e6e | 2009-05-17 12:32:25 +0000 | [diff] [blame] | 1727 | #define IXGBE_SAN_MAC_ADDR_PTR 0x28 |
Emil Tantilov | 83dfde4 | 2011-03-31 09:36:24 +0000 | [diff] [blame] | 1728 | #define IXGBE_DEVICE_CAPS 0x2C |
| 1729 | #define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11 |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1730 | #define IXGBE_PCIE_MSIX_82599_CAPS 0x72 |
Emil Tantilov | 7116130 | 2012-03-22 03:00:29 +0000 | [diff] [blame] | 1731 | #define IXGBE_MAX_MSIX_VECTORS_82599 0x40 |
Peter P Waskiewicz Jr | eb7f139 | 2009-02-01 01:18:58 -0800 | [diff] [blame] | 1732 | #define IXGBE_PCIE_MSIX_82598_CAPS 0x62 |
Emil Tantilov | 7116130 | 2012-03-22 03:00:29 +0000 | [diff] [blame] | 1733 | #define IXGBE_MAX_MSIX_VECTORS_82598 0x13 |
Peter P Waskiewicz Jr | eb7f139 | 2009-02-01 01:18:58 -0800 | [diff] [blame] | 1734 | |
| 1735 | /* MSI-X capability fields masks */ |
| 1736 | #define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1737 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1738 | /* Legacy EEPROM word offsets */ |
| 1739 | #define IXGBE_ISCSI_BOOT_CAPS 0x0033 |
| 1740 | #define IXGBE_ISCSI_SETUP_PORT_0 0x0030 |
| 1741 | #define IXGBE_ISCSI_SETUP_PORT_1 0x0034 |
| 1742 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1743 | /* EEPROM Commands - SPI */ |
| 1744 | #define IXGBE_EEPROM_MAX_RETRY_SPI 5000 /* Max wait 5ms for RDY signal */ |
| 1745 | #define IXGBE_EEPROM_STATUS_RDY_SPI 0x01 |
| 1746 | #define IXGBE_EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */ |
| 1747 | #define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */ |
| 1748 | #define IXGBE_EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = addr bit-8 */ |
| 1749 | #define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Ena latch */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1750 | /* EEPROM reset Write Enable latch */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1751 | #define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04 |
| 1752 | #define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status reg */ |
| 1753 | #define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status reg */ |
| 1754 | #define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */ |
| 1755 | #define IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */ |
| 1756 | #define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */ |
| 1757 | |
| 1758 | /* EEPROM Read Register */ |
Mallikarjuna R Chilakala | 21ce849 | 2010-05-13 17:33:41 +0000 | [diff] [blame] | 1759 | #define IXGBE_EEPROM_RW_REG_DATA 16 /* data offset in EEPROM read reg */ |
| 1760 | #define IXGBE_EEPROM_RW_REG_DONE 2 /* Offset to READ done bit */ |
| 1761 | #define IXGBE_EEPROM_RW_REG_START 1 /* First bit to start operation */ |
| 1762 | #define IXGBE_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ |
| 1763 | #define IXGBE_NVM_POLL_WRITE 1 /* Flag for polling for write complete */ |
| 1764 | #define IXGBE_NVM_POLL_READ 0 /* Flag for polling for read complete */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1765 | |
Emil Tantilov | 68c7005 | 2011-04-20 08:49:06 +0000 | [diff] [blame] | 1766 | #define IXGBE_EEPROM_PAGE_SIZE_MAX 128 |
| 1767 | #define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT 512 /* EEPROM words # read in burst */ |
| 1768 | #define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT 256 /* EEPROM words # wr in burst */ |
| 1769 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1770 | #ifndef IXGBE_EEPROM_GRANT_ATTEMPTS |
| 1771 | #define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */ |
| 1772 | #endif |
| 1773 | |
Mallikarjuna R Chilakala | 21ce849 | 2010-05-13 17:33:41 +0000 | [diff] [blame] | 1774 | #ifndef IXGBE_EERD_EEWR_ATTEMPTS |
| 1775 | /* Number of 5 microseconds we wait for EERD read and |
| 1776 | * EERW write to complete */ |
| 1777 | #define IXGBE_EERD_EEWR_ATTEMPTS 100000 |
| 1778 | #endif |
| 1779 | |
| 1780 | #ifndef IXGBE_FLUDONE_ATTEMPTS |
| 1781 | /* # attempts we wait for flush update to complete */ |
| 1782 | #define IXGBE_FLUDONE_ATTEMPTS 20000 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1783 | #endif |
| 1784 | |
Emil Tantilov | c913018 | 2011-03-16 01:55:55 +0000 | [diff] [blame] | 1785 | #define IXGBE_PCIE_CTRL2 0x5 /* PCIe Control 2 Offset */ |
| 1786 | #define IXGBE_PCIE_CTRL2_DUMMY_ENABLE 0x8 /* Dummy Function Enable */ |
| 1787 | #define IXGBE_PCIE_CTRL2_LAN_DISABLE 0x2 /* LAN PCI Disable */ |
| 1788 | #define IXGBE_PCIE_CTRL2_DISABLE_SELECT 0x1 /* LAN Disable Select */ |
| 1789 | |
PJ Waskiewicz | 0365e6e | 2009-05-17 12:32:25 +0000 | [diff] [blame] | 1790 | #define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0 |
| 1791 | #define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3 |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1792 | #define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1 |
Yi Zou | eacd73f | 2009-05-13 13:11:06 +0000 | [diff] [blame] | 1793 | #define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS 0x2 |
Emil Tantilov | 0fa6d83 | 2011-03-18 08:18:32 +0000 | [diff] [blame] | 1794 | #define IXGBE_FW_LESM_PARAMETERS_PTR 0x2 |
| 1795 | #define IXGBE_FW_LESM_STATE_1 0x1 |
| 1796 | #define IXGBE_FW_LESM_STATE_ENABLED 0x8000 /* LESM Enable bit */ |
Peter P Waskiewicz Jr | 794caeb | 2009-06-04 16:02:24 +0000 | [diff] [blame] | 1797 | #define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4 |
Emil Tantilov | 83dfde4 | 2011-03-31 09:36:24 +0000 | [diff] [blame] | 1798 | #define IXGBE_FW_PATCH_VERSION_4 0x7 |
| 1799 | #define IXGBE_FCOE_IBA_CAPS_BLK_PTR 0x33 /* iSCSI/FCOE block */ |
| 1800 | #define IXGBE_FCOE_IBA_CAPS_FCOE 0x20 /* FCOE flags */ |
| 1801 | #define IXGBE_ISCSI_FCOE_BLK_PTR 0x17 /* iSCSI/FCOE block */ |
| 1802 | #define IXGBE_ISCSI_FCOE_FLAGS_OFFSET 0x0 /* FCOE flags */ |
| 1803 | #define IXGBE_ISCSI_FCOE_FLAGS_ENABLE 0x1 /* FCOE flags enable bit */ |
Yi Zou | 383ff34 | 2009-10-28 18:23:57 +0000 | [diff] [blame] | 1804 | #define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR 0x27 /* Alt. SAN MAC block */ |
| 1805 | #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET 0x0 /* Alt. SAN MAC capability */ |
| 1806 | #define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt. SAN MAC 0 offset */ |
| 1807 | #define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4 /* Alt. SAN MAC 1 offset */ |
| 1808 | #define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET 0x7 /* Alt. WWNN prefix offset */ |
| 1809 | #define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET 0x8 /* Alt. WWPN prefix offset */ |
| 1810 | #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC 0x0 /* Alt. SAN MAC exists */ |
| 1811 | #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1 /* Alt. WWN base exists */ |
| 1812 | |
Emil Tantilov | c23f5b6 | 2011-08-16 07:34:18 +0000 | [diff] [blame] | 1813 | #define IXGBE_DEVICE_CAPS_WOL_PORT0_1 0x4 /* WoL supported on ports 0 & 1 */ |
| 1814 | #define IXGBE_DEVICE_CAPS_WOL_PORT0 0x8 /* WoL supported on port 0 */ |
| 1815 | #define IXGBE_DEVICE_CAPS_WOL_MASK 0xC /* Mask for WoL capabilities */ |
| 1816 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1817 | /* PCI Bus Info */ |
Emil Tantilov | a4297dc | 2011-02-14 08:45:13 +0000 | [diff] [blame] | 1818 | #define IXGBE_PCI_DEVICE_STATUS 0xAA |
| 1819 | #define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING 0x0020 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1820 | #define IXGBE_PCI_LINK_STATUS 0xB2 |
Mallikarjuna R Chilakala | 202ff1e | 2009-08-03 07:20:38 +0000 | [diff] [blame] | 1821 | #define IXGBE_PCI_DEVICE_CONTROL2 0xC8 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1822 | #define IXGBE_PCI_LINK_WIDTH 0x3F0 |
| 1823 | #define IXGBE_PCI_LINK_WIDTH_1 0x10 |
| 1824 | #define IXGBE_PCI_LINK_WIDTH_2 0x20 |
| 1825 | #define IXGBE_PCI_LINK_WIDTH_4 0x40 |
| 1826 | #define IXGBE_PCI_LINK_WIDTH_8 0x80 |
| 1827 | #define IXGBE_PCI_LINK_SPEED 0xF |
| 1828 | #define IXGBE_PCI_LINK_SPEED_2500 0x1 |
| 1829 | #define IXGBE_PCI_LINK_SPEED_5000 0x2 |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1830 | #define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E |
| 1831 | #define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80 |
Mallikarjuna R Chilakala | 202ff1e | 2009-08-03 07:20:38 +0000 | [diff] [blame] | 1832 | #define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1833 | |
| 1834 | /* Number of 100 microseconds we wait for PCI Express master disable */ |
| 1835 | #define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800 |
| 1836 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1837 | /* RAH */ |
| 1838 | #define IXGBE_RAH_VIND_MASK 0x003C0000 |
| 1839 | #define IXGBE_RAH_VIND_SHIFT 18 |
| 1840 | #define IXGBE_RAH_AV 0x80000000 |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1841 | #define IXGBE_CLEAR_VMDQ_ALL 0xFFFFFFFF |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1842 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1843 | /* Header split receive */ |
| 1844 | #define IXGBE_RFCTL_ISCSI_DIS 0x00000001 |
| 1845 | #define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E |
| 1846 | #define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1 |
| 1847 | #define IXGBE_RFCTL_NFSW_DIS 0x00000040 |
| 1848 | #define IXGBE_RFCTL_NFSR_DIS 0x00000080 |
| 1849 | #define IXGBE_RFCTL_NFS_VER_MASK 0x00000300 |
| 1850 | #define IXGBE_RFCTL_NFS_VER_SHIFT 8 |
| 1851 | #define IXGBE_RFCTL_NFS_VER_2 0 |
| 1852 | #define IXGBE_RFCTL_NFS_VER_3 1 |
| 1853 | #define IXGBE_RFCTL_NFS_VER_4 2 |
| 1854 | #define IXGBE_RFCTL_IPV6_DIS 0x00000400 |
| 1855 | #define IXGBE_RFCTL_IPV6_XSUM_DIS 0x00000800 |
| 1856 | #define IXGBE_RFCTL_IPFRSP_DIS 0x00004000 |
| 1857 | #define IXGBE_RFCTL_IPV6_EX_DIS 0x00010000 |
| 1858 | #define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 |
| 1859 | |
| 1860 | /* Transmit Config masks */ |
| 1861 | #define IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */ |
| 1862 | #define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */ |
Emil Tantilov | 83dfde4 | 2011-03-31 09:36:24 +0000 | [diff] [blame] | 1863 | #define IXGBE_TXDCTL_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1864 | /* Enable short packet padding to 64 bytes */ |
| 1865 | #define IXGBE_TX_PAD_ENABLE 0x00000400 |
| 1866 | #define IXGBE_JUMBO_FRAME_ENABLE 0x00000004 /* Allow jumbo frames */ |
| 1867 | /* This allows for 16K packets + 4k for vlan */ |
| 1868 | #define IXGBE_MAX_FRAME_SZ 0x40040000 |
| 1869 | |
| 1870 | #define IXGBE_TDWBAL_HEAD_WB_ENABLE 0x1 /* Tx head write-back enable */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1871 | #define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2 /* Tx seq# write-back enable */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1872 | |
| 1873 | /* Receive Config masks */ |
| 1874 | #define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */ |
| 1875 | #define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */ |
| 1876 | #define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */ |
Emil Tantilov | ff9d1a5 | 2011-08-16 04:35:11 +0000 | [diff] [blame] | 1877 | #define IXGBE_RXDCTL_SWFLSH 0x04000000 /* Rx Desc. write-back flushing */ |
Greg Rose | e9f9807 | 2011-01-26 01:06:07 +0000 | [diff] [blame] | 1878 | #define IXGBE_RXDCTL_RLPMLMASK 0x00003FFF /* Only supported on the X540 */ |
| 1879 | #define IXGBE_RXDCTL_RLPML_EN 0x00008000 |
Emil Tantilov | 83dfde4 | 2011-03-31 09:36:24 +0000 | [diff] [blame] | 1880 | #define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1881 | |
Jacob E Keller | 681ae1a | 2012-05-01 05:24:41 +0000 | [diff] [blame] | 1882 | #define IXGBE_TSAUXC_EN_CLK 0x00000004 |
| 1883 | #define IXGBE_TSAUXC_SYNCLK 0x00000008 |
| 1884 | #define IXGBE_TSAUXC_SDP0_INT 0x00000040 |
| 1885 | |
Jacob Keller | 3a6a4ed | 2012-05-01 05:24:58 +0000 | [diff] [blame] | 1886 | #define IXGBE_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */ |
| 1887 | #define IXGBE_TSYNCTXCTL_ENABLED 0x00000010 /* Tx timestamping enabled */ |
| 1888 | |
| 1889 | #define IXGBE_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */ |
| 1890 | #define IXGBE_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */ |
| 1891 | #define IXGBE_TSYNCRXCTL_TYPE_L2_V2 0x00 |
| 1892 | #define IXGBE_TSYNCRXCTL_TYPE_L4_V1 0x02 |
| 1893 | #define IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 |
| 1894 | #define IXGBE_TSYNCRXCTL_TYPE_EVENT_V2 0x0A |
| 1895 | #define IXGBE_TSYNCRXCTL_ENABLED 0x00000010 /* Rx Timestamping enabled */ |
| 1896 | |
| 1897 | #define IXGBE_RXMTRL_V1_CTRLT_MASK 0x000000FF |
| 1898 | #define IXGBE_RXMTRL_V1_SYNC_MSG 0x00 |
| 1899 | #define IXGBE_RXMTRL_V1_DELAY_REQ_MSG 0x01 |
| 1900 | #define IXGBE_RXMTRL_V1_FOLLOWUP_MSG 0x02 |
| 1901 | #define IXGBE_RXMTRL_V1_DELAY_RESP_MSG 0x03 |
| 1902 | #define IXGBE_RXMTRL_V1_MGMT_MSG 0x04 |
| 1903 | |
| 1904 | #define IXGBE_RXMTRL_V2_MSGID_MASK 0x0000FF00 |
| 1905 | #define IXGBE_RXMTRL_V2_SYNC_MSG 0x0000 |
| 1906 | #define IXGBE_RXMTRL_V2_DELAY_REQ_MSG 0x0100 |
| 1907 | #define IXGBE_RXMTRL_V2_PDELAY_REQ_MSG 0x0200 |
| 1908 | #define IXGBE_RXMTRL_V2_PDELAY_RESP_MSG 0x0300 |
| 1909 | #define IXGBE_RXMTRL_V2_FOLLOWUP_MSG 0x0800 |
| 1910 | #define IXGBE_RXMTRL_V2_DELAY_RESP_MSG 0x0900 |
| 1911 | #define IXGBE_RXMTRL_V2_PDELAY_FOLLOWUP_MSG 0x0A00 |
| 1912 | #define IXGBE_RXMTRL_V2_ANNOUNCE_MSG 0x0B00 |
| 1913 | #define IXGBE_RXMTRL_V2_SIGNALING_MSG 0x0C00 |
| 1914 | #define IXGBE_RXMTRL_V2_MGMT_MSG 0x0D00 |
| 1915 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1916 | #define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */ |
| 1917 | #define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/ |
| 1918 | #define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */ |
| 1919 | #define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */ |
| 1920 | #define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */ |
| 1921 | #define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1922 | /* Receive Priority Flow Control Enable */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1923 | #define IXGBE_FCTRL_RPFCE 0x00004000 |
| 1924 | #define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1925 | #define IXGBE_MFLCN_PMCF 0x00000001 /* Pass MAC Control Frames */ |
| 1926 | #define IXGBE_MFLCN_DPF 0x00000002 /* Discard Pause Frame */ |
| 1927 | #define IXGBE_MFLCN_RPFCE 0x00000004 /* Receive Priority FC Enable */ |
| 1928 | #define IXGBE_MFLCN_RFCE 0x00000008 /* Receive FC Enable */ |
Alexander Duyck | 041441d | 2012-04-19 17:48:48 +0000 | [diff] [blame] | 1929 | #define IXGBE_MFLCN_RPFCE_MASK 0x00000FF4 /* Receive FC Mask */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1930 | |
John Fastabend | 45a5f72 | 2011-04-04 04:29:46 +0000 | [diff] [blame] | 1931 | #define IXGBE_MFLCN_RPFCE_SHIFT 4 |
| 1932 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1933 | /* Multiple Receive Queue Control */ |
| 1934 | #define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1935 | #define IXGBE_MRQC_MRQE_MASK 0xF /* Bits 3:0 */ |
| 1936 | #define IXGBE_MRQC_RT8TCEN 0x00000002 /* 8 TC no RSS */ |
| 1937 | #define IXGBE_MRQC_RT4TCEN 0x00000003 /* 4 TC no RSS */ |
| 1938 | #define IXGBE_MRQC_RTRSS8TCEN 0x00000004 /* 8 TC w/ RSS */ |
| 1939 | #define IXGBE_MRQC_RTRSS4TCEN 0x00000005 /* 4 TC w/ RSS */ |
| 1940 | #define IXGBE_MRQC_VMDQEN 0x00000008 /* VMDq2 64 pools no RSS */ |
| 1941 | #define IXGBE_MRQC_VMDQRSS32EN 0x0000000A /* VMDq2 32 pools w/ RSS */ |
| 1942 | #define IXGBE_MRQC_VMDQRSS64EN 0x0000000B /* VMDq2 64 pools w/ RSS */ |
| 1943 | #define IXGBE_MRQC_VMDQRT8TCEN 0x0000000C /* VMDq2/RT 16 pool 8 TC */ |
| 1944 | #define IXGBE_MRQC_VMDQRT4TCEN 0x0000000D /* VMDq2/RT 32 pool 4 TC */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1945 | #define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000 |
| 1946 | #define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 |
| 1947 | #define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000 |
| 1948 | #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000 |
| 1949 | #define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000 |
| 1950 | #define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000 |
| 1951 | #define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 |
| 1952 | #define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 |
| 1953 | #define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 |
| 1954 | #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000 |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1955 | #define IXGBE_MRQC_L3L4TXSWEN 0x00008000 |
| 1956 | |
Jacob Keller | cb6d0f5 | 2012-12-04 06:03:14 +0000 | [diff] [blame] | 1957 | #define IXGBE_FWSM_TS_ENABLED 0x1 |
| 1958 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1959 | /* Queue Drop Enable */ |
| 1960 | #define IXGBE_QDE_ENABLE 0x00000001 |
| 1961 | #define IXGBE_QDE_IDX_MASK 0x00007F00 |
| 1962 | #define IXGBE_QDE_IDX_SHIFT 8 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1963 | |
| 1964 | #define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ |
| 1965 | #define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ |
| 1966 | #define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */ |
| 1967 | #define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ |
| 1968 | #define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */ |
| 1969 | #define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */ |
| 1970 | #define IXGBE_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ |
| 1971 | #define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ |
| 1972 | #define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */ |
| 1973 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1974 | #define IXGBE_RXDADV_IPSEC_STATUS_SECP 0x00020000 |
| 1975 | #define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000 |
| 1976 | #define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000 |
| 1977 | #define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED 0x18000000 |
| 1978 | #define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000 |
| 1979 | /* Multiple Transmit Queue Command Register */ |
| 1980 | #define IXGBE_MTQC_RT_ENA 0x1 /* DCB Enable */ |
| 1981 | #define IXGBE_MTQC_VT_ENA 0x2 /* VMDQ2 Enable */ |
| 1982 | #define IXGBE_MTQC_64Q_1PB 0x0 /* 64 queues 1 pack buffer */ |
Don Skidmore | d988ead | 2009-04-09 22:26:40 +0000 | [diff] [blame] | 1983 | #define IXGBE_MTQC_32VF 0x8 /* 4 TX Queues per pool w/32VF's */ |
| 1984 | #define IXGBE_MTQC_64VF 0x4 /* 2 TX Queues per pool w/64VF's */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1985 | #define IXGBE_MTQC_8TC_8TQ 0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */ |
John Fastabend | 8b1c0b2 | 2011-05-03 02:26:48 +0000 | [diff] [blame] | 1986 | #define IXGBE_MTQC_4TC_4TQ 0x8 /* 4 TC if RT_ENA or 4 TQ if VT_ENA */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1987 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1988 | /* Receive Descriptor bit definitions */ |
| 1989 | #define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */ |
| 1990 | #define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1991 | #define IXGBE_RXD_STAT_FLM 0x04 /* FDir Match */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1992 | #define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1993 | #define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */ |
| 1994 | #define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004 |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1995 | #define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1996 | #define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */ |
| 1997 | #define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ |
| 1998 | #define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */ |
| 1999 | #define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */ |
| 2000 | #define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */ |
| 2001 | #define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ |
| 2002 | #define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2003 | #define IXGBE_RXD_STAT_LLINT 0x800 /* Pkt caused Low Latency Interrupt */ |
| 2004 | #define IXGBE_RXD_STAT_TS 0x10000 /* Time Stamp */ |
| 2005 | #define IXGBE_RXD_STAT_SECP 0x20000 /* Security Processing */ |
| 2006 | #define IXGBE_RXD_STAT_LB 0x40000 /* Loopback Status */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2007 | #define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ |
| 2008 | #define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */ |
| 2009 | #define IXGBE_RXD_ERR_LE 0x02 /* Length Error */ |
| 2010 | #define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */ |
| 2011 | #define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */ |
| 2012 | #define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */ |
| 2013 | #define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */ |
| 2014 | #define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2015 | #define IXGBE_RXDADV_ERR_MASK 0xfff00000 /* RDESC.ERRORS mask */ |
| 2016 | #define IXGBE_RXDADV_ERR_SHIFT 20 /* RDESC.ERRORS shift */ |
Yi Zou | bff6617 | 2009-05-13 13:09:39 +0000 | [diff] [blame] | 2017 | #define IXGBE_RXDADV_ERR_FCEOFE 0x80000000 /* FCoEFe/IPE */ |
| 2018 | #define IXGBE_RXDADV_ERR_FCERR 0x00700000 /* FCERR/FDIRERR */ |
Peter P Waskiewicz Jr | bfde493 | 2009-06-04 16:01:06 +0000 | [diff] [blame] | 2019 | #define IXGBE_RXDADV_ERR_FDIR_LEN 0x00100000 /* FDIR Length error */ |
| 2020 | #define IXGBE_RXDADV_ERR_FDIR_DROP 0x00200000 /* FDIR Drop error */ |
| 2021 | #define IXGBE_RXDADV_ERR_FDIR_COLL 0x00400000 /* FDIR Collision error */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2022 | #define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2023 | #define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */ |
| 2024 | #define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */ |
| 2025 | #define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */ |
| 2026 | #define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */ |
| 2027 | #define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */ |
| 2028 | #define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */ |
| 2029 | #define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */ |
| 2030 | #define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ |
| 2031 | #define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ |
| 2032 | #define IXGBE_RXD_PRI_SHIFT 13 |
| 2033 | #define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */ |
| 2034 | #define IXGBE_RXD_CFI_SHIFT 12 |
| 2035 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2036 | #define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD /* Done */ |
| 2037 | #define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP /* End of Packet */ |
| 2038 | #define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM /* FDir Match */ |
| 2039 | #define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP /* IEEE VLAN Pkt */ |
| 2040 | #define IXGBE_RXDADV_STAT_MASK 0x000fffff /* Stat/NEXTP: bit 0-19 */ |
Yi Zou | bff6617 | 2009-05-13 13:09:39 +0000 | [diff] [blame] | 2041 | #define IXGBE_RXDADV_STAT_FCEOFS 0x00000040 /* FCoE EOF/SOF Stat */ |
| 2042 | #define IXGBE_RXDADV_STAT_FCSTAT 0x00000030 /* FCoE Pkt Stat */ |
| 2043 | #define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */ |
| 2044 | #define IXGBE_RXDADV_STAT_FCSTAT_NODDP 0x00000010 /* 01: Ctxt w/o DDP */ |
| 2045 | #define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */ |
| 2046 | #define IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030 /* 11: Ctxt w/ DDP */ |
Jacob Keller | 3a6a4ed | 2012-05-01 05:24:58 +0000 | [diff] [blame] | 2047 | #define IXGBE_RXDADV_STAT_TS 0x00010000 /* IEEE 1588 Time Stamp */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2048 | |
| 2049 | /* PSRTYPE bit definitions */ |
| 2050 | #define IXGBE_PSRTYPE_TCPHDR 0x00000010 |
| 2051 | #define IXGBE_PSRTYPE_UDPHDR 0x00000020 |
| 2052 | #define IXGBE_PSRTYPE_IPV4HDR 0x00000100 |
| 2053 | #define IXGBE_PSRTYPE_IPV6HDR 0x00000200 |
Yi Zou | dfa12f0 | 2009-05-07 10:39:35 +0000 | [diff] [blame] | 2054 | #define IXGBE_PSRTYPE_L2HDR 0x00001000 |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2055 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2056 | /* SRRCTL bit definitions */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2057 | #define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2058 | #define IXGBE_SRRCTL_RDMTS_SHIFT 22 |
| 2059 | #define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000 |
| 2060 | #define IXGBE_SRRCTL_DROP_EN 0x10000000 |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2061 | #define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F |
| 2062 | #define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00 |
| 2063 | #define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2064 | #define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 |
| 2065 | #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 |
| 2066 | #define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 |
| 2067 | #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2068 | #define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2069 | |
| 2070 | #define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000 |
| 2071 | #define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF |
| 2072 | |
| 2073 | #define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F |
| 2074 | #define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0 |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2075 | #define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2076 | #define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0 |
Emil Tantilov | 83dfde4 | 2011-03-31 09:36:24 +0000 | [diff] [blame] | 2077 | #define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000 |
| 2078 | #define IXGBE_RXDADV_RSCCNT_SHIFT 17 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2079 | #define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5 |
| 2080 | #define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000 |
| 2081 | #define IXGBE_RXDADV_SPH 0x8000 |
| 2082 | |
| 2083 | /* RSS Hash results */ |
| 2084 | #define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000 |
| 2085 | #define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001 |
| 2086 | #define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002 |
| 2087 | #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003 |
| 2088 | #define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004 |
| 2089 | #define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005 |
| 2090 | #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006 |
| 2091 | #define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007 |
| 2092 | #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008 |
| 2093 | #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009 |
| 2094 | |
| 2095 | /* RSS Packet Types as indicated in the receive descriptor. */ |
| 2096 | #define IXGBE_RXDADV_PKTTYPE_NONE 0x00000000 |
| 2097 | #define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */ |
| 2098 | #define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPv4 hdr + extensions */ |
| 2099 | #define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */ |
| 2100 | #define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */ |
| 2101 | #define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */ |
| 2102 | #define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */ |
| 2103 | #define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */ |
| 2104 | #define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2105 | #define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */ |
| 2106 | #define IXGBE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */ |
| 2107 | #define IXGBE_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */ |
| 2108 | #define IXGBE_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */ |
| 2109 | #define IXGBE_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */ |
| 2110 | #define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */ |
| 2111 | |
| 2112 | /* Security Processing bit Indication */ |
| 2113 | #define IXGBE_RXDADV_LNKSEC_STATUS_SECP 0x00020000 |
| 2114 | #define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000 |
| 2115 | #define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000 |
| 2116 | #define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000 |
| 2117 | #define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000 |
| 2118 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2119 | /* Masks to determine if packets should be dropped due to frame errors */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2120 | #define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \ |
| 2121 | IXGBE_RXD_ERR_CE | \ |
| 2122 | IXGBE_RXD_ERR_LE | \ |
| 2123 | IXGBE_RXD_ERR_PE | \ |
| 2124 | IXGBE_RXD_ERR_OSE | \ |
| 2125 | IXGBE_RXD_ERR_USE) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2126 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2127 | #define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \ |
| 2128 | IXGBE_RXDADV_ERR_CE | \ |
| 2129 | IXGBE_RXDADV_ERR_LE | \ |
| 2130 | IXGBE_RXDADV_ERR_PE | \ |
| 2131 | IXGBE_RXDADV_ERR_OSE | \ |
| 2132 | IXGBE_RXDADV_ERR_USE) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2133 | |
| 2134 | /* Multicast bit mask */ |
| 2135 | #define IXGBE_MCSTCTRL_MFE 0x4 |
| 2136 | |
| 2137 | /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ |
| 2138 | #define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8 |
| 2139 | #define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8 |
| 2140 | #define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024 |
| 2141 | |
| 2142 | /* Vlan-specific macros */ |
| 2143 | #define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */ |
| 2144 | #define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority in upper 3 bits */ |
| 2145 | #define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */ |
| 2146 | #define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT |
| 2147 | |
Greg Rose | 7f87047 | 2010-01-09 02:25:29 +0000 | [diff] [blame] | 2148 | /* SR-IOV specific macros */ |
| 2149 | #define IXGBE_MBVFICR_INDEX(vf_number) (vf_number >> 4) |
Alexander Duyck | 795be95 | 2012-01-18 22:13:30 +0000 | [diff] [blame] | 2150 | #define IXGBE_MBVFICR(_i) (0x00710 + ((_i) * 4)) |
| 2151 | #define IXGBE_VFLRE(_i) ((((_i) & 1) ? 0x001C0 : 0x00600)) |
| 2152 | #define IXGBE_VFLREC(_i) (0x00700 + ((_i) * 4)) |
Greg Rose | 7f87047 | 2010-01-09 02:25:29 +0000 | [diff] [blame] | 2153 | |
Peter P Waskiewicz Jr | bfde493 | 2009-06-04 16:01:06 +0000 | [diff] [blame] | 2154 | enum ixgbe_fdir_pballoc_type { |
Alexander Duyck | c04f6ca | 2011-05-11 07:18:36 +0000 | [diff] [blame] | 2155 | IXGBE_FDIR_PBALLOC_NONE = 0, |
| 2156 | IXGBE_FDIR_PBALLOC_64K = 1, |
| 2157 | IXGBE_FDIR_PBALLOC_128K = 2, |
| 2158 | IXGBE_FDIR_PBALLOC_256K = 3, |
Peter P Waskiewicz Jr | bfde493 | 2009-06-04 16:01:06 +0000 | [diff] [blame] | 2159 | }; |
| 2160 | #define IXGBE_FDIR_PBALLOC_SIZE_SHIFT 16 |
| 2161 | |
| 2162 | /* Flow Director register values */ |
| 2163 | #define IXGBE_FDIRCTRL_PBALLOC_64K 0x00000001 |
| 2164 | #define IXGBE_FDIRCTRL_PBALLOC_128K 0x00000002 |
| 2165 | #define IXGBE_FDIRCTRL_PBALLOC_256K 0x00000003 |
| 2166 | #define IXGBE_FDIRCTRL_INIT_DONE 0x00000008 |
| 2167 | #define IXGBE_FDIRCTRL_PERFECT_MATCH 0x00000010 |
| 2168 | #define IXGBE_FDIRCTRL_REPORT_STATUS 0x00000020 |
| 2169 | #define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS 0x00000080 |
| 2170 | #define IXGBE_FDIRCTRL_DROP_Q_SHIFT 8 |
| 2171 | #define IXGBE_FDIRCTRL_FLEX_SHIFT 16 |
| 2172 | #define IXGBE_FDIRCTRL_SEARCHLIM 0x00800000 |
| 2173 | #define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT 24 |
| 2174 | #define IXGBE_FDIRCTRL_FULL_THRESH_MASK 0xF0000000 |
| 2175 | #define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT 28 |
| 2176 | |
| 2177 | #define IXGBE_FDIRTCPM_DPORTM_SHIFT 16 |
| 2178 | #define IXGBE_FDIRUDPM_DPORTM_SHIFT 16 |
| 2179 | #define IXGBE_FDIRIP6M_DIPM_SHIFT 16 |
| 2180 | #define IXGBE_FDIRM_VLANID 0x00000001 |
| 2181 | #define IXGBE_FDIRM_VLANP 0x00000002 |
| 2182 | #define IXGBE_FDIRM_POOL 0x00000004 |
Alexander Duyck | 45b9f50 | 2011-01-06 14:29:59 +0000 | [diff] [blame] | 2183 | #define IXGBE_FDIRM_L4P 0x00000008 |
| 2184 | #define IXGBE_FDIRM_FLEX 0x00000010 |
| 2185 | #define IXGBE_FDIRM_DIPv6 0x00000020 |
Peter P Waskiewicz Jr | bfde493 | 2009-06-04 16:01:06 +0000 | [diff] [blame] | 2186 | |
| 2187 | #define IXGBE_FDIRFREE_FREE_MASK 0xFFFF |
| 2188 | #define IXGBE_FDIRFREE_FREE_SHIFT 0 |
| 2189 | #define IXGBE_FDIRFREE_COLL_MASK 0x7FFF0000 |
| 2190 | #define IXGBE_FDIRFREE_COLL_SHIFT 16 |
| 2191 | #define IXGBE_FDIRLEN_MAXLEN_MASK 0x3F |
| 2192 | #define IXGBE_FDIRLEN_MAXLEN_SHIFT 0 |
| 2193 | #define IXGBE_FDIRLEN_MAXHASH_MASK 0x7FFF0000 |
| 2194 | #define IXGBE_FDIRLEN_MAXHASH_SHIFT 16 |
| 2195 | #define IXGBE_FDIRUSTAT_ADD_MASK 0xFFFF |
| 2196 | #define IXGBE_FDIRUSTAT_ADD_SHIFT 0 |
| 2197 | #define IXGBE_FDIRUSTAT_REMOVE_MASK 0xFFFF0000 |
| 2198 | #define IXGBE_FDIRUSTAT_REMOVE_SHIFT 16 |
| 2199 | #define IXGBE_FDIRFSTAT_FADD_MASK 0x00FF |
| 2200 | #define IXGBE_FDIRFSTAT_FADD_SHIFT 0 |
| 2201 | #define IXGBE_FDIRFSTAT_FREMOVE_MASK 0xFF00 |
| 2202 | #define IXGBE_FDIRFSTAT_FREMOVE_SHIFT 8 |
| 2203 | #define IXGBE_FDIRPORT_DESTINATION_SHIFT 16 |
| 2204 | #define IXGBE_FDIRVLAN_FLEX_SHIFT 16 |
| 2205 | #define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT 15 |
| 2206 | #define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT 16 |
| 2207 | |
| 2208 | #define IXGBE_FDIRCMD_CMD_MASK 0x00000003 |
| 2209 | #define IXGBE_FDIRCMD_CMD_ADD_FLOW 0x00000001 |
| 2210 | #define IXGBE_FDIRCMD_CMD_REMOVE_FLOW 0x00000002 |
| 2211 | #define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT 0x00000003 |
Alexander Duyck | c04f6ca | 2011-05-11 07:18:36 +0000 | [diff] [blame] | 2212 | #define IXGBE_FDIRCMD_FILTER_VALID 0x00000004 |
Peter P Waskiewicz Jr | bfde493 | 2009-06-04 16:01:06 +0000 | [diff] [blame] | 2213 | #define IXGBE_FDIRCMD_FILTER_UPDATE 0x00000008 |
| 2214 | #define IXGBE_FDIRCMD_IPv6DMATCH 0x00000010 |
| 2215 | #define IXGBE_FDIRCMD_L4TYPE_UDP 0x00000020 |
| 2216 | #define IXGBE_FDIRCMD_L4TYPE_TCP 0x00000040 |
| 2217 | #define IXGBE_FDIRCMD_L4TYPE_SCTP 0x00000060 |
| 2218 | #define IXGBE_FDIRCMD_IPV6 0x00000080 |
| 2219 | #define IXGBE_FDIRCMD_CLEARHT 0x00000100 |
| 2220 | #define IXGBE_FDIRCMD_DROP 0x00000200 |
| 2221 | #define IXGBE_FDIRCMD_INT 0x00000400 |
| 2222 | #define IXGBE_FDIRCMD_LAST 0x00000800 |
| 2223 | #define IXGBE_FDIRCMD_COLLISION 0x00001000 |
| 2224 | #define IXGBE_FDIRCMD_QUEUE_EN 0x00008000 |
Alexander Duyck | 905e4a4 | 2011-01-06 14:29:57 +0000 | [diff] [blame] | 2225 | #define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT 5 |
Peter P Waskiewicz Jr | bfde493 | 2009-06-04 16:01:06 +0000 | [diff] [blame] | 2226 | #define IXGBE_FDIRCMD_RX_QUEUE_SHIFT 16 |
| 2227 | #define IXGBE_FDIRCMD_VT_POOL_SHIFT 24 |
| 2228 | #define IXGBE_FDIR_INIT_DONE_POLL 10 |
| 2229 | #define IXGBE_FDIRCMD_CMD_POLL 10 |
| 2230 | |
Alexander Duyck | c04f6ca | 2011-05-11 07:18:36 +0000 | [diff] [blame] | 2231 | #define IXGBE_FDIR_DROP_QUEUE 127 |
| 2232 | |
Emil Tantilov | 9612de9 | 2011-05-07 07:40:20 +0000 | [diff] [blame] | 2233 | /* Manageablility Host Interface defines */ |
| 2234 | #define IXGBE_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Num of bytes in range */ |
| 2235 | #define IXGBE_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Num of dwords in range */ |
| 2236 | #define IXGBE_HI_COMMAND_TIMEOUT 500 /* Process HI command limit */ |
| 2237 | |
| 2238 | /* CEM Support */ |
| 2239 | #define FW_CEM_HDR_LEN 0x4 |
| 2240 | #define FW_CEM_CMD_DRIVER_INFO 0xDD |
| 2241 | #define FW_CEM_CMD_DRIVER_INFO_LEN 0x5 |
Don Skidmore | a38a104 | 2011-05-20 03:05:14 +0000 | [diff] [blame] | 2242 | #define FW_CEM_CMD_RESERVED 0x0 |
| 2243 | #define FW_CEM_UNUSED_VER 0x0 |
Emil Tantilov | 9612de9 | 2011-05-07 07:40:20 +0000 | [diff] [blame] | 2244 | #define FW_CEM_MAX_RETRIES 3 |
| 2245 | #define FW_CEM_RESP_STATUS_SUCCESS 0x1 |
| 2246 | |
| 2247 | /* Host Interface Command Structures */ |
| 2248 | struct ixgbe_hic_hdr { |
| 2249 | u8 cmd; |
| 2250 | u8 buf_len; |
| 2251 | union { |
| 2252 | u8 cmd_resv; |
| 2253 | u8 ret_status; |
| 2254 | } cmd_or_resp; |
| 2255 | u8 checksum; |
| 2256 | }; |
| 2257 | |
| 2258 | struct ixgbe_hic_drv_info { |
| 2259 | struct ixgbe_hic_hdr hdr; |
| 2260 | u8 port_num; |
| 2261 | u8 ver_sub; |
| 2262 | u8 ver_build; |
| 2263 | u8 ver_min; |
| 2264 | u8 ver_maj; |
| 2265 | u8 pad; /* end spacing to ensure length is mult. of dword */ |
| 2266 | u16 pad2; /* end spacing to ensure length is mult. of dword2 */ |
| 2267 | }; |
| 2268 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2269 | /* Transmit Descriptor - Advanced */ |
| 2270 | union ixgbe_adv_tx_desc { |
| 2271 | struct { |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2272 | __le64 buffer_addr; /* Address of descriptor's data buf */ |
Al Viro | 8327d00 | 2007-12-10 18:54:12 +0000 | [diff] [blame] | 2273 | __le32 cmd_type_len; |
| 2274 | __le32 olinfo_status; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2275 | } read; |
| 2276 | struct { |
Al Viro | 8327d00 | 2007-12-10 18:54:12 +0000 | [diff] [blame] | 2277 | __le64 rsvd; /* Reserved */ |
| 2278 | __le32 nxtseq_seed; |
| 2279 | __le32 status; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2280 | } wb; |
| 2281 | }; |
| 2282 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2283 | /* Receive Descriptor - Advanced */ |
| 2284 | union ixgbe_adv_rx_desc { |
| 2285 | struct { |
Al Viro | 8327d00 | 2007-12-10 18:54:12 +0000 | [diff] [blame] | 2286 | __le64 pkt_addr; /* Packet buffer address */ |
| 2287 | __le64 hdr_addr; /* Header buffer address */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2288 | } read; |
| 2289 | struct { |
| 2290 | struct { |
Jesse Brandeburg | 7c6e0a4 | 2008-08-26 04:27:16 -0700 | [diff] [blame] | 2291 | union { |
| 2292 | __le32 data; |
| 2293 | struct { |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2294 | __le16 pkt_info; /* RSS, Pkt type */ |
| 2295 | __le16 hdr_info; /* Splithdr, hdrlen */ |
Jesse Brandeburg | 7c6e0a4 | 2008-08-26 04:27:16 -0700 | [diff] [blame] | 2296 | } hs_rss; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2297 | } lo_dword; |
| 2298 | union { |
Al Viro | 8327d00 | 2007-12-10 18:54:12 +0000 | [diff] [blame] | 2299 | __le32 rss; /* RSS Hash */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2300 | struct { |
Al Viro | 8327d00 | 2007-12-10 18:54:12 +0000 | [diff] [blame] | 2301 | __le16 ip_id; /* IP id */ |
Jesse Brandeburg | 9da09bb | 2008-08-26 04:26:59 -0700 | [diff] [blame] | 2302 | __le16 csum; /* Packet Checksum */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2303 | } csum_ip; |
| 2304 | } hi_dword; |
| 2305 | } lower; |
| 2306 | struct { |
Al Viro | 8327d00 | 2007-12-10 18:54:12 +0000 | [diff] [blame] | 2307 | __le32 status_error; /* ext status/error */ |
| 2308 | __le16 length; /* Packet length */ |
| 2309 | __le16 vlan; /* VLAN tag */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2310 | } upper; |
| 2311 | } wb; /* writeback */ |
| 2312 | }; |
| 2313 | |
| 2314 | /* Context descriptors */ |
| 2315 | struct ixgbe_adv_tx_context_desc { |
Al Viro | 8327d00 | 2007-12-10 18:54:12 +0000 | [diff] [blame] | 2316 | __le32 vlan_macip_lens; |
| 2317 | __le32 seqnum_seed; |
| 2318 | __le32 type_tucmd_mlhl; |
| 2319 | __le32 mss_l4len_idx; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2320 | }; |
| 2321 | |
| 2322 | /* Adv Transmit Descriptor Config Masks */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2323 | #define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buf length(bytes) */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2324 | #define IXGBE_ADVTXD_MAC_LINKSEC 0x00040000 /* Insert LinkSec */ |
Jacob Keller | 3a6a4ed | 2012-05-01 05:24:58 +0000 | [diff] [blame] | 2325 | #define IXGBE_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE 1588 Time Stamp */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2326 | #define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK 0x000003FF /* IPSec SA index */ |
| 2327 | #define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK 0x000001FF /* IPSec ESP length */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2328 | #define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */ |
| 2329 | #define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */ |
| 2330 | #define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ |
| 2331 | #define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */ |
| 2332 | #define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2333 | #define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2334 | #define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2335 | #define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */ |
| 2336 | #define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */ |
| 2337 | #define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ |
| 2338 | #define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2339 | #define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED pres in WB */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2340 | #define IXGBE_ADVTXD_STAT_RSV 0x0000000C /* STA Reserved */ |
| 2341 | #define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2342 | #define IXGBE_ADVTXD_CC 0x00000080 /* Check Context */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2343 | #define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */ |
| 2344 | #define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2345 | IXGBE_ADVTXD_POPTS_SHIFT) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2346 | #define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2347 | IXGBE_ADVTXD_POPTS_SHIFT) |
| 2348 | #define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */ |
| 2349 | #define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */ |
| 2350 | #define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */ |
| 2351 | #define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU */ |
| 2352 | #define IXGBE_ADVTXD_POPTS_RSV 0x00002000 /* POPTS Reserved */ |
| 2353 | #define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ |
| 2354 | #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ |
| 2355 | #define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */ |
| 2356 | #define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ |
| 2357 | #define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */ |
| 2358 | #define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */ |
| 2359 | #define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ |
| 2360 | #define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */ |
| 2361 | #define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /*Req requires Markers and CRC*/ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2362 | #define IXGBE_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */ |
| 2363 | #define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */ |
| 2364 | #define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */ |
Yi Zou | bff6617 | 2009-05-13 13:09:39 +0000 | [diff] [blame] | 2365 | #define IXGBE_ADVTXT_TUCMD_FCOE 0x00008000 /* FCoE Frame Type */ |
| 2366 | #define IXGBE_ADVTXD_FCOEF_EOF_MASK (0x3 << 10) /* FC EOF index */ |
| 2367 | #define IXGBE_ADVTXD_FCOEF_SOF ((1 << 2) << 10) /* FC SOF index */ |
| 2368 | #define IXGBE_ADVTXD_FCOEF_PARINC ((1 << 3) << 10) /* Rel_Off in F_CTL */ |
| 2369 | #define IXGBE_ADVTXD_FCOEF_ORIE ((1 << 4) << 10) /* Orientation: End */ |
| 2370 | #define IXGBE_ADVTXD_FCOEF_ORIS ((1 << 5) << 10) /* Orientation: Start */ |
| 2371 | #define IXGBE_ADVTXD_FCOEF_EOF_N (0x0 << 10) /* 00: EOFn */ |
| 2372 | #define IXGBE_ADVTXD_FCOEF_EOF_T (0x1 << 10) /* 01: EOFt */ |
| 2373 | #define IXGBE_ADVTXD_FCOEF_EOF_NI (0x2 << 10) /* 10: EOFni */ |
| 2374 | #define IXGBE_ADVTXD_FCOEF_EOF_A (0x3 << 10) /* 11: EOFa */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2375 | #define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ |
| 2376 | #define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2377 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2378 | /* Autonegotiation advertised speeds */ |
| 2379 | typedef u32 ixgbe_autoneg_advertised; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2380 | /* Link speed */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2381 | typedef u32 ixgbe_link_speed; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2382 | #define IXGBE_LINK_SPEED_UNKNOWN 0 |
| 2383 | #define IXGBE_LINK_SPEED_100_FULL 0x0008 |
| 2384 | #define IXGBE_LINK_SPEED_1GB_FULL 0x0020 |
| 2385 | #define IXGBE_LINK_SPEED_10GB_FULL 0x0080 |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2386 | #define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \ |
| 2387 | IXGBE_LINK_SPEED_10GB_FULL) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2388 | #define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \ |
| 2389 | IXGBE_LINK_SPEED_1GB_FULL | \ |
| 2390 | IXGBE_LINK_SPEED_10GB_FULL) |
| 2391 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2392 | |
| 2393 | /* Physical layer type */ |
| 2394 | typedef u32 ixgbe_physical_layer; |
| 2395 | #define IXGBE_PHYSICAL_LAYER_UNKNOWN 0 |
| 2396 | #define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x0001 |
| 2397 | #define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x0002 |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 2398 | #define IXGBE_PHYSICAL_LAYER_100BASE_TX 0x0004 |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2399 | #define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x0008 |
| 2400 | #define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x0010 |
| 2401 | #define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x0020 |
| 2402 | #define IXGBE_PHYSICAL_LAYER_10GBASE_SR 0x0040 |
| 2403 | #define IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x0080 |
| 2404 | #define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x0100 |
| 2405 | #define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200 |
| 2406 | #define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400 |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 2407 | #define IXGBE_PHYSICAL_LAYER_10GBASE_KR 0x0800 |
Peter P Waskiewicz Jr | 1fcf03e | 2009-05-17 20:58:04 +0000 | [diff] [blame] | 2408 | #define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x1000 |
Don Skidmore | ea0a04d | 2010-05-18 16:00:13 +0000 | [diff] [blame] | 2409 | #define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x2000 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2410 | |
John Fastabend | 9da712d | 2011-08-23 03:14:22 +0000 | [diff] [blame] | 2411 | /* Flow Control Data Sheet defined values |
| 2412 | * Calculation and defines taken from 802.1bb Annex O |
| 2413 | */ |
John Fastabend | 16b61be | 2010-11-16 19:26:44 -0800 | [diff] [blame] | 2414 | |
John Fastabend | 9da712d | 2011-08-23 03:14:22 +0000 | [diff] [blame] | 2415 | /* BitTimes (BT) conversion */ |
John Fastabend | 4f8a91a | 2012-03-28 11:42:45 +0000 | [diff] [blame] | 2416 | #define IXGBE_BT2KB(BT) ((BT + (8 * 1024 - 1)) / (8 * 1024)) |
John Fastabend | 9da712d | 2011-08-23 03:14:22 +0000 | [diff] [blame] | 2417 | #define IXGBE_B2BT(BT) (BT * 8) |
| 2418 | |
| 2419 | /* Calculate Delay to respond to PFC */ |
| 2420 | #define IXGBE_PFC_D 672 |
| 2421 | |
| 2422 | /* Calculate Cable Delay */ |
| 2423 | #define IXGBE_CABLE_DC 5556 /* Delay Copper */ |
| 2424 | #define IXGBE_CABLE_DO 5000 /* Delay Optical */ |
| 2425 | |
| 2426 | /* Calculate Interface Delay X540 */ |
| 2427 | #define IXGBE_PHY_DC 25600 /* Delay 10G BASET */ |
| 2428 | #define IXGBE_MAC_DC 8192 /* Delay Copper XAUI interface */ |
| 2429 | #define IXGBE_XAUI_DC (2 * 2048) /* Delay Copper Phy */ |
| 2430 | |
| 2431 | #define IXGBE_ID_X540 (IXGBE_MAC_DC + IXGBE_XAUI_DC + IXGBE_PHY_DC) |
| 2432 | |
| 2433 | /* Calculate Interface Delay 82598, 82599 */ |
| 2434 | #define IXGBE_PHY_D 12800 |
| 2435 | #define IXGBE_MAC_D 4096 |
| 2436 | #define IXGBE_XAUI_D (2 * 1024) |
| 2437 | |
| 2438 | #define IXGBE_ID (IXGBE_MAC_D + IXGBE_XAUI_D + IXGBE_PHY_D) |
| 2439 | |
| 2440 | /* Calculate Delay incurred from higher layer */ |
| 2441 | #define IXGBE_HD 6144 |
| 2442 | |
| 2443 | /* Calculate PCI Bus delay for low thresholds */ |
| 2444 | #define IXGBE_PCI_DELAY 10000 |
| 2445 | |
| 2446 | /* Calculate X540 delay value in bit times */ |
John Fastabend | 4f8a91a | 2012-03-28 11:42:45 +0000 | [diff] [blame] | 2447 | #define IXGBE_DV_X540(_max_frame_link, _max_frame_tc) \ |
| 2448 | ((36 * \ |
| 2449 | (IXGBE_B2BT(_max_frame_link) + \ |
| 2450 | IXGBE_PFC_D + \ |
| 2451 | (2 * IXGBE_CABLE_DC) + \ |
| 2452 | (2 * IXGBE_ID_X540) + \ |
| 2453 | IXGBE_HD) / 25 + 1) + \ |
| 2454 | 2 * IXGBE_B2BT(_max_frame_tc)) |
John Fastabend | 9da712d | 2011-08-23 03:14:22 +0000 | [diff] [blame] | 2455 | |
| 2456 | /* Calculate 82599, 82598 delay value in bit times */ |
John Fastabend | 4f8a91a | 2012-03-28 11:42:45 +0000 | [diff] [blame] | 2457 | #define IXGBE_DV(_max_frame_link, _max_frame_tc) \ |
| 2458 | ((36 * \ |
| 2459 | (IXGBE_B2BT(_max_frame_link) + \ |
| 2460 | IXGBE_PFC_D + \ |
| 2461 | (2 * IXGBE_CABLE_DC) + \ |
| 2462 | (2 * IXGBE_ID) + \ |
| 2463 | IXGBE_HD) / 25 + 1) + \ |
| 2464 | 2 * IXGBE_B2BT(_max_frame_tc)) |
John Fastabend | 9da712d | 2011-08-23 03:14:22 +0000 | [diff] [blame] | 2465 | |
| 2466 | /* Calculate low threshold delay values */ |
John Fastabend | 4f8a91a | 2012-03-28 11:42:45 +0000 | [diff] [blame] | 2467 | #define IXGBE_LOW_DV_X540(_max_frame_tc) \ |
| 2468 | (2 * IXGBE_B2BT(_max_frame_tc) + \ |
| 2469 | (36 * IXGBE_PCI_DELAY / 25) + 1) |
| 2470 | #define IXGBE_LOW_DV(_max_frame_tc) \ |
| 2471 | (2 * IXGBE_LOW_DV_X540(_max_frame_tc)) |
John Fastabend | 16b61be | 2010-11-16 19:26:44 -0800 | [diff] [blame] | 2472 | |
Peter P Waskiewicz Jr | bfde493 | 2009-06-04 16:01:06 +0000 | [diff] [blame] | 2473 | /* Software ATR hash keys */ |
Alexander Duyck | 905e4a4 | 2011-01-06 14:29:57 +0000 | [diff] [blame] | 2474 | #define IXGBE_ATR_BUCKET_HASH_KEY 0x3DAD14E2 |
| 2475 | #define IXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614 |
Peter P Waskiewicz Jr | bfde493 | 2009-06-04 16:01:06 +0000 | [diff] [blame] | 2476 | |
Alexander Duyck | 905e4a4 | 2011-01-06 14:29:57 +0000 | [diff] [blame] | 2477 | /* Software ATR input stream values and masks */ |
| 2478 | #define IXGBE_ATR_HASH_MASK 0x7fff |
Peter P Waskiewicz Jr | bfde493 | 2009-06-04 16:01:06 +0000 | [diff] [blame] | 2479 | #define IXGBE_ATR_L4TYPE_MASK 0x3 |
Peter P Waskiewicz Jr | bfde493 | 2009-06-04 16:01:06 +0000 | [diff] [blame] | 2480 | #define IXGBE_ATR_L4TYPE_UDP 0x1 |
| 2481 | #define IXGBE_ATR_L4TYPE_TCP 0x2 |
| 2482 | #define IXGBE_ATR_L4TYPE_SCTP 0x3 |
Alexander Duyck | 905e4a4 | 2011-01-06 14:29:57 +0000 | [diff] [blame] | 2483 | #define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4 |
| 2484 | enum ixgbe_atr_flow_type { |
| 2485 | IXGBE_ATR_FLOW_TYPE_IPV4 = 0x0, |
| 2486 | IXGBE_ATR_FLOW_TYPE_UDPV4 = 0x1, |
| 2487 | IXGBE_ATR_FLOW_TYPE_TCPV4 = 0x2, |
| 2488 | IXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3, |
| 2489 | IXGBE_ATR_FLOW_TYPE_IPV6 = 0x4, |
| 2490 | IXGBE_ATR_FLOW_TYPE_UDPV6 = 0x5, |
| 2491 | IXGBE_ATR_FLOW_TYPE_TCPV6 = 0x6, |
| 2492 | IXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7, |
| 2493 | }; |
Peter P Waskiewicz Jr | bfde493 | 2009-06-04 16:01:06 +0000 | [diff] [blame] | 2494 | |
| 2495 | /* Flow Director ATR input struct. */ |
Alexander Duyck | 905e4a4 | 2011-01-06 14:29:57 +0000 | [diff] [blame] | 2496 | union ixgbe_atr_input { |
| 2497 | /* |
| 2498 | * Byte layout in order, all values with MSB first: |
Peter P Waskiewicz Jr | bfde493 | 2009-06-04 16:01:06 +0000 | [diff] [blame] | 2499 | * |
Alexander Duyck | 905e4a4 | 2011-01-06 14:29:57 +0000 | [diff] [blame] | 2500 | * vm_pool - 1 byte |
| 2501 | * flow_type - 1 byte |
Peter P Waskiewicz Jr | bfde493 | 2009-06-04 16:01:06 +0000 | [diff] [blame] | 2502 | * vlan_id - 2 bytes |
| 2503 | * src_ip - 16 bytes |
| 2504 | * dst_ip - 16 bytes |
| 2505 | * src_port - 2 bytes |
| 2506 | * dst_port - 2 bytes |
| 2507 | * flex_bytes - 2 bytes |
Alexander Duyck | c04f6ca | 2011-05-11 07:18:36 +0000 | [diff] [blame] | 2508 | * bkt_hash - 2 bytes |
Peter P Waskiewicz Jr | bfde493 | 2009-06-04 16:01:06 +0000 | [diff] [blame] | 2509 | */ |
Alexander Duyck | 905e4a4 | 2011-01-06 14:29:57 +0000 | [diff] [blame] | 2510 | struct { |
| 2511 | u8 vm_pool; |
| 2512 | u8 flow_type; |
| 2513 | __be16 vlan_id; |
| 2514 | __be32 dst_ip[4]; |
| 2515 | __be32 src_ip[4]; |
| 2516 | __be16 src_port; |
| 2517 | __be16 dst_port; |
| 2518 | __be16 flex_bytes; |
Alexander Duyck | c04f6ca | 2011-05-11 07:18:36 +0000 | [diff] [blame] | 2519 | __be16 bkt_hash; |
Alexander Duyck | 905e4a4 | 2011-01-06 14:29:57 +0000 | [diff] [blame] | 2520 | } formatted; |
| 2521 | __be32 dword_stream[11]; |
Peter P Waskiewicz Jr | bfde493 | 2009-06-04 16:01:06 +0000 | [diff] [blame] | 2522 | }; |
| 2523 | |
Alexander Duyck | 6983052 | 2011-01-06 14:29:58 +0000 | [diff] [blame] | 2524 | /* Flow Director compressed ATR hash input struct */ |
| 2525 | union ixgbe_atr_hash_dword { |
| 2526 | struct { |
| 2527 | u8 vm_pool; |
| 2528 | u8 flow_type; |
| 2529 | __be16 vlan_id; |
| 2530 | } formatted; |
| 2531 | __be32 ip; |
| 2532 | struct { |
| 2533 | __be16 src; |
| 2534 | __be16 dst; |
| 2535 | } port; |
| 2536 | __be16 flex_bytes; |
| 2537 | __be32 dword; |
| 2538 | }; |
| 2539 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2540 | enum ixgbe_eeprom_type { |
| 2541 | ixgbe_eeprom_uninitialized = 0, |
| 2542 | ixgbe_eeprom_spi, |
Don Skidmore | fe15e8e | 2010-11-16 19:27:16 -0800 | [diff] [blame] | 2543 | ixgbe_flash, |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2544 | ixgbe_eeprom_none /* No NVM support */ |
| 2545 | }; |
| 2546 | |
| 2547 | enum ixgbe_mac_type { |
| 2548 | ixgbe_mac_unknown = 0, |
| 2549 | ixgbe_mac_82598EB, |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2550 | ixgbe_mac_82599EB, |
Don Skidmore | fe15e8e | 2010-11-16 19:27:16 -0800 | [diff] [blame] | 2551 | ixgbe_mac_X540, |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2552 | ixgbe_num_macs |
| 2553 | }; |
| 2554 | |
| 2555 | enum ixgbe_phy_type { |
| 2556 | ixgbe_phy_unknown = 0, |
Emil Tantilov | 21cc5b4 | 2011-02-12 10:52:07 +0000 | [diff] [blame] | 2557 | ixgbe_phy_none, |
Jesse Brandeburg | 0befdb3 | 2008-10-31 00:46:40 -0700 | [diff] [blame] | 2558 | ixgbe_phy_tn, |
Don Skidmore | fe15e8e | 2010-11-16 19:27:16 -0800 | [diff] [blame] | 2559 | ixgbe_phy_aq, |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2560 | ixgbe_phy_cu_unknown, |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2561 | ixgbe_phy_qt, |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2562 | ixgbe_phy_xaui, |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 2563 | ixgbe_phy_nl, |
Don Skidmore | ea0a04d | 2010-05-18 16:00:13 +0000 | [diff] [blame] | 2564 | ixgbe_phy_sfp_passive_tyco, |
| 2565 | ixgbe_phy_sfp_passive_unknown, |
| 2566 | ixgbe_phy_sfp_active_unknown, |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2567 | ixgbe_phy_sfp_avago, |
| 2568 | ixgbe_phy_sfp_ftl, |
Don Skidmore | ea0a04d | 2010-05-18 16:00:13 +0000 | [diff] [blame] | 2569 | ixgbe_phy_sfp_ftl_active, |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2570 | ixgbe_phy_sfp_unknown, |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2571 | ixgbe_phy_sfp_intel, |
Waskiewicz Jr, Peter P | fa466e9 | 2009-04-23 11:31:37 +0000 | [diff] [blame] | 2572 | ixgbe_phy_sfp_unsupported, |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2573 | ixgbe_phy_generic |
| 2574 | }; |
| 2575 | |
| 2576 | /* |
| 2577 | * SFP+ module type IDs: |
| 2578 | * |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2579 | * ID Module Type |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2580 | * ============= |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2581 | * 0 SFP_DA_CU |
| 2582 | * 1 SFP_SR |
| 2583 | * 2 SFP_LR |
| 2584 | * 3 SFP_DA_CU_CORE0 - 82599-specific |
| 2585 | * 4 SFP_DA_CU_CORE1 - 82599-specific |
| 2586 | * 5 SFP_SR/LR_CORE0 - 82599-specific |
| 2587 | * 6 SFP_SR/LR_CORE1 - 82599-specific |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2588 | */ |
| 2589 | enum ixgbe_sfp_type { |
| 2590 | ixgbe_sfp_type_da_cu = 0, |
| 2591 | ixgbe_sfp_type_sr = 1, |
| 2592 | ixgbe_sfp_type_lr = 2, |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2593 | ixgbe_sfp_type_da_cu_core0 = 3, |
| 2594 | ixgbe_sfp_type_da_cu_core1 = 4, |
| 2595 | ixgbe_sfp_type_srlr_core0 = 5, |
| 2596 | ixgbe_sfp_type_srlr_core1 = 6, |
Don Skidmore | ea0a04d | 2010-05-18 16:00:13 +0000 | [diff] [blame] | 2597 | ixgbe_sfp_type_da_act_lmt_core0 = 7, |
| 2598 | ixgbe_sfp_type_da_act_lmt_core1 = 8, |
Don Skidmore | cb836a9 | 2010-06-29 18:30:59 +0000 | [diff] [blame] | 2599 | ixgbe_sfp_type_1g_cu_core0 = 9, |
| 2600 | ixgbe_sfp_type_1g_cu_core1 = 10, |
Jacob Keller | a49fda3 | 2012-06-08 06:59:09 +0000 | [diff] [blame] | 2601 | ixgbe_sfp_type_1g_sx_core0 = 11, |
| 2602 | ixgbe_sfp_type_1g_sx_core1 = 12, |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 2603 | ixgbe_sfp_type_not_present = 0xFFFE, |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2604 | ixgbe_sfp_type_unknown = 0xFFFF |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2605 | }; |
| 2606 | |
| 2607 | enum ixgbe_media_type { |
| 2608 | ixgbe_media_type_unknown = 0, |
| 2609 | ixgbe_media_type_fiber, |
Don Skidmore | 4f6290c | 2011-05-14 06:36:35 +0000 | [diff] [blame] | 2610 | ixgbe_media_type_fiber_lco, |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2611 | ixgbe_media_type_copper, |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2612 | ixgbe_media_type_backplane, |
Peter P Waskiewicz Jr | 6b1be19 | 2009-09-14 07:48:10 +0000 | [diff] [blame] | 2613 | ixgbe_media_type_cx4, |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2614 | ixgbe_media_type_virtual |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2615 | }; |
| 2616 | |
| 2617 | /* Flow Control Settings */ |
Peter P Waskiewicz Jr | 0ecc061 | 2009-02-06 21:46:54 -0800 | [diff] [blame] | 2618 | enum ixgbe_fc_mode { |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2619 | ixgbe_fc_none = 0, |
| 2620 | ixgbe_fc_rx_pause, |
| 2621 | ixgbe_fc_tx_pause, |
| 2622 | ixgbe_fc_full, |
| 2623 | ixgbe_fc_default |
| 2624 | }; |
| 2625 | |
Don Skidmore | cd7e1f0 | 2009-10-08 15:36:22 +0000 | [diff] [blame] | 2626 | /* Smart Speed Settings */ |
| 2627 | #define IXGBE_SMARTSPEED_MAX_RETRIES 3 |
| 2628 | enum ixgbe_smart_speed { |
| 2629 | ixgbe_smart_speed_auto = 0, |
| 2630 | ixgbe_smart_speed_on, |
| 2631 | ixgbe_smart_speed_off |
| 2632 | }; |
| 2633 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2634 | /* PCI bus types */ |
| 2635 | enum ixgbe_bus_type { |
| 2636 | ixgbe_bus_type_unknown = 0, |
| 2637 | ixgbe_bus_type_pci, |
| 2638 | ixgbe_bus_type_pcix, |
| 2639 | ixgbe_bus_type_pci_express, |
| 2640 | ixgbe_bus_type_reserved |
| 2641 | }; |
| 2642 | |
| 2643 | /* PCI bus speeds */ |
| 2644 | enum ixgbe_bus_speed { |
| 2645 | ixgbe_bus_speed_unknown = 0, |
Emil Tantilov | 26d6899 | 2011-02-17 11:34:53 +0000 | [diff] [blame] | 2646 | ixgbe_bus_speed_33 = 33, |
| 2647 | ixgbe_bus_speed_66 = 66, |
| 2648 | ixgbe_bus_speed_100 = 100, |
| 2649 | ixgbe_bus_speed_120 = 120, |
| 2650 | ixgbe_bus_speed_133 = 133, |
| 2651 | ixgbe_bus_speed_2500 = 2500, |
| 2652 | ixgbe_bus_speed_5000 = 5000, |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2653 | ixgbe_bus_speed_reserved |
| 2654 | }; |
| 2655 | |
| 2656 | /* PCI bus widths */ |
| 2657 | enum ixgbe_bus_width { |
| 2658 | ixgbe_bus_width_unknown = 0, |
Emil Tantilov | 26d6899 | 2011-02-17 11:34:53 +0000 | [diff] [blame] | 2659 | ixgbe_bus_width_pcie_x1 = 1, |
| 2660 | ixgbe_bus_width_pcie_x2 = 2, |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2661 | ixgbe_bus_width_pcie_x4 = 4, |
| 2662 | ixgbe_bus_width_pcie_x8 = 8, |
Emil Tantilov | 26d6899 | 2011-02-17 11:34:53 +0000 | [diff] [blame] | 2663 | ixgbe_bus_width_32 = 32, |
| 2664 | ixgbe_bus_width_64 = 64, |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2665 | ixgbe_bus_width_reserved |
| 2666 | }; |
| 2667 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2668 | struct ixgbe_addr_filter_info { |
| 2669 | u32 num_mc_addrs; |
| 2670 | u32 rar_used_count; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2671 | u32 mta_in_use; |
Christopher Leech | 2c5645c | 2008-08-26 04:27:02 -0700 | [diff] [blame] | 2672 | u32 overflow_promisc; |
Emil Tantilov | e433ea1 | 2010-05-13 17:33:00 +0000 | [diff] [blame] | 2673 | bool uc_set_promisc; |
Christopher Leech | 2c5645c | 2008-08-26 04:27:02 -0700 | [diff] [blame] | 2674 | bool user_set_promisc; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2675 | }; |
| 2676 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2677 | /* Bus parameters */ |
| 2678 | struct ixgbe_bus_info { |
| 2679 | enum ixgbe_bus_speed speed; |
| 2680 | enum ixgbe_bus_width width; |
| 2681 | enum ixgbe_bus_type type; |
| 2682 | |
| 2683 | u16 func; |
| 2684 | u16 lan_id; |
| 2685 | }; |
| 2686 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2687 | /* Flow control parameters */ |
| 2688 | struct ixgbe_fc_info { |
John Fastabend | 9da712d | 2011-08-23 03:14:22 +0000 | [diff] [blame] | 2689 | u32 high_water[MAX_TRAFFIC_CLASS]; /* Flow Control High-water */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2690 | u32 low_water; /* Flow Control Low-water */ |
| 2691 | u16 pause_time; /* Flow Control Pause timer */ |
| 2692 | bool send_xon; /* Flow control send XON */ |
| 2693 | bool strict_ieee; /* Strict IEEE mode */ |
Mallikarjuna R Chilakala | 620fa03 | 2009-06-04 11:11:13 +0000 | [diff] [blame] | 2694 | bool disable_fc_autoneg; /* Do not autonegotiate FC */ |
| 2695 | bool fc_was_autonegged; /* Is current_mode the result of autonegging? */ |
Peter P Waskiewicz Jr | 0ecc061 | 2009-02-06 21:46:54 -0800 | [diff] [blame] | 2696 | enum ixgbe_fc_mode current_mode; /* FC mode in effect */ |
| 2697 | enum ixgbe_fc_mode requested_mode; /* FC mode requested by caller */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2698 | }; |
| 2699 | |
| 2700 | /* Statistics counters collected by the MAC */ |
| 2701 | struct ixgbe_hw_stats { |
| 2702 | u64 crcerrs; |
| 2703 | u64 illerrc; |
| 2704 | u64 errbc; |
| 2705 | u64 mspdc; |
| 2706 | u64 mpctotal; |
| 2707 | u64 mpc[8]; |
| 2708 | u64 mlfc; |
| 2709 | u64 mrfc; |
| 2710 | u64 rlec; |
| 2711 | u64 lxontxc; |
| 2712 | u64 lxonrxc; |
| 2713 | u64 lxofftxc; |
| 2714 | u64 lxoffrxc; |
| 2715 | u64 pxontxc[8]; |
| 2716 | u64 pxonrxc[8]; |
| 2717 | u64 pxofftxc[8]; |
| 2718 | u64 pxoffrxc[8]; |
| 2719 | u64 prc64; |
| 2720 | u64 prc127; |
| 2721 | u64 prc255; |
| 2722 | u64 prc511; |
| 2723 | u64 prc1023; |
| 2724 | u64 prc1522; |
| 2725 | u64 gprc; |
| 2726 | u64 bprc; |
| 2727 | u64 mprc; |
| 2728 | u64 gptc; |
| 2729 | u64 gorc; |
| 2730 | u64 gotc; |
| 2731 | u64 rnbc[8]; |
| 2732 | u64 ruc; |
| 2733 | u64 rfc; |
| 2734 | u64 roc; |
| 2735 | u64 rjc; |
| 2736 | u64 mngprc; |
| 2737 | u64 mngpdc; |
| 2738 | u64 mngptc; |
| 2739 | u64 tor; |
| 2740 | u64 tpr; |
| 2741 | u64 tpt; |
| 2742 | u64 ptc64; |
| 2743 | u64 ptc127; |
| 2744 | u64 ptc255; |
| 2745 | u64 ptc511; |
| 2746 | u64 ptc1023; |
| 2747 | u64 ptc1522; |
| 2748 | u64 mptc; |
| 2749 | u64 bptc; |
| 2750 | u64 xec; |
| 2751 | u64 rqsmr[16]; |
| 2752 | u64 tqsmr[8]; |
| 2753 | u64 qprc[16]; |
| 2754 | u64 qptc[16]; |
| 2755 | u64 qbrc[16]; |
| 2756 | u64 qbtc[16]; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2757 | u64 qprdc[16]; |
| 2758 | u64 pxon2offc[8]; |
| 2759 | u64 fdirustat_add; |
| 2760 | u64 fdirustat_remove; |
| 2761 | u64 fdirfstat_fadd; |
| 2762 | u64 fdirfstat_fremove; |
| 2763 | u64 fdirmatch; |
| 2764 | u64 fdirmiss; |
Yi Zou | 6d45522 | 2009-05-13 13:12:16 +0000 | [diff] [blame] | 2765 | u64 fccrc; |
| 2766 | u64 fcoerpdc; |
| 2767 | u64 fcoeprc; |
| 2768 | u64 fcoeptc; |
| 2769 | u64 fcoedwrc; |
| 2770 | u64 fcoedwtc; |
Amir Hanania | 7b859eb | 2011-08-31 02:07:55 +0000 | [diff] [blame] | 2771 | u64 fcoe_noddp; |
| 2772 | u64 fcoe_noddp_ext_buff; |
Emil Tantilov | 58f6bcf | 2011-04-21 08:43:43 +0000 | [diff] [blame] | 2773 | u64 b2ospc; |
| 2774 | u64 b2ogprc; |
| 2775 | u64 o2bgptc; |
| 2776 | u64 o2bspc; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2777 | }; |
| 2778 | |
| 2779 | /* forward declaration */ |
| 2780 | struct ixgbe_hw; |
| 2781 | |
Christopher Leech | 2c5645c | 2008-08-26 04:27:02 -0700 | [diff] [blame] | 2782 | /* iterator type for walking multicast address lists */ |
| 2783 | typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr, |
| 2784 | u32 *vmdq); |
| 2785 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2786 | /* Function pointer table */ |
| 2787 | struct ixgbe_eeprom_operations { |
| 2788 | s32 (*init_params)(struct ixgbe_hw *); |
| 2789 | s32 (*read)(struct ixgbe_hw *, u16, u16 *); |
Emil Tantilov | 68c7005 | 2011-04-20 08:49:06 +0000 | [diff] [blame] | 2790 | s32 (*read_buffer)(struct ixgbe_hw *, u16, u16, u16 *); |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2791 | s32 (*write)(struct ixgbe_hw *, u16, u16); |
Emil Tantilov | 68c7005 | 2011-04-20 08:49:06 +0000 | [diff] [blame] | 2792 | s32 (*write_buffer)(struct ixgbe_hw *, u16, u16, u16 *); |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2793 | s32 (*validate_checksum)(struct ixgbe_hw *, u16 *); |
| 2794 | s32 (*update_checksum)(struct ixgbe_hw *); |
Don Skidmore | a391f1d | 2010-11-16 19:27:15 -0800 | [diff] [blame] | 2795 | u16 (*calc_checksum)(struct ixgbe_hw *); |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2796 | }; |
| 2797 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2798 | struct ixgbe_mac_operations { |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2799 | s32 (*init_hw)(struct ixgbe_hw *); |
| 2800 | s32 (*reset_hw)(struct ixgbe_hw *); |
| 2801 | s32 (*start_hw)(struct ixgbe_hw *); |
| 2802 | s32 (*clear_hw_cntrs)(struct ixgbe_hw *); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2803 | enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2804 | u32 (*get_supported_physical_layer)(struct ixgbe_hw *); |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2805 | s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *); |
PJ Waskiewicz | 0365e6e | 2009-05-17 12:32:25 +0000 | [diff] [blame] | 2806 | s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *); |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 2807 | s32 (*get_device_caps)(struct ixgbe_hw *, u16 *); |
Yi Zou | 383ff34 | 2009-10-28 18:23:57 +0000 | [diff] [blame] | 2808 | s32 (*get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *); |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2809 | s32 (*stop_adapter)(struct ixgbe_hw *); |
| 2810 | s32 (*get_bus_info)(struct ixgbe_hw *); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2811 | void (*set_lan_id)(struct ixgbe_hw *); |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2812 | s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*); |
| 2813 | s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2814 | s32 (*setup_sfp)(struct ixgbe_hw *); |
Atita Shirwaikar | d2f5e7f | 2012-02-18 02:58:58 +0000 | [diff] [blame] | 2815 | s32 (*disable_rx_buff)(struct ixgbe_hw *); |
| 2816 | s32 (*enable_rx_buff)(struct ixgbe_hw *); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2817 | s32 (*enable_rx_dma)(struct ixgbe_hw *, u32); |
Don Skidmore | 5e65510 | 2011-02-25 01:58:04 +0000 | [diff] [blame] | 2818 | s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u16); |
| 2819 | void (*release_swfw_sync)(struct ixgbe_hw *, u16); |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2820 | |
| 2821 | /* Link */ |
Peter Waskiewicz | 61fac74 | 2010-04-27 00:38:15 +0000 | [diff] [blame] | 2822 | void (*disable_tx_laser)(struct ixgbe_hw *); |
| 2823 | void (*enable_tx_laser)(struct ixgbe_hw *); |
Mallikarjuna R Chilakala | 1097cd1 | 2010-03-18 14:34:52 +0000 | [diff] [blame] | 2824 | void (*flap_tx_laser)(struct ixgbe_hw *); |
Mallikarjuna R Chilakala | 8620a10 | 2009-09-01 13:49:35 +0000 | [diff] [blame] | 2825 | s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool, bool); |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2826 | s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool); |
| 2827 | s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *, |
| 2828 | bool *); |
| 2829 | |
John Fastabend | 80605c65 | 2011-05-02 12:34:10 +0000 | [diff] [blame] | 2830 | /* Packet Buffer Manipulation */ |
| 2831 | void (*set_rxpba)(struct ixgbe_hw *, int, u32, int); |
| 2832 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2833 | /* LED */ |
| 2834 | s32 (*led_on)(struct ixgbe_hw *, u32); |
| 2835 | s32 (*led_off)(struct ixgbe_hw *, u32); |
| 2836 | s32 (*blink_led_start)(struct ixgbe_hw *, u32); |
| 2837 | s32 (*blink_led_stop)(struct ixgbe_hw *, u32); |
| 2838 | |
| 2839 | /* RAR, Multicast, VLAN */ |
| 2840 | s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32); |
| 2841 | s32 (*clear_rar)(struct ixgbe_hw *, u32); |
| 2842 | s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32); |
Alexander Duyck | 7fa7c9d | 2012-05-05 05:32:52 +0000 | [diff] [blame] | 2843 | s32 (*set_vmdq_san_mac)(struct ixgbe_hw *, u32); |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2844 | s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32); |
| 2845 | s32 (*init_rx_addrs)(struct ixgbe_hw *); |
Jiri Pirko | 2853eb8 | 2010-03-23 22:58:01 +0000 | [diff] [blame] | 2846 | s32 (*update_mc_addr_list)(struct ixgbe_hw *, struct net_device *); |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2847 | s32 (*enable_mc)(struct ixgbe_hw *); |
| 2848 | s32 (*disable_mc)(struct ixgbe_hw *); |
| 2849 | s32 (*clear_vfta)(struct ixgbe_hw *); |
| 2850 | s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool); |
| 2851 | s32 (*init_uta_tables)(struct ixgbe_hw *); |
Greg Rose | a985b6c3 | 2010-11-18 03:02:52 +0000 | [diff] [blame] | 2852 | void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int); |
| 2853 | void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int); |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2854 | |
| 2855 | /* Flow Control */ |
Alexander Duyck | 041441d | 2012-04-19 17:48:48 +0000 | [diff] [blame] | 2856 | s32 (*fc_enable)(struct ixgbe_hw *); |
Emil Tantilov | 9612de9 | 2011-05-07 07:40:20 +0000 | [diff] [blame] | 2857 | |
| 2858 | /* Manageability interface */ |
| 2859 | s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8); |
Don Skidmore | e1ea915 | 2012-02-17 02:38:58 +0000 | [diff] [blame] | 2860 | s32 (*get_thermal_sensor_data)(struct ixgbe_hw *); |
| 2861 | s32 (*init_thermal_sensor_thresh)(struct ixgbe_hw *hw); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2862 | }; |
| 2863 | |
| 2864 | struct ixgbe_phy_operations { |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2865 | s32 (*identify)(struct ixgbe_hw *); |
| 2866 | s32 (*identify_sfp)(struct ixgbe_hw *); |
PJ Waskiewicz | 04f165e | 2009-04-09 22:27:57 +0000 | [diff] [blame] | 2867 | s32 (*init)(struct ixgbe_hw *); |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2868 | s32 (*reset)(struct ixgbe_hw *); |
| 2869 | s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *); |
| 2870 | s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16); |
Auke Kok | 3957d63 | 2007-10-31 15:22:10 -0700 | [diff] [blame] | 2871 | s32 (*setup_link)(struct ixgbe_hw *); |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2872 | s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool, |
| 2873 | bool); |
Jesse Brandeburg | 0befdb3 | 2008-10-31 00:46:40 -0700 | [diff] [blame] | 2874 | s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *); |
| 2875 | s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *); |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2876 | s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *); |
| 2877 | s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8); |
| 2878 | s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *); |
| 2879 | s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8); |
Mallikarjuna R Chilakala | 119fc60 | 2010-05-20 23:07:06 -0700 | [diff] [blame] | 2880 | s32 (*check_overtemp)(struct ixgbe_hw *); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2881 | }; |
| 2882 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2883 | struct ixgbe_eeprom_info { |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2884 | struct ixgbe_eeprom_operations ops; |
| 2885 | enum ixgbe_eeprom_type type; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2886 | u32 semaphore_delay; |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2887 | u16 word_size; |
| 2888 | u16 address_bits; |
Emil Tantilov | 68c7005 | 2011-04-20 08:49:06 +0000 | [diff] [blame] | 2889 | u16 word_page_size; |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2890 | }; |
| 2891 | |
Emil Tantilov | a4297dc | 2011-02-14 08:45:13 +0000 | [diff] [blame] | 2892 | #define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED 0x01 |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2893 | struct ixgbe_mac_info { |
| 2894 | struct ixgbe_mac_operations ops; |
| 2895 | enum ixgbe_mac_type type; |
Joe Perches | ea99d83 | 2011-09-20 15:32:52 +0000 | [diff] [blame] | 2896 | u8 addr[ETH_ALEN]; |
| 2897 | u8 perm_addr[ETH_ALEN]; |
| 2898 | u8 san_addr[ETH_ALEN]; |
Yi Zou | 383ff34 | 2009-10-28 18:23:57 +0000 | [diff] [blame] | 2899 | /* prefix for World Wide Node Name (WWNN) */ |
| 2900 | u16 wwnn_prefix; |
| 2901 | /* prefix for World Wide Port Name (WWPN) */ |
| 2902 | u16 wwpn_prefix; |
Emil Tantilov | 7116130 | 2012-03-22 03:00:29 +0000 | [diff] [blame] | 2903 | u16 max_msix_vectors; |
Emil Tantilov | 80960ab | 2011-02-18 08:58:27 +0000 | [diff] [blame] | 2904 | #define IXGBE_MAX_MTA 128 |
| 2905 | u32 mta_shadow[IXGBE_MAX_MTA]; |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2906 | s32 mc_filter_type; |
| 2907 | u32 mcft_size; |
| 2908 | u32 vft_size; |
| 2909 | u32 num_rar_entries; |
Mallikarjuna R Chilakala | 21ce849 | 2010-05-13 17:33:41 +0000 | [diff] [blame] | 2910 | u32 rar_highwater; |
John Fastabend | e09ad23 | 2011-04-04 04:29:41 +0000 | [diff] [blame] | 2911 | u32 rx_pb_size; |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2912 | u32 max_tx_queues; |
| 2913 | u32 max_rx_queues; |
Peter P Waskiewicz Jr | 3201d31 | 2009-02-05 23:54:21 -0800 | [diff] [blame] | 2914 | u32 orig_autoc; |
| 2915 | u32 orig_autoc2; |
| 2916 | bool orig_link_settings_stored; |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 2917 | bool autotry_restart; |
Emil Tantilov | a4297dc | 2011-02-14 08:45:13 +0000 | [diff] [blame] | 2918 | u8 flags; |
Alexander Duyck | 7fa7c9d | 2012-05-05 05:32:52 +0000 | [diff] [blame] | 2919 | u8 san_mac_rar_index; |
Don Skidmore | e1ea915 | 2012-02-17 02:38:58 +0000 | [diff] [blame] | 2920 | struct ixgbe_thermal_sensor_data thermal_sensor_data; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2921 | }; |
| 2922 | |
| 2923 | struct ixgbe_phy_info { |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2924 | struct ixgbe_phy_operations ops; |
Ben Hutchings | 6b73e10 | 2009-04-29 08:08:58 +0000 | [diff] [blame] | 2925 | struct mdio_if_info mdio; |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2926 | enum ixgbe_phy_type type; |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2927 | u32 id; |
| 2928 | enum ixgbe_sfp_type sfp_type; |
PJ Waskiewicz | 553b449 | 2009-04-09 22:28:15 +0000 | [diff] [blame] | 2929 | bool sfp_setup_needed; |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2930 | u32 revision; |
| 2931 | enum ixgbe_media_type media_type; |
| 2932 | bool reset_disable; |
| 2933 | ixgbe_autoneg_advertised autoneg_advertised; |
Don Skidmore | cd7e1f0 | 2009-10-08 15:36:22 +0000 | [diff] [blame] | 2934 | enum ixgbe_smart_speed smart_speed; |
| 2935 | bool smart_speed_active; |
Peter P Waskiewicz Jr | 0ecc061 | 2009-02-06 21:46:54 -0800 | [diff] [blame] | 2936 | bool multispeed_fiber; |
Mallikarjuna R Chilakala | 119fc60 | 2010-05-20 23:07:06 -0700 | [diff] [blame] | 2937 | bool reset_if_overtemp; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2938 | }; |
| 2939 | |
Greg Rose | 7f87047 | 2010-01-09 02:25:29 +0000 | [diff] [blame] | 2940 | #include "ixgbe_mbx.h" |
| 2941 | |
| 2942 | struct ixgbe_mbx_operations { |
| 2943 | s32 (*init_params)(struct ixgbe_hw *hw); |
| 2944 | s32 (*read)(struct ixgbe_hw *, u32 *, u16, u16); |
| 2945 | s32 (*write)(struct ixgbe_hw *, u32 *, u16, u16); |
| 2946 | s32 (*read_posted)(struct ixgbe_hw *, u32 *, u16, u16); |
| 2947 | s32 (*write_posted)(struct ixgbe_hw *, u32 *, u16, u16); |
| 2948 | s32 (*check_for_msg)(struct ixgbe_hw *, u16); |
| 2949 | s32 (*check_for_ack)(struct ixgbe_hw *, u16); |
| 2950 | s32 (*check_for_rst)(struct ixgbe_hw *, u16); |
| 2951 | }; |
| 2952 | |
| 2953 | struct ixgbe_mbx_stats { |
| 2954 | u32 msgs_tx; |
| 2955 | u32 msgs_rx; |
| 2956 | |
| 2957 | u32 acks; |
| 2958 | u32 reqs; |
| 2959 | u32 rsts; |
| 2960 | }; |
| 2961 | |
| 2962 | struct ixgbe_mbx_info { |
| 2963 | struct ixgbe_mbx_operations ops; |
| 2964 | struct ixgbe_mbx_stats stats; |
| 2965 | u32 timeout; |
| 2966 | u32 usec_delay; |
| 2967 | u32 v2p_mailbox; |
| 2968 | u16 size; |
| 2969 | }; |
| 2970 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2971 | struct ixgbe_hw { |
| 2972 | u8 __iomem *hw_addr; |
| 2973 | void *back; |
| 2974 | struct ixgbe_mac_info mac; |
| 2975 | struct ixgbe_addr_filter_info addr_ctrl; |
| 2976 | struct ixgbe_fc_info fc; |
| 2977 | struct ixgbe_phy_info phy; |
| 2978 | struct ixgbe_eeprom_info eeprom; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2979 | struct ixgbe_bus_info bus; |
Greg Rose | 7f87047 | 2010-01-09 02:25:29 +0000 | [diff] [blame] | 2980 | struct ixgbe_mbx_info mbx; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2981 | u16 device_id; |
| 2982 | u16 vendor_id; |
| 2983 | u16 subsystem_device_id; |
| 2984 | u16 subsystem_vendor_id; |
| 2985 | u8 revision_id; |
| 2986 | bool adapter_stopped; |
Don Skidmore | fe15e8e | 2010-11-16 19:27:16 -0800 | [diff] [blame] | 2987 | bool force_full_reset; |
Peter P Waskiewicz Jr | 8ef78ad | 2012-02-01 09:19:21 +0000 | [diff] [blame] | 2988 | bool allow_unsupported_sfp; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 2989 | }; |
| 2990 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2991 | struct ixgbe_info { |
| 2992 | enum ixgbe_mac_type mac; |
| 2993 | s32 (*get_invariants)(struct ixgbe_hw *); |
| 2994 | struct ixgbe_mac_operations *mac_ops; |
| 2995 | struct ixgbe_eeprom_operations *eeprom_ops; |
| 2996 | struct ixgbe_phy_operations *phy_ops; |
Greg Rose | 7f87047 | 2010-01-09 02:25:29 +0000 | [diff] [blame] | 2997 | struct ixgbe_mbx_operations *mbx_ops; |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 2998 | }; |
| 2999 | |
| 3000 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 3001 | /* Error Codes */ |
| 3002 | #define IXGBE_ERR_EEPROM -1 |
| 3003 | #define IXGBE_ERR_EEPROM_CHECKSUM -2 |
| 3004 | #define IXGBE_ERR_PHY -3 |
| 3005 | #define IXGBE_ERR_CONFIG -4 |
| 3006 | #define IXGBE_ERR_PARAM -5 |
| 3007 | #define IXGBE_ERR_MAC_TYPE -6 |
| 3008 | #define IXGBE_ERR_UNKNOWN_PHY -7 |
| 3009 | #define IXGBE_ERR_LINK_SETUP -8 |
| 3010 | #define IXGBE_ERR_ADAPTER_STOPPED -9 |
| 3011 | #define IXGBE_ERR_INVALID_MAC_ADDR -10 |
| 3012 | #define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11 |
| 3013 | #define IXGBE_ERR_MASTER_REQUESTS_PENDING -12 |
| 3014 | #define IXGBE_ERR_INVALID_LINK_SETTINGS -13 |
| 3015 | #define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14 |
| 3016 | #define IXGBE_ERR_RESET_FAILED -15 |
| 3017 | #define IXGBE_ERR_SWFW_SYNC -16 |
| 3018 | #define IXGBE_ERR_PHY_ADDR_INVALID -17 |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 3019 | #define IXGBE_ERR_I2C -18 |
| 3020 | #define IXGBE_ERR_SFP_NOT_SUPPORTED -19 |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 3021 | #define IXGBE_ERR_SFP_NOT_PRESENT -20 |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 3022 | #define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT -21 |
Mallikarjuna R Chilakala | 21ce849 | 2010-05-13 17:33:41 +0000 | [diff] [blame] | 3023 | #define IXGBE_ERR_NO_SAN_ADDR_PTR -22 |
Peter P Waskiewicz Jr | bfde493 | 2009-06-04 16:01:06 +0000 | [diff] [blame] | 3024 | #define IXGBE_ERR_FDIR_REINIT_FAILED -23 |
Peter P Waskiewicz Jr | 794caeb | 2009-06-04 16:02:24 +0000 | [diff] [blame] | 3025 | #define IXGBE_ERR_EEPROM_VERSION -24 |
Mallikarjuna R Chilakala | 21ce849 | 2010-05-13 17:33:41 +0000 | [diff] [blame] | 3026 | #define IXGBE_ERR_NO_SPACE -25 |
Mallikarjuna R Chilakala | 119fc60 | 2010-05-20 23:07:06 -0700 | [diff] [blame] | 3027 | #define IXGBE_ERR_OVERTEMP -26 |
Emil Tantilov | 0b0c2b3 | 2011-02-26 06:40:16 +0000 | [diff] [blame] | 3028 | #define IXGBE_ERR_FC_NOT_NEGOTIATED -27 |
| 3029 | #define IXGBE_ERR_FC_NOT_SUPPORTED -28 |
Don Skidmore | a7f5a5f | 2010-12-03 13:23:30 +0000 | [diff] [blame] | 3030 | #define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE -30 |
Don Skidmore | 289700db | 2010-12-03 03:32:58 +0000 | [diff] [blame] | 3031 | #define IXGBE_ERR_PBA_SECTION -31 |
| 3032 | #define IXGBE_ERR_INVALID_ARGUMENT -32 |
Emil Tantilov | 9612de9 | 2011-05-07 07:40:20 +0000 | [diff] [blame] | 3033 | #define IXGBE_ERR_HOST_INTERFACE_COMMAND -33 |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 3034 | #define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF |
| 3035 | |
| 3036 | #endif /* _IXGBE_TYPE_H_ */ |